JPH04120591A - Liquid crystal display device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of a picture quality by delaying the generation timing of an output enable signal by the time corresponding to a fall characteristic of a gate driving signal, and generating a voltage fluctuation of a drain driving signal while a picture element display is being executed. CONSTITUTION:Plural pieces of drain electrodes D1 - DM are divided into plural groups, drain drivers 12a, 12b are divided at every divided group thereof, and a drain driving signal generating part 17 is constituted so that an output enable signal is inputted to each of them by a separate timing. In such a state, it is driven so that the output enable signal is turned off after a gate driving signal is turned off by delaying a generation timing of the output enable signal at every group by the time corresponding to a fall characteristic of the gate driving signal of a gate driving signal generating part 18 applied to gates G1 - GN of a thin film transistor. In such a way, a voltage fluctuation of the drain driving signal is generated while a picture element display is not being executed, and deterioration of a picture quality is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to improving the image quality of a liquid crystal display device.

[Conventional technology]

FIG. 2 is a block diagram showing the configuration of a conventional liquid crystal display device. As shown in the figure, a liquid crystal panel of a conventional liquid crystal display device includes a liquid crystal layer (not shown), pixel electrodes (not shown) arranged in a matrix, and drive signals applied to the pixel electrodes. Control thin film transistors (not shown), drain electric currents D1 to D8, and gate electrodes 01 to GN are provided.

Further, in the conventional device, the drain electrode D of the liquid crystal panel 1 is
Drain driver 2 that applies drain signals to 1 to DH
and 3, a gate driver 4 that applies gate signals to the gate electrodes 01 to GN, and an LCD control section 5 that provides drain generation timing and gate generation timing.

FIG. 3 is a block diagram showing an example of the configuration of the drain driver shown in FIG. 2. In this drain driver, after inputting the horizontal scanning start pulse STH, the horizontal shift clock C
An on signal that is sequentially shifted to the shift register 11 by the PH is applied to the switch 13 via the level shifter 12, and while the switch 13 is on, an analog video signal V I DE is applied to the capacitor 14 as a sample hold circuit.
An amount of charge proportional to OA to C is accumulated. A voltage proportional to this charge is applied to the drain electrodes D1 to D6o via the buffer 15 while the output enable signal OE is on. 6 Note that 16 is a power supply circuit for the buffer 15.

FIG. 4 is a timing chart showing the operation of the device shown in FIG. In this device, as shown in FIG. 4, line data is sampled and held during the generation interval of a horizontal synchronizing signal (period: 63.5 μs), and then a drain driver drive signal is output to the drain. A drain driver drive signal is applied to the pixel electrode connected to the drain via the thin film transistor only while the gate drive signal is on, and an image is displayed.

[Problem to be solved by the invention]

However, the gate drive signal in the above conventional example is
As shown in FIG. 4, pixel c, 1-D1 has a rectangular waveform, but in pixel G1-DH, which is located away from the gate driver, the waveform is distorted due to the resistance of the gate electrode, resulting in a gate drive waveform. before it turns off (i.e.,
While displaying a pixel), the drain driver drive signal fluctuates by Δ■1 from ■2 and decreases when the output enable signal is turned off), and the image quality deteriorates due to fluctuations in liquid crystal transmittance due to this voltage fluctuation. There was a problem.

Here, FIG. 5 shows the drain voltage V during multi-color driving.
. -The transmittance T characteristic is shown, and FIG. 6 shows the drain voltage V during full color drive for gradation display.

It shows the transmittance T characteristic. As can be seen from Figure 5, in multi-color drive, the drain voltage is set to a value that is stable at transmittance, so voltage fluctuations of Δ■1 do not affect the image quality. In full-color drive for gradation display, the drain voltage is set in the range where the transmittance characteristics are sloped (voltage range from ■ to ■4), so voltage fluctuation of ΔV2 causes transmittance fluctuation ΔT, which affects image quality. affect. Therefore, the above-mentioned deterioration in image quality becomes a problem in full-color driving.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a liquid crystal display device that does not suffer from deterioration in image quality due to voltage fluctuations.

[Means to solve the problem]

A liquid crystal display device according to the present invention includes a liquid crystal layer, a plurality of pixel electrodes that apply an electric field to the liquid crystal layer, a plurality of thin film transistors that control drive signals applied to each of the plurality of pixel electrodes, and a liquid crystal panel having a plurality of gate electrodes arranged in a plurality and connected to the gates of the thin film transistors; a plurality of drain electrodes arranged in a direction crossing the gate electrodes and connected to the drains of the thin film transistors; A gate driver that applies a gate drive signal that is turned on for a certain period of time to the gate electrode, a drain drive signal generator that outputs an output enable signal that is turned on for a certain period of time at a certain period, and a drain drive signal generator that outputs an output enable signal that is turned on for a certain period of time to the gate electrode, a drain driver that applies a drain driver drive signal to the drain electrode in response to the signal, and applies the drain driver drive signal to the pixel electrode while the gate drive signal applied to the gate of the thin film transistor is on. In a liquid crystal display device that displays an image, the plurality of drain electrodes are divided into a plurality of groups, the drain driver is divided for each divided group, and each of the divided drain drivers has a separate The drain drive signal generator is configured to receive an output enable signal at a certain timing, and the drain drive signal generator is configured to input the output enable signal to the group for a time corresponding to the falling characteristic when the gate drive signal applied to the gate of the thin film transistor changes from on to off. By delaying the generation timing of the output enable signal each time, the output enable signal is driven to be turned off after the gate drive signal applied to the gate of the thin film transistor is turned off.

Further, a liquid crystal display device according to another invention includes a liquid crystal layer, a plurality of pixel electrodes that apply an electric field to the liquid crystal layer, and a plurality of thin film transistors that control drive signals applied to each of the plurality of pixel electrodes. A liquid crystal panel having a plurality of gate electrodes arranged in a predetermined direction and connected to the gate of the thin film transistor, and a plurality of drain electrodes arranged in a direction intersecting the gate electrode and connected to the drain of the thin film transistor. a gate driver that applies a gate drive signal that is turned on for a certain period of time to the electrodes 1 to 1; a drain drive signal generator that outputs an output enable signal that is turned on for a certain period of time at a certain period; a drain driver that applies a drain driver drive signal to the drain electrode in response to a video signal for a period of time, and applies the drain driver drive signal to the drain electrode while the gate drive signal applied to the gate of the thin film transistor is on. In the liquid crystal display device that displays an image by applying voltage to the pixel electrode, the plurality of drain electrodes are divided into a plurality of groups, the drain driver is divided for each divided group, and the divided drain driver Each of the above-mentioned wirings is separately provided with a wiring having a different resistance characteristic for transmitting the above-mentioned output enable signal, and each of the above-mentioned wirings By setting resistance characteristics, the thin film transistor is driven so that the output enable signal applied to the drain driver is turned off after the D-drive signal applied to the gate of the thin film transistor is turned off.

[For production]

In the present invention, a plurality of drain electrodes are divided into a plurality of groups, a drain driver is divided for each divided group, and an output enable signal is input to each of the divided drain drivers at separate timings. The drain drive signal generating section is configured so as to

By delaying the generation timing of the output enable signal for each group by a time corresponding to the falling characteristic of the gate drive signal applied to the gate of the thin film transistor, the output enable signal is generated after the gate drive signal is turned off. It is driven to turn off. This prevents the output enable signal from turning off while the gate drive signal is on and pixel display is occurring, and causes voltage fluctuations in the drain drive signal to occur while pixel display is not occurring, resulting in image quality deterioration. We are trying to prevent this from occurring.

Further, in another invention, a plurality of drain electrodes are divided into a plurality of groups, a drain driver and an indriver are divided for each divided group, and an output enable signal is sent to each of the divided drain drivers. A separate wire having a resistance characteristic for transmission is provided, and the output enable signal is transmitted to the drain driver via this separate wire. This is done by setting the resistance characteristics of each of the wirings above according to the falling characteristics when the gate drive signal applied to the gate of the thin film transistor turns from on to off, thereby preventing distortion of the waveform due to wiring resistance. This is to drive the thin film transistor so that the output enable signal applied to the drain driver is turned off after the gate drive signal applied to the gate of the thin film transistor is turned off. This prevents the output enable signal from turning off while the gate drive signal is on and pixel display is occurring, causing voltage fluctuations in the drain drive signal to occur while pixel display is not occurring, resulting in deterioration of image quality. We are trying to prevent this from occurring.

〔Example〕

The present invention will be explained below based on illustrated embodiments.

FIG. 1 is a block diagram showing the configuration of an embodiment of a liquid crystal display device according to the present invention.

As shown in the figure, the liquid crystal display device of this embodiment has a liquid crystal panel 11, and this liquid crystal panel 11 includes a liquid crystal layer (
(not shown), a plurality of pixel electrodes (not shown) that are arranged in a matrix and apply an electric field to the liquid crystal layer, and a plurality of thin film transistors that control drive signals applied to each of the plurality of pixel electrodes. (not shown), a plurality of gate electrodes 01 to GN arranged in a predetermined direction and connected to the gate of the thin film transistor, and a plurality of gate electrodes 01 to GN arranged in a direction crossing the gate electrode and connected to the drain of the thin film transistor. Drain electrodes D1 to DH are provided.

In addition, this embodiment includes drain drivers 12a, 12b, 13a, and 13b that apply drain driver drive signals to the drain electrodes D1 to DH in response to video signals, and gates of thin film transistors via gate electrodes 01 to GN. a gate driver 4 that applies a gate drive signal that is turned on for a certain period of time; and the drain drivers 2a, 12b,
13a.

13b and the LCD control unit 1 that controls the gate driver 4
5 is provided. This LCD control section 15 includes a data processing section 1 that performs data conversion processing corresponding to the pixel array.
6, a drain drive signal generation unit 17 that outputs an output enable signal that is turned on for a certain period of time, and a gate drive signal generation unit 18 that provides generation timing of a gate drive signal.

In this embodiment, a plurality of drain electrodes D1 to D
H is divided into four groups, and the drain electrodes D,
Let D, . . , Da,, 1 be the group GPI, and the drain electrode Da+1' Da,! ``'' DH-1 is grouped into group GP2, and drain electrodes D2, D4゜...
・, D is group GP3, and drain electrode Da+2
．． Da+4. ...-, DH is set to group GP4.

The drain drivers are also divided into four groups.
The drain driver 12a has drain electrodes D1, D3 .
..., for Da-1, and the drain driver 12b is for drain/in electrodes D, Da+1 a+
3°゛.

DH-1A, the drain driver 13a is for drain electrodes D2, Da, ..., Da, and the drain driver 13b is for drain electrodes D2, D, D.
.

a+2 a soil 4 ..., for DH.

Note that the drain drivers 12a, 12b, and 13a.

13b has the same configuration as that in FIG. 3, and the carry terminal (HO6 in FIG. 3) of the drain driver 12a (13a>
0) and the shift clock input terminal (CPH in FIG. 3) of the drain driver 12b (13b) are connected in cascade.

Further, the drain drive signal generating section 17 is configured to be able to input an output enable signal to each of the divided drain drivers 12a, 12b, 13a, and 13b at separate timings.

FIG. 7 is a timing chart for explaining the operation of this embodiment. Next, the operation of the liquid crystal display device of this embodiment will be explained based on FIGS. 1 and 7.

In this embodiment, as shown in FIG. 7, the line data is sampled and held in synchronization with the horizontal synchronization signal (at times 1 t1 and Tt2), and then the drain driver drive signal is output in accordance with the output enable signal. output to the drain electrode. A drain driver drive signal is applied to the pixel electrode only while the gate drive signal is on.

By the way, the gate drive signal has a gate drive waveform of pixel G on the voltage supply side and the termination side of the gate line as shown in FIG.
-G and pixel G1-GM a As can be seen, there is a difference in the drive waveform. Here, the time during which the gate drive signal is turned off is the time T for pixel 01G.
The time during which the voltage VG of the gate drive signal drops from 0.9VG to O,IVG with a delay fl is defined as a delay time), and the pixel G1-G is delayed by a time T1□.

Therefore, for example, the output enable signal for the drain driver 13a is delayed by a time TD1 longer than the time Tf1, and for the drain driver 13b, the output enable signal is delayed by a time Tf2.
Delay TD2 for a longer time.

In this way, the gate drive signal was turned off by delaying the generation timing of the output enable signal by a time corresponding to the falling characteristic when the gate drive signal applied to the gate of the five thin film transistors turned from on to off. It is driven so that the output enable signal is turned off later.

This prevents the output enable signal from turning off while the pixel is being displayed (while the gate drive signal applied to the gate of the thin film transistor is on), and prevents the output enable signal from turning off when the pixel is not being displayed. causing a voltage fluctuation Δ■2 of the driver drive signal,
This voltage fluctuation is prevented from affecting image quality.

Note that the on time T of the output enable signal. F is 1. Since it is necessary to suppress the amount of heat generated by the buffer of the drain driver, it is necessary to keep the period within about 30% of the generation period of the horizontal synchronizing signal.

FIG. 8 is a block diagram showing the structure of another embodiment of the liquid crystal display device according to the present invention.

As shown in the figure, the liquid crystal display device of this example includes:
Similar to the embodiment of FIG. 1, a liquid crystal layer (not shown), pixel electrodes (not shown) arranged in a matrix, a plurality of thin film transistors (not shown), and a plurality of gate electrodes G1 ~GN, and a plurality of drain electrodes D1 to DH.

Further, this embodiment is provided with a drain driver that applies a drain driver drive signal to the drain electrodes D1 to DH in response to a video signal.

This drain driver is divided into groups DDV1 to DDVn.

Then, these divided drain drivers DDV1 to DDV1-D
Wiring lines 1 to LIl with different resistance characteristics for transmitting output enable signals to each of the drain drivers DDV1 to DDV[
It is configured so that it is transmitted to I. As will be described later, the wiring resistance can be determined by wiring each wire according to the falling characteristics when the gate drive signal applied to the gate of the thin film transistor turns from on to off, and setting the resistance characteristics of ~L11. Taking advantage of the fact that the waveform is distorted by
This is to drive so that the output enable signal applied to the drain driver is turned off after the gate drive signal applied to the gates of the thin film 1 to the transistor is turned off.

Furthermore, in this embodiment, gate drivers GDv1 to CDVn apply gate drive signals that are turned on for a certain period of time to the gates of thin film transistors via gate electrodes 01 to GN.
After inputting the NTSC video signal to the connector 22, data conversion processing corresponding to the pixel arrangement of the liquid crystal panel 21 is performed and the drain driver DDV1 is connected via the connector 22.
-DDvm and an LCD control unit 23 that outputs signals to gate drivers GDVI-CDVn.

FIG. 9 is a timing chart for explaining the operation of this embodiment. Third, the operation of the liquid crystal display device of this embodiment will be explained based on FIGS. 8 and 9.

In this embodiment, as shown in FIG. 9, line data is sampled and held in synchronization with the generation of a horizontal synchronizing signal, and then a drain driver drive signal is output to the drain electrode in response to an output enable signal. A drain driver drive signal is applied to the pixel electrode only while the gate drive signal is on.

By the way, the gate drive signal has a gate drive waveform of pixel G-G in FIG. 9 on the voltage supply side and the termination side of the gate line.
(or Gi Gb) and the pixel Ga 1-GM-1 (or G1-GM), a difference occurs in the drive waveform. Here, the time during which the gate drive signal is turned off is the pixel G1-Ga (S is G-G
) is delayed by time Tf3, and pixel Gb 1'H-1 (G - G ) is delayed by time ]゛, 4,
4 delayed.

Therefore, in this embodiment, the wirings L1 to L1 of the drain drivers DDV1 to DD'Vl are
Set the resistance characteristics of This wiring resistance distorts the waveform of the output enable signal and delays the time when the output enable signal turns off (for pixels G1-Ga, time T
Let Tf5' be longer than f3, pixel G1'M-1
In this case, the output enable signal applied to the drain driver is turned off after the gate drive signal applied to the gate of the thin film transistor is turned off for a time "f6 delayed longer than time T14".

This prevents the output enable signal from turning off while the pixel is being displayed (while the gate drive signal applied to the gate of the thin film transistor is on), and prevents the output enable signal from turning off when the pixel is not being displayed. causing a voltage variation Δv2 of the driver drive signal;
It is driven so that this voltage fluctuation does not affect the image quality.

〔Effect of the invention〕

As described above, according to the present invention, the gate drive signal is turned off by delaying the generation timing of the output enable signal by a time corresponding to the falling characteristic of the gate drive signal applied to the gate of the thin film transistor. drive the output enable signal to turn off after
The output enable signal is prevented from turning off while the gate drive signal is on and pixel display is being performed. Therefore, it is possible to prevent deterioration of image quality by causing voltage fluctuations in the drain drive signal while no pixel display is being performed.

Further, in another invention, the resistance of the wiring that transmits the output enable signal to each of the divided drain drivers is determined according to the falling characteristics when the gate drive signal applied to the gate of the thin film transistor turns from on to off. By setting the characteristics and taking advantage of the fact that the waveform is distorted by wiring resistance, the output enable signal applied to the drain driver is turned off after the gate drive signal applied to the gate of the thin film transistor is turned off. There is. Therefore, it is possible to prevent deterioration of image quality by causing voltage fluctuations in the drain drive signal while the pixels are not being displayed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the liquid crystal display device according to the present invention, FIG. 2 is a block diagram showing the configuration of a conventional liquid crystal display device, and FIG. 3 is the configuration of the drain driver shown in FIG. 2. A block diagram showing an example, Fig. 4 is a timing chart showing the operation of the device shown in Fig. 2, Fig. 5 is a graph showing the drain voltage ■0-transmittance T characteristic during multi-color drive, and Fig. 6 is a graph showing the Drain voltage during full color drive with color display ■. - A graph showing the transmittance T characteristic, Fig. 7 is a timing chart showing the operation of this embodiment, Fig. 8 is a block diagram showing the configuration of another embodiment of the liquid crystal display device according to the present invention, and Fig. 9 is a 5 is a timing chart showing the operation of this embodiment. 1121...Liquid crystal panels 12a, 12b, 13a DD■1~DDVrQ...Drain driver 14, GDVI~GDVn 15.23...LCD control section G1~GN...Gate electrode D1~DH...Drain Electrodes L1 to LH...Wiring 3b...Gate driver

Claims (2)

[Claims] (1) A liquid crystal layer, a plurality of pixel electrodes that apply an electric field to the liquid crystal layer, and a plurality of thin film transistors that control drive signals applied to each of the plurality of pixel electrodes, which are arranged in a predetermined direction. a liquid crystal panel having a gate electrode connected to the gate of the thin film transistor; a plurality of drain electrodes arranged in a direction crossing the gate electrode and connected to the drain of the thin film transistor; a gate driver that applies a gate drive signal that turns on; a drain drive signal generator that outputs an output enable signal that is turned on for a certain period of time at a certain period; and a drain driver that applies a driver drive signal to the drain electrode, and displays an image by applying the drain driver drive signal to the pixel electrode while the gate drive signal applied to the gate of the thin film transistor is on. In the liquid crystal display device, the plurality of drain electrodes are divided into a plurality of groups,
The drain driver is divided into each of the divided groups, and the drain drive signal generating section is configured so that an output enable signal is inputted to each of the divided drain drivers at separate timings, and the gate of the thin film transistor is The gate drive signal applied to the gate of the thin film transistor is delayed by delaying the generation timing of the output enable signal for each group by a time corresponding to the falling characteristic when the gate drive signal applied to the gate turns from on to off. A liquid crystal display device characterized in that the liquid crystal display device is driven so that the output enable signal is turned off after the signal is turned off. (2) A liquid crystal layer, a plurality of pixel electrodes that apply an electric field to the liquid crystal layer, and a plurality of thin film transistors that control drive signals applied to each of the plurality of pixel electrodes, which are arranged in a predetermined direction. a liquid crystal panel having a gate electrode connected to the gate of the thin film transistor; a plurality of drain electrodes arranged in a direction crossing the gate electrode and connected to the drain of the thin film transistor; a gate driver that applies a gate drive signal that turns on; a drain drive signal generator that outputs an output enable signal that is turned on for a certain period of time at a certain period; and a drain driver that applies a driver drive signal to the drain electrode, and displays an image by applying the drain driver drive signal to the pixel electrode while the gate drive signal applied to the gate of the thin film transistor is on. In the liquid crystal display device, the plurality of drain electrodes are divided into a plurality of groups,
The drain driver is divided into each of the divided groups, and each of the divided drain drivers is provided with a separate wiring having a different resistance characteristic for transmitting the output enable signal, and the gate drive is applied to the gate of the thin film transistor. By setting the resistance characteristics of each of the wirings according to the falling characteristics when the signal turns from on to off, the gate drive signal applied to the gate of the thin film transistor is applied to the drain driver after turning off. 1. A liquid crystal display device characterized in that the device is driven so that an output enable signal is turned off.