KR20090013623A - Driving circuit for liquid crystal display - Google Patents

Abstract

A driving circuit for liquid crystal display is provided to prevent the deterioration of the picture quality due to the abnormal gate signal outputted from gate driver by resetting the first dummy gate driver among the dummy gate drivers of 2 stage in proper time. A driver circuit for liquid crystal display comprises a plurality stage of the gate drivers(12A-12.), the first and second dummy gate drivers(DM1,DM2) and the third dummy gate driver(DM3). The plurality stage of the gate drivers is successively driven after the new frame is initiated and outputs the gate ON signal to each gate line in the liquid crystal panel. The output node is reset by the output signal of N+ 2 stages. In order to reset the output node of the final stage gate driver among the plurality stage of gate drivers, The first and second dummy gate drivers consisted in the same configuration are connected subordinately. The third dummy gate driver resets the output node of the first dummy gate driver in proper time. Therefore, the undesired gate signal is not outputted to the corresponding gate line.

Description

 DRIVING CIRCUIT FOR LIQUID CRYSTAL DISPLAY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving technology of a liquid crystal display device, and more particularly, to a driving circuit of a liquid crystal display device which is suitable for preventing abnormal signal from being outputted from a gate driver and deteriorating image quality.

Recently, with the rapid development of information technology (IT), the importance of the flat panel display device as a visual information transmission medium has been further emphasized. However, in order for the flat panel display device to preoccupy a major position in the future, low power consumption, thinness, light weight, and high quality are required.

Liquid crystal display (LCD), which is a typical flat panel display device, displays an image by using optical anisotropy of liquid crystal, and is a cathode ray tube due to its advantages such as thin, small size, low power consumption, and high quality. It is being developed as a major product of flat panel display that can replace CRT.

In general, a liquid crystal display device is a display device in which image information is individually supplied to pixels arranged in a matrix, and a desired image is displayed by adjusting light transmittance of the pixels. Accordingly, the liquid crystal display includes a liquid crystal panel in which pixels, which are the smallest units for implementing an image, are arranged in an active matrix form, and a driving unit for driving the liquid crystal panel. Since the LCD does not emit light by itself, a backlight unit is provided to supply light to the LCD.

FIG. 1 is a block diagram of a driving circuit of a liquid crystal display according to the prior art, and is mounted on the main PC 10 to control driving of the gate driver 12 and the data driver 13, as shown therein. A timing controller 11 for outputting various control signals for outputting the signal, and reordering and outputting the input digital video data RGB; A gate driver 12 mounted on one side of the liquid crystal panel 14 and supplying a gate-on signal to each gate line GL1 to GLn of the display region 14A on the liquid crystal panel 15; A data driver 13 mounted on the other side of the liquid crystal panel 14 to supply a data signal to each of the data lines DL1 to DLm of the display area 14A; It consists of a liquid crystal panel 14 for displaying an image by using the liquid crystal cells of the matrix type driven by the data signal and the gate-on signal, the operation thereof will be described as follows.

The timing controller 11 installed on the main PC 10 controls the gate control signal and the data driver 13 for controlling the gate driver 12 using the vertical / horizontal synchronization signal and the clock signal input from the system. To generate a data control signal. In addition, the timing controller 11 samples the digital video data RGB input from the system, rearranges the digital video data RGB, and supplies the data to the data driver 13.

The gate driver 12 sequentially supplies a gate-on signal (scan pulse) to each gate line GL1 to GLn on the liquid crystal panel 14 in response to the gate control signal from the timing controller 11. Horizontal lines from which data is supplied are selected.

In addition, the data driver 13 converts the digital video data RGB into a data voltage (analog gamma compensation voltage) corresponding to the gray scale value in response to a data control signal from the timing controller 11, and thus converts the digital video data RGB into a data voltage corresponding to the gray scale value. The data voltage is supplied to each of the data lines DL1 to DLm on the liquid crystal panel 14.

In the display area 14A on the liquid crystal panel 14, the gate lines GL1 to GLn and the data lines DL1 to DLm are arranged to cross each other, and the liquid crystal cells are positioned in the intersection area. In the display area 14A, pixel electrodes and a common electrode for applying a data voltage to each of the liquid crystal cells are provided. Each of the pixel electrodes is connected to one of the data lines via source and drain terminals of a thin film transistor TFT that is a switching element. Gate terminals of the thin film transistors are connected to gate lines on the corresponding horizontal lines, respectively. In the display area 14A, the light transmittance is adjusted according to the data voltage applied between the pixel electrode and the common electrode for each liquid crystal cell to display an image.

The gate driver 12 and the data driver 13 may be provided outside the liquid crystal panel 14 as needed. However, as described above, the gate driver 12 and the data driver 13 may be disposed on the outside of the display area 14A. For example, the glass panel is mounted.

2 is an internal block diagram of the gate driver 12. As shown therein, the number of gate drivers 12A to 12N corresponding to the gate lines GL1 to GLn is provided, and the dummy gate driver is provided therein. (DM1) and (DM2) are further provided.

FIG. 3 is a detailed circuit diagram of an arbitrary gate driver among the gate drivers 12A to 12N. As shown in FIG. 3, the power supply terminal is turned on by the output signal Vout (N-2) and is connected to the output node Q. A MOS transistor (hereinafter referred to as a transistor) T1 for supplying a voltage Vdd; A transistor T2 turned on by an output signal Vout (N + 2) to reset the output node Q; A transistor (T3) which is turned on by the V-start signal (Vst) supplied in a frame period to reset the output node (Q); A transistor T4 which is turned on by a clock signal CLK (N-1) and mutes the voltage of the output node Q to the output terminal Vout (N-1) of the previous gate driver; A transistor T5 which is turned on when the output node Q is in a high potential state and outputs a clock signal CLK (N) to an output terminal Vout; The transistor T6 is turned on by the clock signal CLK (N + 2) to reset the output terminal Vout. The operation thereof will be described below.

The transistor T3 is turned on by the V-start signal Vst at the start of the frame. Therefore, the output node Q is reset by the transistor T3.

Thereafter, the transistor T1 is turned on by the output signal Vout (N-2) of the (N-2) th gate driver, whereby the power supply terminal voltage Vdd is output through the transistor T1. Q) and its output node (Q) is at high potential (logic 'high'). At this time, the transistors T2-T4 and T6 maintain the turn-off state.

In this state, the clock signal CLK (N) is supplied to the drain of the output terminal transistor T5 whose gate is connected to the output node Q, and the transistor T5 is turned on. Accordingly, the clock signal CLK (N) is output to the output terminal OUT through the transistor T5. The signal thus output is supplied to the corresponding gate line on the liquid crystal panel 14 as the gate-on signal.

After the gate-on signal is output from the output terminal OUT, the transistor T2 is turned on by the output signal Vout (N + 2) of the N + 2th gate driver. Thus, the output node Q is reset through the transistor T2.

Similarly, the remaining gate drivers are also driven as described above to sequentially supply gate-on signals to the respective gate lines GL1 to GLn.

As described above, the gate drivers 12A to 12N are sequentially driven, and a gate-on signal is supplied to the gate lines GL1 to GLn of the liquid crystal panel 14 every time, and the output signal Vout of the N + 2th gate driver is supplied. (N + 2)], the output node Q of the gate driver is reset. As a result, the transistor T5 of the output terminal is reliably kept in the OFF state, thereby preventing the wrong gate-on signal from being output from the output terminal OUT.

However, in the case of the last gate driver 12N and the gate driver 12N-1 immediately preceding the gate driver 12N, since the gate driver no longer exists at the rear end, the output signal [Vout (N + 2)] It is not possible to reset these output nodes Q because they are not supplied. Therefore, two dummy gate drivers DM1 and DM2 are additionally provided in the gate driver 12N.

In this way, after the gate-on signal Vout is output from the output terminal of the gate driver 12N-1, the output signal Vout (N) is transmitted to the gate driver 12N-1 through the dummy gate driver DM1. +2) can be supplied to reset the output node Q thereof.

Similarly, after the gate-on signal Vout is output from the output terminal of the last gate driver 12N, the output signal Vout (N + 2) to the gate driver 12N through the dummy gate driver DM2. ) Can be supplied to reset the output node Q thereof.

4 shows a timing diagram of the clock signals CLK1-CLK4, the signals of the output nodes Q_DM1 and Q_DM2 of the dummy gate drivers DM1 and DM2, and the output signals OUT_DM1 and OUT_DM2. will be.

However, the first dummy gate driver DM1 has a structure in which the transistor T3 is turned on by the V-start signal Vst and the output node Q (n) is reset when the frame is newly started. It is not designed to be reset by the output signal Vout (N + 2) at the next stage.

Thus, the output node Q in the dummy gate driver DM1 is maintained at a high level of a predetermined level until a new frame is started after the output signal OUT (n) is output from the last gate driver 12N. .

Therefore, in the dummy gate driver DM1, the high potential of the output node Q (n) is supplied through the transistor T4 at the moment when the clock signal CLK (N-1) is supplied and the transistor T4 is turned on. It is fed back to the output signal of the previous stage, that is, the output signal [Vout (N-1)] of the gate driver 12N.

Accordingly, an undesirable gate-on signal corresponding to the level of the output node Q (n) of the dummy gate driver DM1 from the output terminal OUT of the gate driver 12N to the corresponding gate line, that is, FIG. 5. The signal of the part indicated by the circle at is outputted.

In FIG. 5, "OUT_N" is a waveform diagram of the output signal of the last stage gate driver 12N, and "Q_DM1" is a waveform diagram of the output signal of the output node Q_DM1 of the first dummy gate driver DM1.

As described above, in the conventional liquid crystal display device, in order to reset the last gate driver and the gate driver immediately before the gate driver in time, two dummy gate drivers are used. Since the output node voltage is not reset, the output node voltage is fed back to the output terminal of the last gate driver, and thus, an undesirable gate-on signal is supplied to the corresponding gate line, resulting in deterioration of image quality.

Accordingly, an object of the present invention is that the first dummy gate driver of the two-stage dummy gate driver used to reset the last two gate drivers of the multiple stage gate drivers for driving the liquid crystal panel of the liquid crystal display device in time. This is to prevent the undesirable supply of the gate signal to the corresponding gate line because it is not reset in time.

In order to achieve the above object, the present invention provides a gate-on signal to each gate line on the liquid crystal panel while a new frame is started and the output node is reset, and then sequentially driven. A plurality of gate drivers, in which output nodes are reset by the plurality of gate drivers; First and second dummy gate drivers having the same configuration and cascaded to reset the output nodes of the last two gate drivers of the multiple stage gate drivers; In order to reset the output node of the first dummy gate driver in a timely manner to prevent the unwanted gate signal from being output to the corresponding gate line, an additional third dummy gate driver may be provided or the second dummy gate driver may be used. It features.

According to the present invention, the first dummy gate driver of the two-stage dummy gate driver used to reset the last gate driver of the multiple stage gate drivers for driving the liquid crystal panel of the liquid crystal display device is not reset in time. By appropriately eliminating the problem, there is an effect that the gate-on signal is abnormally output to prevent the image quality defect from occurring.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 6 is a block diagram showing an embodiment of a driving circuit of a liquid crystal display according to the present invention. As shown in FIG. 6, each time a new frame starts, the output node is reset by the V-start signal Vst. Gate drivers 12A to 12N which are sequentially driven to output gate-on signals to the gate lines GL1 to GLn on the liquid crystal panel, and the output nodes are reset by the output signals of the N + second stage; In order to reset the output node of the last gate driver 12N and the immediately preceding gate driver 12N-1, two-stage dummy gate drivers DM1 and cascaded in the same configuration are connected. )Wow; In order to reset the output node of the dummy gate driver DM1 in a timely manner to prevent an unwanted gate signal from being output to the corresponding gate line, a dummy gate driver DM3 connected to the dummy gate driver DM2 is further connected. It was configured to include.

Each of the gate drivers includes a transistor T1, which is turned on by an output signal Vout (N-2) and supplies a power terminal voltage Vdd to an output node Q, as shown in FIG. A transistor T2 turned on by an output signal Vout (N + 2) to reset the output node Q; A transistor (T3) which is turned on by the V-start signal (Vst) supplied in a frame period to reset the output node (Q); A transistor T4 which is turned on by the clock signal CLK (N-1) and mutes the voltage of the output node Qn to the output terminal Vout (N-1) of the previous gate driver; A transistor T5 which is turned on when the output node Qn becomes a high potential state and outputs a clock signal CLK (N) to an output terminal Vout; A transistor T6 is turned on by the clock signal CLK (N + 2) to reset the output terminal Vout.

Referring to Figure 7 attached to the operation of the first embodiment of the present invention configured as described above in detail as follows.

The gate drivers 12A to 12N in FIG. 6 are provided inside the gate driver 12 mounted on the liquid crystal panel 14 in FIG. 1, and gate-on signals sequentially output from the gate drivers 12 are disposed on the liquid crystal panel 14. It is supplied to each gate line GL1-GLn.

In addition, the gate drivers 12A to 12N are configured as shown in FIG. 3, respectively, and are sequentially driven. Each of the gate drivers 12A to 12N operates in the same manner as a conventional gate driver.

That is, the transistor T3 is turned on by the V-start signal Vst at the time when the frame is newly started. Therefore, the output node Q is reset by the transistor T3.

Thereafter, the transistor T1 is turned on by the output signal Vout (N-2) of the (N-2) th gate driver, whereby the power supply terminal voltage Vdd is output through the transistor T1. Q) and its output node (Q) is at high potential (logic 'high'). At this time, the transistors T2-T4 and T6 maintain the turn-off state.

In this state, the clock signal CLK (N) is supplied to the drain of the output terminal transistor T5 whose gate is connected to the output node Q, and the transistor T5 is turned on. Accordingly, the clock signal CLK (N) is output to the output terminal OUT through the transistor T5. The signal thus output is the gate-on signal, which is supplied to the corresponding gate line on the liquid crystal panel 14 of FIG.

After the gate-on signal is output from the output terminal OUT, the transistor T2 is turned on by the output signal Vout (N + 2) of the N + 2th gate driver. Thus, the output node Q is reset by the transistor T2.

Similarly, the remaining gate drivers are also driven like the gate drivers to sequentially supply gate-on signals to the gate lines GL1 to GLn.

As described above, the gate drivers 12A to 12N are sequentially driven to sequentially supply gate-on signals to the gate lines GL1 to GLn of the liquid crystal panel 14, and output signals Vout of the N + 2th gate drivers. (N + 2)] to reset the output node Q of the gate driver. Accordingly, since the transistor T5 at the output terminal is reliably kept in the OFF state, the wrong gate-on signal is prevented from being output at the output terminal OUT.

However, in the case of the last gate driver 12N and the gate driver 12N-1 immediately preceding the gate driver 12N, since the gate driver no longer exists at the rear end, the output signal [Vout (N + 2)] It is not possible to reset the output node Q as described above. Therefore, two dummy gate drivers DM1 and DM2 are additionally provided at the rear end of the gate driver 12N.

In this way, after the gate-on signal Vout is output from the output terminal of the gate driver 12N-1, the output signal [Vout () is output to the gate driver 12N-1 through the dummy gate driver DM1. N + 2)] can be supplied to reset the output node Q thereof.

Similarly, after the gate-on signal Vout is output from the output terminal of the last gate driver 12N, the output signal Vout (N + 2) to the gate driver 12N through the dummy gate driver DM2. ) Can be supplied to reset the output node Q thereof.

In this case, however, the dummy gate driver DM1 cannot be reset in a timely manner, so that the output node Q (n) of the dummy gate driver DM1 is maintained at a high level of a predetermined level.

Accordingly, in the dummy gate driver DM1, the moment when the transistor T4 is turned on by supplying a clock signal CLK (N-1) to the gate in order to keep the output terminal transistor T5 in the off state. The high potential of the output node Q (n) is fed back to the output signal of the previous stage, ie, the output signal [Vout (N-1)] of the gate driver 12N through the transistor T4.

Accordingly, an undesirable gate-on signal corresponding to the level of the output node Q (n) of the dummy gate driver DM1 from the output terminal OUT of the gate driver 12N to the corresponding gate line, that is, in FIG. 5. The signal of the portion indicated by the circle is output, whereby the image quality deteriorates.

In the present invention, one dummy gate driver DM3 is further added in view of this, and the reset operation according to the present invention is described below.

The dummy gate driver DM3 turns on the transistor T2 by supplying an output signal Vout (N + 2) to the first dummy gate driver DM1 at a corresponding point in time. As a result, the output node Qn of the dummy gate driver DM1 is reset and maintained at the low potential state.

Therefore, in the dummy gate driver DM1, the moment the clock signal CLK (N-1) is supplied to the gate and the transistor T4 is turned on, at the output node Qn through the transistor T4. The high potential is not fed back to the gate-on signal output terminal of the previous stage, that is, the gate-on signal output terminal of the gate driver 12N.

Accordingly, as shown in FIG. 7, after the normal gate-on signal is output from the gate driver 12N, an undesirable gate-on signal, that is, a high potential above a predetermined level is not output.

Meanwhile, FIG. 8 illustrates another embodiment of the present invention. As shown in FIG. 8, each gate of the liquid crystal panel is sequentially driven after the output node is reset by the V-start signal Vst whenever a new frame starts. Gate drivers 12A to 12N which output gate-on signals to the lines GL1 to GLn, and whose output nodes are reset by an output signal of the N + second stage; In order to reset the output node of the last gate driver 12N and the immediately preceding gate driver 12N-1, two-stage dummy gate drivers DM1 and DM2 connected in the same configuration as those of the second stage. '), And the dummy gate driver DM2' is configured to reset the dummy gate driver DM1 together when the gate driver 12N at the last stage is reset. Referring to the following.

In FIG. 8, the gate drivers 12A to 12N are sequentially driven as described with reference to FIG. 6 to sequentially supply gate-on signals to the gate lines GL1 to GLn of the liquid crystal panel 14, and N + 2. The output node Q of the corresponding gate driver is reset using the output signal Vout (N + 2) of the first gate driver.

Accordingly, since the transistor T5 at the output terminal is reliably kept in the OFF state, the wrong gate-on signal is prevented from being output at the output terminal OUT.

However, in the case of the last gate driver 12N and the gate driver 12N-1 immediately preceding the gate driver 12N, since the gate driver no longer exists at the rear end, the output signal [Vout (N + 2)] It is not possible to reset the output node Q as described above. Therefore, two dummy gate drivers DM1 and DM2 'are additionally provided in the gate driver 12N.

In this way, after the gate-on signal Vout is output from the output terminal of the gate driver 12N-1, the output signal Vout (N) is transmitted to the gate driver 12N-1 through the dummy gate driver DM1. +2) can be supplied to reset the output node Q thereof.

Similarly, after the gate-on signal Vout is output from the output terminal of the last gate driver 12N, the output signal Vout (N + 2) to the gate driver 12N through the dummy gate driver DM2 '. ) Can be supplied to reset the output node Q thereof.

At this time, the dummy gate driver DM2 'supplies the output signal Vout (N + 2) to the dummy gate driver DM1 to reset the output node Q thereof. That is, the dummy gate driver DM2 ′ simultaneously supplies the output signal Vout (N + 2) to the gate driver 12N and the dummy gate driver DM1 to simultaneously output their output node Q. Set. As a result, the voltage of the output node Q of the dummy gate driver DM1 transitions to the ground potential level Vss as shown in FIG. 7.

In Fig. 7, "OUT_N" is a waveform diagram of the output signal of the last stage gate driver 12N, "Q_DM1" is a waveform diagram of the output signal of the output node Q_DM1 of the first dummy gate driver DM1, and " OUT_DM1 "and" OUT_DM2 "are waveform diagrams of output signals of the first and second gate drivers.

Accordingly, in the dummy gate driver DM1, the clock signal CLK (N-1) is supplied to the gate to maintain the output terminal transistor T5 in the off state, and the transistor T4 is turned on. At the moment, the low potential of the output node Q (n) is fed back through the transistor T4 to the output signal of the previous stage, that is, the output signal [Vout (N-1)] of the gate driver 12N.

Accordingly, the gate-on signal of an undesirable level or more is not output from the output terminal OUT of the gate driver 12N, and thus the stable low potential level can be maintained.

However, due to this, the output node signal Q_DM1 of the dummy gate driver DM1 is slightly distorted as shown in FIG. 7, but it does not have any relationship with the displayed pixel.

However, as in the above description, the output signal [Vout (N + 2)] is simultaneously supplied to the gate driver 12N and the dummy gate driver DM1 using the dummy gate driver DM2 'and their output node. When (Q) is reset at the same time, the high potential is continuously supplied from the dummy gate driver DM1 to the gate of the transistor T2 of the previous previous gate driver 12N-1 connected to the output terminal Q_DM1. As a result, the transistor T2 of the gate driver 12N-1 is easily deteriorated to cause a malfunction of the circuit.

In view of this, in the present invention, the timing of the clock signal is adjusted. For example, as shown in FIG. 9, the timing of the clock signal CLK2 is adjusted such that the high and low sections of two adjacent clock signals CLK1 and CLK2 alternately appear without overlapping.

By doing so, the high potential intervals of the output node signals Q_DM1, Q_DM2, and output signals OUT_DM1, OUT_DM2 of the two adjacent gate drivers, for example, the dummy gate drivers DM1, DM2, are shown in FIG. As shown in FIG. 6, they are not overlapped but alternately appear, whereby a state in which the high potential is continuously supplied to the gate of the transistor T2 of the gate driver 12N-1 is not generated.

1 is a block diagram of a liquid crystal display device according to the prior art.

FIG. 2 is a detailed block diagram of the gate driver of FIG. 1. FIG.

3 is a circuit diagram of the gate driver in FIG.

4 is a waveform diagram of each signal applied to the gate driver of FIG.

5 is a waveform diagram of an output node and an output signal in FIG. 3;

6 is a block diagram of a gate driver according to the present invention.

Fig. 7 is a waveform diagram of each signal on the gate driver according to the present invention.

8 is a block diagram of another gate driver in accordance with the present invention.

9 is a waveform diagram of each signal applied to a gate driver according to the present invention.

*** Description of the symbols for the main parts of the drawings ***

11: timing controller 12: gate driver

12A-12N: Gate driver 13: Data driver

14: liquid crystal panel DM1, DM2: dummy gate driver

Claims (6)

A plurality of gate drivers each of which is sequentially driven after a new frame starts and outputs a gate-on signal to each gate line on the liquid crystal panel, and the output node is reset by an output signal of an N + second stage; First and second dummy gate drivers having the same configuration and cascaded to reset the output node of the last gate driver among the gate drivers of the plurality of stages; And a third dummy gate driver for resetting the output node of the first dummy gate driver in a timely manner to prevent an unwanted gate signal from being output to the corresponding gate line. The gate driver of claim 1, wherein each gate driver A first transistor turned on by an output signal Vout (N-2) to supply a power supply terminal voltage Vdd to the output node Q; A second transistor turned on by an output signal Vout (N + 2) to reset the output node Q; A third transistor turned on by a V-start signal Vst supplied at a frame period to reset the output node Q; A fourth transistor turned on by a clock signal CLK (N-1) and muting the voltage of the output node Qn to the output terminal Vout (N-1) of the previous gate driver; A fifth transistor which is turned on when the output node Q is in a high potential state and outputs a clock signal CLK (N) to an output terminal Vout; And a sixth transistor which is turned on by a clock signal (CLK (N + 2)) to reset the output terminal (Vout). The driving circuit of a liquid crystal display device according to claim 1, wherein each gate driver is provided on a liquid crystal panel. The third dummy gate driver is configured to prevent an unwanted gate signal from being output to the corresponding gate line when the output node of the first dummy gate driver cannot be reset in a timely manner. Driving circuit of liquid crystal display device. A plurality of stages of gate drivers which are sequentially driven after a new frame is started and output gate-on signals to respective gate lines on the liquid crystal panel, and the output nodes are reset by output signals of the N + 2 th stage; In order to reset the output node of the last stage gate driver of the multiple stages of the gate driver having the same configuration and cascaded first and second dummy gate driver, wherein the second dummy gate driver A driving circuit for a liquid crystal display device, characterized in that the first dummy gate driver is also reset when the gate driver at the last stage of the driver is reset. 6. The driving circuit of a liquid crystal display device according to claim 5, wherein the clock signal supplied to the first and second dummy gate drivers is supplied so that the same potential does not overlap.

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