KR101409514B1 - Liquid Crystal Display And Method Of Dirving The Same - Google Patents

Abstract

The present invention relates to a liquid crystal display and a driving method thereof.

The liquid crystal display according to the present invention includes a liquid crystal panel, a gate driver for applying a gate signal to the liquid crystal panel, and an RC delay compensation output buffer unit for applying a variable pixel voltage signal to the liquid crystal panel according to the position of the data line And a timing controller for controlling the gate driver and the data driver.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display, including: storing a portion of a pixel voltage signal in a capacitor every one scan period; applying a voltage stored in a capacitor to the pixel voltage signal; Lt; / RTI > to the pixel voltage signal.

Description

[0001] The present invention relates to a liquid crystal display device and a driving method thereof,

1 is a view showing a conventional liquid crystal display device.

2 is an equivalent circuit diagram of a data line;

3 is a diagram illustrating a conventional pre-emphasis voltage.

4 is a view showing a liquid crystal display device according to the present invention.

5 shows a data driver according to the present invention.

6 is a view showing a data drive IC according to the present invention;

7 is a circuit diagram showing an output buffer according to the present invention;

8 is a timing chart showing a control signal of the output buffer;

Figs. 9 to 10 are diagrams showing equivalent circuit diagrams of a line-emphasis voltage generating section according to the timing of a control signal. Fig.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof that can prevent delay of a data voltage due to RC delay while eliminating voltage instability.

A liquid crystal display device is a display device that displays an image by adjusting the light transmittance of a liquid crystal using an electric field.

That is, the liquid crystal display device adjusts the light transmittance by varying the arrangement state of liquid crystal having dielectric anisotropy according to a pixel voltage signal charged through a thin film transistor (TFT) in a liquid crystal cell formed in a matrix form in a liquid crystal panel, .

The pixel voltage signal for gradation representation is applied to the liquid crystal cell 7 via the data lines via the data driver shown in Fig.

At this time, the data line for applying the pixel voltage signal can be expressed by an equivalent circuit as shown in FIG. Accordingly, the pixel voltage signal Vvideo output from the data driver is delayed and output via the data line by the RC delay.

As a method for preventing the delay of the pixel voltage signal due to the RC delay, there has been proposed a method of driving a liquid crystal display device in which a pre-empasis voltage is applied to a pixel voltage signal. This is due to the driving method of the liquid crystal display device disclosed in the application No. 2002-76164, in which a pre-emphasis voltage is applied at the beginning of the pixel voltage signal to prevent the pixel voltage signal from being delayed by the RC delay Method.

However, the conventional method of applying the line-emphasis voltage has a difficulty in simultaneously achieving the improvement of the RC delay between all the pixels and the voltage stabilization because the line-emphasis voltage of the same magnitude is applied to all the pixels. This is because the pixels of each liquid crystal panel have different distances from the data driver to the delay of the pixel voltage signal due to the RC delay. The magnitude of the line-emphasized voltage applied to compensate for the delay of the pixel voltage signal is the same .

In other words, as shown in FIG. 1, the difference between the A point near the data driver and the B point far from the data driver is different and the degree of delay of the pixel voltage signal is different. For example, since the point B far from the data driver has a large RC load, if the line-emphasis voltage is applied to the point B, the voltage stabilization at the point A may be obstructed. Alternatively, if the magnitude of the line-emphasis voltage is set corresponding to the RC load at the point A, it is insufficient to compensate the delay of the pixel voltage signal due to the RC delay at the point B.

This phenomenon becomes more difficult to achieve the voltage stabilization and the compensation of the delay of the pixel voltage signal because the number of liquid crystal cells increases and the difference in the RC load on the data line also increases as the liquid crystal display becomes a large screen.

Accordingly, it is an object of the present invention to provide a liquid crystal display device and a method of driving the same that can prevent delay of a data voltage due to RC delay while eliminating voltage instability.

According to an aspect of the present invention, there is provided a liquid crystal display device including a liquid crystal panel, a gate driver for applying a gate signal to the liquid crystal panel, and a gate driver for applying a variable pixel voltage signal to the liquid crystal panel, A data driver including an RC delay compensation output buffer unit, and a timing controller for controlling the gate driver and the data driver.

According to another aspect of the present invention, there is provided a method of driving a liquid crystal display, including: storing a portion of a pixel voltage signal in a capacitor every one scan period; applying a voltage stored in a capacitor to the pixel voltage signal; Lt; / RTI > to the pixel voltage signal.

Other objects and features of the present invention will become apparent from the following description of embodiments with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described with reference to FIGS. 4 to 10. FIG.

4 is a view showing a liquid crystal display device according to the present invention.

4, a liquid crystal display according to the present invention includes a liquid crystal panel 102 in which liquid crystal cells are arranged in a matrix form, a gate driver (not shown) for driving the gate lines GL1 to GLn of the liquid crystal panel 102 A data driver 104 for driving the data lines DL1 to DLm of the liquid crystal panel 102 and a timing controller 108 for controlling the gate driver 106 and the data driver 104 Respectively.

The liquid crystal panel 102 includes a thin film transistor TFT formed at each intersection of the gate lines GL1 through GLn and the data lines DL1 through DLm and a liquid crystal cell 107 connected to the thin film transistor TFT do. The thin film transistor TFT is turned on when a scan signal from the gate line GL, that is, a gate high voltage VGH, is supplied to supply a pixel signal from the data line DL to the liquid crystal cell 107. [ The thin film transistor TFT is turned off when the gate line voltage VGL is supplied from the gate line GL so that the pixel signal charged in the liquid crystal cell 107 is maintained.

The liquid crystal cell 107 is equivalently represented by a liquid crystal capacitance capacitor and includes a common electrode facing the liquid crystal and a pixel electrode connected to the thin film transistor (TFT). The liquid crystal cell 107 further includes a storage capacitor so that the charged pixel voltage signal stably remains until the next pixel voltage signal is charged. The storage capacitor is formed between the pixel electrode and the previous-stage gate line. In this liquid crystal cell 107, the alignment state of the liquid crystal having dielectric anisotropy varies according to the pixel voltage signal to be charged through the thin film transistor (TFT), and the light transmittance is adjusted to realize the gradation.

The timing controller 108 receives the gate control signals GSP, GSC and GOE and the data control signals SSP, SSC, SOE and POL using the synchronous signals V and H supplied from a video card Occurs. The gate control signals GSP, GSC and GOE are supplied to the gate driver 106 to control the gate driver and the data control signals SSP, SSC, SOE and POL are supplied to the data driver 104, And controls the driver. The timing controller 108 aligns pixel data VD of red (R), green (G), and blue (B) and supplies them to the data driver 104.

The data driver 104 is for supplying a pixel signal of one line for each horizontal period to the data lines DL1 to DLm, and particularly includes an RC delay compensation output buffer unit.

To this end, the data driver 104 includes a plurality of data ICs 116 as shown in FIG. The data ICs 116 supply the pixel signals to the data lines DL1 to DLm in response to the data control signals SSP, SSC, SOE, and POL supplied from the timing controller 108. [ At this time, the data ICs 116 convert the pixel data VD from the timing controller 108 into analog pixel signals using a gamma voltage from a gamma voltage generator (not shown) and output them.

Such a data IC will now be described with reference to FIG.

Each of the data ICs 116 includes a shift register unit 134 for supplying a sequential sampling signal as shown in FIG. 6, a latch unit 134 for sequentially latching and outputting the pixel data VD in response to a sampling signal, A DAC unit 138 for converting the pixel data VD from the latch unit 136 into a pixel voltage signal and a DAC unit 138 for converting the pixel data VD from the DAC 138 And an output buffer unit 146 for buffering the pixel voltage signal and for RC delay compensation. The data IC 116 further includes a signal controller 120 for relaying various control signals SSP, SSC, SOE, REV, and POL supplied from the timing controller 108 and the pixel data VD do.

The signal controller 120 controls the various control signals SSP, SSC, SOE, REV, and POL from the timing controller (not shown) and the pixel data VD to be output to the corresponding components.

The shift registers included in the shift register unit 134 sequentially shift the source start pulse SSP from the signal controller 120 in accordance with the source sampling clock signal SSC to output a sampling signal.

The latch unit 136 sequentially samples and latches the pixel data VD from the signal controller 120 in units of a predetermined unit in response to a sampling signal from the shift register unit 134. To this end, the latch unit 136 is composed of i latches for latching i (i is a natural number) pixel data VD, and each of the latches has a size corresponding to the number of bits of the pixel data VD .

Then, the latch unit 136 outputs i pixel data VD latched in response to the source output enable signal SOE from the signal controller 120 at the same time. In this case, the latch unit 136 restores and outputs the modulated pixel data VD so that the number of transition bits is reduced in response to the data inversion selection signal REV. This is because, in order to minimize electromagnetic interference (EMI) in data transmission in the timing control unit 108, pixel data VD whose number of transitions exceeds a reference value is modulated so as to reduce the number of transition bits.

The DAC unit 138 simultaneously converts the pixel data VD from the latch unit 136 into positive and negative polarity pixel voltage signals and outputs them.

The i output buffers included in the RC delay compensation output buffer unit 114 are constituted by a voltage follower connected in series to the i data lines D1 to Di, respectively. These output buffers buffer the pixel voltage signals from the DAC unit 138 and supply them to the data lines DL1 to DLi. In particular, the RC delay compensation output buffer portion output buffer portion 114 compensates for the delay of the pixel voltage signals according to the degree of the RC load on the data line.

7 is a circuit diagram showing one output stage of the output stages of the RC delay compensation output buffer section 114 formed by the number of data lines.

Referring to FIG. 7, the RC delay compensation output buffer unit 114 includes a pre-emphasis voltage generator 120 and a pre-emphasis voltage compensator 122.

The line-emphasis voltage generating unit 120 includes one operational amplifier 150 and two capacitors. The line-emphasis voltage generating unit 120 is connected to the pixel voltage input terminal Vin through the first to sixth switches S1 to S2, Emphasis voltage to the pixel-voltage signal which is the pixel-voltage signal.

The pixel voltage input terminal Vin is connected to the inverting terminal () of the operational amplifier 150 through the first switch S1.

The first capacitor C1 is connected to the first node n1 formed between the pixel voltage input terminal Vin and the first switch S1 through the second and third switches S2 and S3.

The second capacitor C2 is branched at the second node n2 formed between the second and third switches S2 and S3 and connected to the noninverting terminal of the operational amplifier 150 through the fourth switch S4. (-).

The third node n3 formed between the second capacitor C2 and the fourth switch S4 is connected to the inverting terminal (+) of the operational amplifier 150 through the fifth switch S5.

The line-emphasis voltage compensating unit 122 is for compensating an additional voltage value according to the position of the data line to the line-emphasis voltage generated in the line-emphasis voltage generating unit 120. [ The line-emphasis voltage compensating unit 122 is composed of one capacitor and two 2-to-1 MUXs.

The first MUX 140a and the second MUX 140b charge the third capacitor C3 with the compensation voltage ref generated by the compensation voltage generator 160 and generate To the applied line-emphasized voltage. That is, the switch-signal applied to the MUX is selected so as to select the compensation voltage ref in accordance with the switch timing for generating the line-emphasis voltage in the line-emphasis voltage generating section 120. [

The operation of the line-emphasis voltage generating unit 120 and the line-emphasis voltage compensating unit 122 will be described with reference to FIG. 8, which is a switch signal timing diagram.

The control signals (Ctrl1 to Ctrl3) shown in FIG. 8 are selection signals of the first to sixth switches S1 to S6 and two MUXs. The first control signal Ctrl1 controls the operation of the first, third and fourth switches S1, S3 and S4 and the second control signal Ctrl2 controls the operation of the second and fifth switches S2 , S5), and the third control signal (Ctrl3) controls the operation of the sixth switch (S6). The first and second control signals (Ctrl1, Ctrl2) are applied as selection signals of the MUX.

The RC delay compensation output buffer unit 114 according to the present invention firstly turns on the first, third and fourth switches S1, S3 and S4 by the first control signal Ctrl1 during 't0' . Accordingly, the line-emphasis voltage generating unit can be expressed by an equivalent circuit diagram as shown in FIG. That is, the pixel voltage signal Vvideo is amplified and outputted to the output buffer, and the output pixel voltage signal Vvideo is stored in the first and second capacitors C1 and C2 connected in series. At this time, the magnitude of the voltage stored in the first and second capacitors C1 and C2 is set by the following equation (1).

That is, the ratio of the first and second capacitors C1 and C2 can be adjusted to set the magnitude of the line-emphasis voltage generated by the line-emphasis voltage generator 120. [ In this case, the magnitude of the line-emphasis voltage generated by the line-emphasis voltage generator 120 applies a voltage value corresponding to the pixel cell located near the data driver 104. This is because the RC delay is not relatively large in the data line located in the pixel cell located near the data driver 104, so that when the line-emphasis voltage is applied in response to the data line having a large RC delay, the voltage may become unstable.

During the 't0' period, the first MUX 140a of the pre-emphasis voltage compensating unit 122 of the pre-emphasis voltage compensating unit 122 selects the first control signal Ctrl1 and outputs the seventh switch S7, And the sixth node n6 is discharged to GND as the first MUX 140a selects the first control signal Ctrl1 to turn on the eighth switch S8.

During the 't1' period, the fourth and fifth switches S4 and S5 are turned on by the second control signal Ctrl2. At this time, the line-emphasis voltage generating unit 120 generates the line- Lt; / RTI > Thus, the voltage across the first capacitor C1 at which the pre-emphasis voltage is stored is added to the pixel voltage signal Vvideo via the pixel voltage signal input terminal ().

Then, the compensation voltage generated by the pre-emphasis voltage compensating unit 122 is added. In more detail, the first MUX 140a turns on the seventh switch S7 by the second control signal Ctrl2, and accordingly the compensation voltage ref generated in the compensation voltage generator Is charged in the sixth node n6.

At this time, the compensation voltage ref charged to the sixth node n6 varies depending on the position of the data driver 104. [ That is, the compensation voltage generator 160 resets the counter to '0' in the sync interval of the vertical synchronization signal Vsync, and whenever the data-in-assertion (DE) signal rises, the counter Increase the output value. As a result, the digital-analog-converter (DAC) raises the compensation voltage, which is the output voltage. In other words, the compensation voltage ref applied to the pixel cell corresponding to the gate line in the data driver 104 rises.

That is, in the 't1' period, the compensating voltage ref having a magnitude proportional to the distance from the data driver 104 to the line-emphasis voltage generated by the line-emphasis voltage generating unit 120 is applied to the pixel voltage signal Vvideo Added. Accordingly, it is possible to apply an effective compensation voltage to the RC delay while solving the voltage instability that occurs when applying the conventional uniform pre-emphasis voltage.

During the 't2' period, the first, third, fourth and sixth switches S6 are turned on by the first and third control signals, so that the pre-emphasis voltage generator 120 generates the pre- Equivalent circuit. Thus, the first capacitor C1 storing the pre-emphasis voltage is short-circuited to be completely discharged. Also, the first MUX 140a of the pre-emphasis voltage compensating unit 122 selects the first control signal Ctrl1 to turn on the seventh switch S7, and the first MUX 140a turns on the first As the control signal Ctrl1 is selected and the eighth switch S8 is turned on, the compensation voltage ref charged in the third capacitor C3 is discharged to GND.

Accordingly, in the 't2' period, only the pixel voltage signal Vvideo from which the line-emphasis voltage or the compensation voltage is removed is output through the output buffer.

The above method has described a method of applying a pre-emphasis voltage when the POL signal is a high signal. Similarly, when the POL signal is low, the switching functions of the first and second MUXs 140b of the pre-emphasis voltage compensating unit 122 of the pre-emphasis voltage compensating unit 122 are reversed, Is the same as the above-mentioned method.

As described above, according to the liquid crystal display device and the driving method thereof according to the present invention, it is possible to prevent the data voltage from being delayed by the RC delay by applying the line-emphasis voltage to the pixel voltage signal. In particular, by applying a variable compensation voltage according to the position of the data line to the pre-emphasis voltage, it is possible to eliminate voltage instability caused by applying a uniform pre-emphasis voltage.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (10)

A liquid crystal panel; A gate driver for applying a gate signal to the liquid crystal panel; A data driver including an RC delay compensation output buffer for applying a variable pixel voltage signal to the liquid crystal panel according to a position of a data line; And And a timing controller for controlling the gate driver and the data driver, Wherein the RC delay compensation output buffer unit comprises: A line-emphasizing voltage generating unit for generating a line-emphasizing voltage for raising a voltage of a part of the pixel voltage signal; And a line-emphasizing voltage compensating unit for generating a compensating voltage having a variable value according to a position of the data line for raising the line-emphasizing voltage, The line-emphasis voltage compensation unit includes: And a compensation voltage generator for generating a compensation voltage having a variable value according to the position of the data line, Wherein the compensation voltage generator comprises: And generates a compensating voltage which is counted by the data enable signal and varies according to the position of the data line. delete The method according to claim 1, Wherein the line-emphasis voltage generator An operational amplifier connected to a pixel voltage input terminal through a first switch; A first capacitor branched from a first node formed between the pixel voltage input terminal and the first switch and connected through the second and third switches; A second capacitor branching at a second node formed between the second and third switches and connected to a non-inverting terminal of the operational amplifier through a fourth switch; A fifth switch connecting a third node formed between the second capacitor and the fourth switch and an inverting terminal of the operational amplifier; And a sixth switch formed between a fourth node formed between the second node and the second capacitor and a fifth node formed between the fourth switch and the non-inverting terminal of the operational amplifier. Device. The method of claim 3, The first, third, and fourth switches are turned on by a first control signal during a first period to output the pixel voltage signal to the operational amplifier, The second and fifth switches are turned on by a second control signal for a second period to output a pixel voltage signal added with the line-emphasized voltage to the operational amplifier, And the sixth switch is turned on as the first, second, third, and fourth switches by the third control signal during the third period to output the pixel voltage signal to the operational amplifier. Display device. 5. The method of claim 4, The line-emphasis voltage compensating unit A third capacitor for charging the compensation voltage; A grounding unit for discharging a voltage charged in the third capacitor; A seventh switch formed between the compensation voltage generator and the third capacitor; And an eighth switch formed between the third capacitor and the grounding unit. 6. The method of claim 5, The line-emphasis voltage compensating unit If the polarity inversion signal is high, during the second period A first MUX for turning on the seventh switch; And a second MUX for turning off the eighth switch. The method according to claim 6, The line-emphasis voltage compensating unit And turns on the seventh switch and turns on the eighth switch during the second period when the polarity inversion signal is low. 6. The method of claim 5, The compensation voltage generator And reset by a vertical synchronization signal. A method of driving a liquid crystal display device which applies a pixel voltage signal output from an output buffer to a pixel cell through a data line, Generating a line-emphasizing voltage that raises a voltage of a portion of the pixel voltage signal; Generating a compensation voltage having a variable value according to a position of the data line for raising the pre-emphasis voltage; The compensation voltage generator And generating a compensating voltage which is counted by the data enable signal and is variable according to the position of the data line. 10. The method of claim 9, Wherein the compensation voltage is reset by a vertical synchronization signal and counted and increased by a data enable signal.

Images