KR20080107064A - Liquid crystal display and method of dirving the same - Google Patents

Abstract

A liquid crystal display and a driving method thereof are provided to prevent voltage instability by applying a variable compensation voltage to a pre-emphasis voltage according to a position of a data line. A gate driver(106) is used for applying a gate signal to a liquid crystal panel(102). A data driver(104) includes an RC delay compensation output buffer unit(144) for applying a variable pixel voltage signal to the liquid crystal panel according to a position of a data line. A timing control unit(108) controls the gate driver and the data driver.

Description

Liquid Crystal Display And Method Of Dirving The Same

1 is a view showing a conventional liquid crystal display device.

2 is an equivalent circuit diagram of a data line.

3 illustrates a conventional line-high voltage.

4 is a view showing a liquid crystal display device according to the present invention.

5 shows a data driver according to the present invention;

6 illustrates a data drive integrated circuit in accordance with the present invention.

7 is a circuit diagram showing an output buffer according to the present invention.

8 is a timing diagram showing a control signal of an output buffer;

9 to 10 are diagrams showing an equivalent circuit diagram of the line-high voltage generator according to the timing of the control signal.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving method thereof, and more particularly, to a liquid crystal display device and a driving method thereof capable of preventing a data voltage delay due to RC delay while eliminating voltage instability.

A liquid crystal display device is a display device that displays an image by adjusting the light transmittance of the liquid crystal using an electric field.

That is, the liquid crystal display device adjusts the light transmittance by adjusting the light transmittance by changing the arrangement state of the liquid crystal having dielectric anisotropy according to the pixel voltage signal charged through the thin film transistor (TFT) to the liquid crystal cell () formed in a matrix in the liquid crystal panel. Implement

The pixel voltage signal for gray scale expression is applied to the liquid crystal cell 7 via the data lines through the data driver shown in FIG.

In this case, the data line for applying the pixel voltage signal may be represented by an equivalent circuit as shown in FIG. 2. Accordingly, the pixel voltage signal Vvideo output from the data driver is delayed and output via the data line due to RC delay.

As a method for preventing the delay of the pixel voltage signal due to the RC delay, there has been proposed a method of driving a liquid crystal display device in which a pre-emphasis voltage is applied to the pixel voltage signal. This is due to the driving method of the liquid crystal display device disclosed in the application number 2002-76164, which prevents the pixel voltage signal from being delayed by RC delay by applying a pre-high voltage to the pixel voltage signal at the beginning of the pixel voltage signal as shown in FIG. Way.

However, the conventional method of applying the pre-high voltage is difficult to achieve the RC stabilization and voltage stabilization at the same time between all the pixels because the pre-high voltage of the same magnitude is applied to all pixels. This is because the pixel voltage signal is delayed by RC delay because each pixel of the liquid crystal panel is not constant from the data driver. The pre-high voltage applied to compensate for the delay of the pixel voltage signal is the same. Because.

That is, as shown in FIG. 1, the point A close to the data driver and the point B far from the data driver have a difference in RC load, and accordingly, a pixel voltage signal is delayed. For example, since the B point far from the data driver has a large RC load, applying a pre-high voltage to the B point causes a problem in voltage stabilization at the A point. Alternatively, if the magnitude of the line-high voltage is set corresponding to the RC load at point A, the point B is insufficient to compensate for the delay of the pixel voltage signal due to the RC delay.

This phenomenon is more difficult to achieve both voltage stabilization and compensation of the delay of the pixel voltage signal because the number of liquid crystal cells increases as the liquid crystal display becomes larger and the difference in RC load on the data line increases.

Accordingly, it is an object of the present invention to provide a liquid crystal display device and a driving method thereof capable of preventing a voltage voltage delay caused by an RC delay while eliminating voltage instability.

In order to achieve the above object, a liquid crystal display according to the present invention is a liquid crystal panel, a gate driver for applying a gate signal to the liquid crystal panel, and for applying a variable pixel voltage signal depending on the position of the data line to the liquid crystal panel. And a timing controller for controlling the gate driver and the data driver including an RC delay compensation output buffer unit.

The method of driving the liquid crystal display according to the present invention includes the steps of storing a part of the pixel voltage signal in the capacitor every one scan period, applying the voltage stored in the capacitor to the pixel voltage signal, and variable according to the position of the data line. Applying a phosphorus compensation voltage to the pixel voltage signal.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 10.

4 is a view showing a liquid crystal display device according to the present invention.

Referring to FIG. 4, the liquid crystal display according to the present invention includes a liquid crystal panel 102 in which liquid crystal cells are arranged in a matrix, and a gate driver for driving gate lines GL1 to GLn of the liquid crystal panel 102. 106, the data driver 104 for driving the data lines DL1 to DLm of the liquid crystal panel 102, and the timing controller 108 for controlling the gate driver 106 and the data driver 104. Equipped.

The liquid crystal panel 102 includes a thin film transistor TFT formed at each intersection of the gate lines GL1 to GLn and the data lines DL1 to DLm, and a liquid crystal cell 107 connected to the thin film transistor TFT. do. The thin film transistor TFT is turned on when the scan signal from the gate line GL, that is, the gate high voltage VGH is supplied, and supplies the pixel signal from the data line DL to the liquid crystal cell 107. The thin film transistor TFT is turned off when the gate low voltage VGL is supplied from the gate line GL to maintain the pixel signal charged in the liquid crystal cell 107.

The liquid crystal cell 107 is equivalently represented by a liquid crystal capacitor, and includes a common electrode facing each other with a liquid crystal interposed therebetween and a pixel electrode connected to a thin film transistor TFT. The liquid crystal cell 107 further includes a storage capacitor such that the charged pixel voltage signal is stably maintained until the next pixel voltage signal is charged. The storage capacitor is formed between the pixel electrode and the previous gate line. The liquid crystal cell 107 realizes gradation by adjusting the light transmittance by changing the arrangement state of the liquid crystal having dielectric anisotropy according to the pixel voltage signal charged through the thin film transistor (TFT).

The timing controller 108 controls the gate control signals GSP, GSC, and GOE and the data control signals SSP, SSC, SOE, and POL using the synchronization signals V and H supplied from a video card (not shown). Occurs. The gate control signals GSP, GSC, and GOE are supplied to the gate driver 106 to control the gate driver, and the data control signals SSP, SSC, SOE, and POL are supplied to the data driver 104 to provide data. Take control of the driver. In addition, the timing controller 108 aligns the red (R), the green (G), and the blue (B) pixel data VD and supplies them to the data driver 104.

The data driver 104 supplies a pixel signal for one line to the data lines DL1 to DLm every horizontal period, and in particular, includes a RC delay compensation output buffer unit.

For this purpose, the data driver 104 includes a plurality of data ICs 116 as shown in FIG. The data ICs 116 supply the pixel signal to the data lines DL1 to DLm in response to the data control signals SSP, SSC, SOE, and POL supplied from the timing controller 108. At this time, the data ICs 116 convert the pixel data VD from the timing controller 108 into an analog pixel signal using a gamma voltage from a gamma voltage generator (not shown) and output the analog pixel signal.

This data IC will be described with reference to FIG. 6 as follows.

Each of the data ICs 116 includes a shift register unit 134 for supplying a sequential sampling signal as shown in FIG. 6, and a latch unit for sequentially latching and simultaneously outputting pixel data VD in response to the sampling signal. 136, a digital-to-analog converter (hereinafter referred to as " DAC unit ") 138 for converting the pixel data VD from the latch unit 136 into a pixel voltage signal, and from the DAC 138. An output buffer unit 146 is provided to buffer the pixel voltage signal and to compensate for the RC delay. In addition, the data IC 116 further includes a signal controller 120 which relays various control signals (SSP, SSC, SOE, REV, POL, etc.) and pixel data VD supplied from the timing controller 108. do.

The signal controller 120 controls various control signals (SSP, SSC, SOE, REV, POL, etc.) and pixel data VD from the timing controller (not shown) to be output to the corresponding components.

The shift registers included in the shift register unit 134 sequentially shift the source start pulse SSP from the signal controller 120 according to the source sampling clock signal SSC and output the sampling signal.

The latch unit 136 sequentially samples and latches the pixel data VD from the signal controller 120 in predetermined units in response to the sampling signal from the shift register unit 134. To this end, the latch unit 136 is composed of i latches for latching i (i is a natural number) pixel data VD, and each of the latches has a size corresponding to the number of bits of the pixel data VD. .

Subsequently, the latch unit 136 simultaneously outputs the latched i pixel data VDs in response to the source output enable signal SOE from the signal controller 120. In this case, the latch unit 136 restores and outputs the pixel data VD modulated to reduce the number of transition bits in response to the data inversion selection signal REV. This is because the timing controller 108 modulates and supplies the pixel data VD having a higher number of transition bits to reduce the number of transition bits in order to minimize electromagnetic interference (EMI) during data transmission.

The DAC unit 138 simultaneously converts the pixel data VD from the latch unit 136 into positive and negative pixel voltage signals and outputs the same.

The i output buffers included in the RC delay compensation output buffer unit 114 are constituted by a voltage follower connected to the i data lines D1 to Di in series. These output buffers buffer the pixel voltage signals from the DAC unit 138 and supply them to the data lines DL1 to DLi. In particular, the RC delay compensation output buffer unit The output buffer unit 114 compensates the delay of the pixel voltage signals according to the degree of RC load on the data line.

FIG. 7 is a circuit diagram illustrating one output terminal of an output terminal of the RC delay compensation output buffer unit 114 formed by the number of data lines.

Referring to FIG. 7, the RC delay compensation output buffer unit 114 includes a pre-high voltage generator 120 and a pre-high voltage compensator 122.

The pre-high voltage generator 120 includes one operational amplifier 150 and two capacitors, and is applied through the pixel voltage input terminal Vin under the control of the first to sixth switches S1 to S2. The line-high voltage is added to the pixel voltage signal.

The pixel voltage input terminal Vin is connected to the inverting terminal of the operational amplifier 150 through the first switch S1.

The first capacitor C1 is branched from the first node n1 formed between the pixel voltage input terminal Vin and the first switch S1 to be connected through the second and third switches S2 and S3.

The second capacitor C2 is branched from the second node n2 formed between the second and third switches S2 and S3, and the non-inverting terminal of the operational amplifier 150 is provided through the fourth switch S4. Is connected to (-).

The third node n3 formed between the second capacitor C2 and the fourth switch S4 is connected to the inverting terminal + of the operational amplifier 150 through the fifth switch S5.

The pre-high voltage compensator 122 compensates for an additional voltage value according to the position of the data line to the pre-high voltage generated by the pre-high voltage generator 120. The pre-high voltage compensation unit 122 is composed of one capacitor and two 2-to-1 MUXs.

The first MUX 140a and the second MUX 140b charge the compensation voltage ref generated by the compensation voltage generator 160 to the third capacitor C3 and generate the voltage in the pre-high voltage generator 120. In addition to the pre-high voltage. In other words, the line-high voltage generator 120 selects a switch signal applied to the MUX to select the compensation voltage ref according to the switch timing of generating the line-high voltage.

The operation of the pre-high voltage generator 120 and the pre-high voltage compensator 122 will be described with reference to FIG. 8, which is a switch signal timing diagram.

The control signals Ctrl1 to Ctrl3 illustrated in FIG. 8 are selection signals of the first to sixth switches S1 to S6 and two MUXs. In more detail, the first control signal Ctrl1 controls the operations of the first, third and fourth switches S1, S3, and S4, and the second control signal Ctrl2 controls the second and fifth switches S2. S5 controls the operation, and the third control signal Ctrl3 controls the operation of the sixth switch S6. The first and second control signals Ctrl1 and Ctrl2 are applied as selection signals of the MUX.

In the RC delay compensation output buffer unit 114 according to the present invention, first, third, and fourth switches S1, S3, and S4 are turned on by the first control signal Ctrl1 during the 't0' period. . Accordingly, the line-high voltage generator can be represented by the equivalent circuit diagram of FIG. 9. That is, the pixel voltage signal Vvideo is amplified and output by the output buffer, and the output pixel voltage signal Vvideo is stored in the first and second capacitors C1 and C2 connected in series. At this time, the magnitudes of the voltages stored in the first and second capacitors C1 and C2 are set by Equation 1 below.

That is, the magnitude of the line-high voltage generated by the line-high voltage generator 120 may be set by adjusting the ratio of the first and second capacitors C 1 and C 2. At this time, the magnitude of the line-high voltage generated by the line-high voltage generator 120 applies a voltage value corresponding to the pixel cell located close to the data driver 104. This is because the RC delay is not relatively large in the data line located in the pixel cell located close to the data driver 104, and thus, when the line-high voltage is applied to the data line having the large RC delay, the voltage may be unstable.

In the 't0' period, the line-high voltage compensation unit 122 selects the first control signal Ctrl1 by the first MUX 140a of the line-high voltage compensation unit 122 to perform the seventh switch S7. Turn on, and the sixth node n6 is discharged to GND as the first MUX 140a selects the first control signal Ctrl1 to turn on the eighth switch S8.

During the 't1' period, the fourth and fifth switches S4 and S5 are turned on by the second control signal Ctrl2, and the line-high voltage generator 120 is equivalent to the circuit shown in FIG. It is expressed as Accordingly, the voltage across the first capacitor C1 in which the pre-high voltage is stored is added to the pixel voltage signal Vvideo via the pixel voltage signal input terminal.

Then, the compensation voltage generated by the pre-high voltage compensation unit 122 is added. In more detail, the first MUX 140a turns on the seventh switch S7 by the second control signal Ctrl2, and accordingly, the compensation voltage ref generated by the compensation voltage generator ) Is charged to the sixth node n6.

In this case, the compensation voltage ref charged in the sixth node n6 varies depending on the position of the data driver 104. That is, the compensation voltage generator 160 resets the counter to '0' in the sync period of the vertical synchronization signal Vsync, and the counter is reset whenever the data enable signal DE rises. Increase the output value. Accordingly, the digital-analog converter (DAC) raises the compensation voltage, which is the output voltage. In other words, the compensation voltage ref applied to the pixel cell corresponding to the gate line in the data driver 104 increases.

That is, in the 't1' period, the compensation voltage ref having a magnitude proportional to the distance from the data driver 104 to the line-high voltage generated by the line-high voltage generator 120 is applied to the pixel voltage signal Vvideo. Is added. Accordingly, it is possible to apply an effective compensation voltage for the RC delay while solving the voltage instability generated when applying the conventional monolithic pre-highlight voltage.

In the 't2' period, the first, third, fourth, and sixth switches S6 are turned on by the first and third control signals, and the pre-high voltage generator 120 is shown in FIG. 11. It is represented by an equivalent circuit. Accordingly, the first capacitor C1 in which the pre-high voltage is stored is short-circuited and completely discharged. In addition, the first MUX 140a of the line-high voltage compensator 122 selects the first control signal Ctrl1 to turn on the seventh switch S7, and the first MUX 140a may turn on the first MUX 140a. As the eighth switch S8 is turned on by selecting the control signal Ctrl1, the compensation voltage ref charged in the third capacitor C3 is discharged to GND.

Accordingly, in the 't2' period, only the pixel voltage signal Vvideo from which the pre-high voltage or the compensation voltage is removed is output through the output buffer.

The above-described method has described a method of applying the pre-high voltage when the POL signal is a high signal. Similarly, when the POL signal is low, the switching roles of the first and second MUXs 140b of the line-high voltage compensation unit 122 of the line-high voltage compensation unit 122 are reversed. Is the same as the method described above.

As described above, according to the liquid crystal display and the driving method thereof according to the present invention, it is possible to prevent the data voltage from being delayed by the RC delay by applying the pre-high voltage to the pixel voltage signal. In particular, by applying a compensation voltage that is variable according to the position of the data line to the line-high voltage, voltage instability caused by applying the uniform line-high voltage can be solved.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

A liquid crystal panel; A gate driver for applying a gate signal to the liquid crystal panel; A data driver including an RC delay compensation output buffer unit for applying a pixel voltage signal variable according to a position of a data line to the liquid crystal panel; And a timing controller for controlling the gate driver and the data driver. The method of claim 1, The RC delay compensation output buffer unit A line-high voltage generator for generating a line-high voltage to increase a voltage of a portion of the pixel voltage signal; And a line-high voltage compensation unit for generating a compensation voltage having a variable value according to the position of the data line for increasing the line-high voltage. The method of claim 2, The pre-high voltage generator An operational amplifier connected through the pixel voltage input terminal and the first switch; A first capacitor branched from a first node formed between the pixel voltage input terminal and the first switch and connected through the second and third switches; A second capacitor branched at a second node formed between the second and third switches and connected to the non-inverting terminal of the operational amplifier through a fourth switch; A fifth switch connecting the third node formed between the second capacitor and the fourth switch and the inverting terminal of the operational amplifier; And a fourth node formed between the second node and the second capacitor, and a sixth switch formed between the fourth node and a fifth node formed between the non-inverting terminal of the operational amplifier. Device. The method of claim 2, First, third and fourth switches are turned on by a first control signal during a first period to output the pixel voltage signal to the operational amplifier, The second and fifth switches are turned on by the second control signal during the second period to output the pixel voltage signal added with the pre-high voltage to the operational amplifier, And the sixth switch is turned on together with the first, second, third and fourth switches by a third control signal for a third period to output the pixel voltage signal to the operational amplifier. Device. The method of claim 2, The pre-high voltage compensation unit A compensation voltage generator configured to generate a compensation voltage having a variable value according to the position of the data line; A third capacitor for charging the compensation voltage; A grounding unit for discharging a voltage charged in the third capacitor; A seventh switch formed between the compensation voltage generator and the third capacitor And an eighth switch formed between the third capacitor and the ground portion. The method of claim 5, wherein The pre-high voltage compensation unit During the second period when the polarity inversion signal is high; A first MUX for turning on the seventh switch; And a second MUX for turning off the eighth switch. The method of claim 6, The pre-high voltage compensation unit And the seventh switch is turned off and the eighth switch is turned on for the second period when the polarity inversion signal is low. The method of claim 5, wherein The compensation voltage generator And a compensation voltage which is reset by the vertical synchronization signal and counted by the data enable signal to generate a compensation voltage variable according to the position of the data line. A driving method of a liquid crystal display device which applies a pixel voltage signal output from an output buffer to a pixel cell through a data line. Every 1 scan cycle Storing a portion of the pixel voltage signal in a capacitor; Applying a voltage stored in the capacitor to the pixel voltage signal; And applying a compensation voltage variable according to the position of a data line to the pixel voltage signal. The method of claim 9, And the compensation voltage is reset by a vertical synchronization signal, and counted and increased by a data enable signal.

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