KR20080054545A - Liquid crystal display - Google Patents

Abstract

An LCD(Liquid Crystal Display) is provided to fix a common voltage to reduce power consumption and vary the voltage of a storage signal applied to a storage electrode line to increase a pixel electrode voltage range, thereby improving the texture of a displayed image. An LCD includes a plurality of gate lines for transmitting gate signals, a plurality of data lines for transmitting data voltages, a plurality of storage electrode lines for transmitting storage signals, a switching element connected to a corresponding gate lines and a corresponding data line, and a liquid crystal capacitor connected between the switching element and a common voltage. The LCD further includes a plurality of pixels(PX) arranged in a matrix, each of which includes a storage capacitor connected between the switching element and a corresponding storage electrode line, a plurality of first signal generator circuits(700a) which are arranged at one side of an LCD assembly(300), generate the storage signals based on at least one control signal and at least one gate signal and apply the storage signals to a plurality of first storage electrode lines, and a plurality of second signal generating circuits(700b) which are arranged in at the other side of the LCD assembly, generate the storage signals based on at least one control signal and at least one gate signal and apply the storage signals to a plurality of second storage electrode lines.

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY}

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

2 is an equivalent circuit diagram of one pixel in a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a circuit diagram of a signal generation circuit according to an embodiment of the present invention.

  4 is a layout diagram illustrating input and output relationships between a signal generation circuit, a gate signal, and a sustain signal according to an exemplary embodiment of the present invention.

FIG. 5A is a timing diagram of signals used in the liquid crystal display including the signal generation circuit shown in FIG. 3 when the odd numbered frame is used. FIG.

FIG. 5B is a timing diagram of signals used in the liquid crystal display including the signal generation circuit shown in FIG. 3 when the even-numbered frame is used. FIG.

* Description of the Drawing Symbols *

3: liquid crystal layer 100, 200: substrate

230: color filter 270: common electrode

300: liquid crystal panel assembly 400: gate driver

400a and 400b: gate driver circuit 500: data driver

600: signal controller 700: maintenance signal generator

700a, 700b: holding signal generating circuit 710: signal generating circuit

800: gray voltage generator PX: pixel

G ₁ -G _2n : Gate line D ₁ -D _m : Data line

S ₁ -S _2n : sustain electrode lines C1, C2: capacitor

Clc: Liquid Crystal Capacitor Cst: Holding Capacitor

Q: switching element Tr1-Tr7: transistor

CONT1: gate control signal CONT2: data control signal

CONT3: Hold control signal STV1, STV2: Vertical sync start signal

Von: gate-on voltage Voff; Gate-off voltage

OE: Output enable signal LOAD: Load signal

HCLK: data clock signal RVS: inverted signal

DAT: Video data CK1, CK1B, CK2: Clock signal

VBE_L, VBE_R: Enable signal VBD_L, VBD_R: Disable signal

Vcom: Common Voltage

The present invention relates to a liquid crystal display device.

A typical liquid crystal display (LCD) includes two display panels provided with pixel electrodes and common electrodes, and a liquid crystal layer having dielectric anisotropy interposed therebetween. The pixel electrodes are arranged in a matrix and connected to switching elements such as thin film transistors (TFTs) to receive data voltages one by one in sequence. The common electrode is formed over the entire surface of the display panel and receives a common voltage. The pixel electrode, the common electrode, and the liquid crystal layer therebetween form a liquid crystal capacitor, and the liquid crystal capacitor becomes a basic unit that forms a pixel together with a switching element connected thereto.

In such a liquid crystal display, a voltage is applied to two electrodes to generate an electric field in the liquid crystal layer, and the intensity of the electric field is adjusted to adjust the transmittance of light passing through the liquid crystal layer to obtain a desired image.

However, in a liquid crystal display, when an electric field in one direction is applied to the liquid crystal layer for a long time, the liquid crystal deteriorates and the image quality is deteriorated.

In addition, since the response speed of the liquid crystal molecules is slow, it takes some time for the voltage charged in the liquid crystal capacitor (hereinafter referred to as "pixel voltage") to reach a target voltage, that is, a voltage at which the desired luminance can be obtained. Depends on the difference from the voltage previously charged in the liquid crystal capacitor. Therefore, for example, when the difference between the target voltage and the previous voltage is large, applying only the target voltage from the beginning may not reach the target voltage during the time that the switching element is turned on. Therefore, the desired pixel voltage is not obtained at the required time.

  An object of the present invention is to improve the image quality of a liquid crystal display device.

According to an exemplary embodiment of the present invention, a liquid crystal display includes a plurality of gate lines for transmitting a gate signal including a gate on voltage and a gate off voltage, a plurality of data lines for transmitting a data voltage, and a plurality of holding lines for transmitting a sustain signal. A matrix including an electrode line, a switching element connected to said gate line and said data line, a liquid crystal capacitor connected between said switching element and a common voltage, and a storage capacitor connected between said switching element and said sustain electrode line, respectively. A plurality of pixels arranged in a shape of a plurality of pixels, disposed in a first direction of the liquid crystal panel assembly, and generating the sustain signal based on at least one control signal and at least one gate signal, and applying the sustain signal to the plurality of first storage electrode lines; A plurality of first signal generation circuits, and a second room facing the first direction A plurality of second signal generating circuits disposed in the second signal generating circuit to generate the sustain signal based on at least one control signal and at least one gate signal to apply the sustain signal to a plurality of second sustain electrode lines; The sustain signal applied to each pixel formed in the first or second pixel row is changed in voltage level immediately after the liquid crystal capacitor and the sustain capacitor are completely charged with the data voltage, and the first and second pixel rows The polarities of the data voltages applied to the pixel rows are opposite to each other.

The sustain signal may change from a high level to a low level when the charged data voltage is negative, or the sustain signal may change from a low level to a high level when the charged data voltage is positive.

The polarity of the data voltage applied to the same pixel row may be reversed for each frame.

In two adjacent frames, pixel rows in which the voltage level of the sustain signal is changed are different from each other.

The common voltage may have a constant value.

The liquid crystal display device is disposed in the first direction and is disposed in the first direction and the second gate line to apply the gate signals to a plurality of first gate lines. The display device may further include a second gate driver configured to apply a gate signal, wherein the first signal generator receives a gate signal from the first gate driver, and the second signal generator includes a gate signal from the second gate driver. Can be authorized.

Each of the first and second signal generation circuits includes a signal input unit to which first and second control signals and first and second gate signals are input, a first clock signal, and a drive control signal from the signal input unit. A sustain signal applying unit for outputting the first control signal as a sustain signal, a second and third clock signals applied thereto, a control unit operating according to the driving control signal, and the sustain signal according to an operation of the control unit. It may include a signal holding unit for holding the sustain signal output from the applying unit for a predetermined time.

Preferably, the waveforms of the first and second control signals applied to the first signal generation circuit and the first and second control signals applied to the second signal generation circuit are opposite to each other.

The waveforms of the first and second control signals may be opposite to each other.

The waveforms of the first and second control signals may be inverted for each frame.

The difference between the timing of applying the gate-on voltage of the first gate signal and the timing of applying the gate-on voltage of the second gate signal may be about 2H.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

1 is a block diagram of a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is an equivalent circuit diagram of one pixel in the liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, a liquid crystal display according to an exemplary embodiment of the present invention includes a liquid crystal panel assembly 300, a gate driver 400, and a data driver 500. ), A gray voltage generator 800, a storage signal generator 700, and a signal controller 600.

Referring to FIG. 1, the liquid crystal panel assembly 300 may include a plurality of signal lines G ₁ -G _2n, D ₁ -D _m , S ₁ -S _2n , and a plurality of pixels when viewed in an equivalent circuit. (PX). On the other hand, in the structure shown in FIG. 2, the liquid crystal panel assembly 300 includes lower and upper panels 100 and 200 facing each other and a liquid crystal layer 3 interposed therebetween.

The signal lines G ₁ -G _2n , D ₁ -D _m , and S ₁ -S _2n are provided on the lower panel 100, and the plurality of gate lines G ₁ -G _2n, and a plurality of data lines D ₁ -D _m ) and a plurality of storage electrode lines S ₁ -S _2n .

The gate lines G ₁ -G _2n transfer gate signals (also referred to as "scan signals"), and the storage electrode lines S ₁ -S _2n are alternately arranged with the gate lines G ₁ -G _2n and are held. A signal is transmitted, and the data lines D ₁ -D _m carry data voltages.

The gate lines G ₁ -G _2n and the storage electrode lines S ₁ -S _2n extend substantially in the row direction and are substantially parallel to each other, and the data lines D ₁ -D _m extend substantially in the column direction and Almost parallel

As shown in FIG. 1, the pixel PX is connected to the gate lines G ₁ -G _2n , the data lines D ₁ -D _m , and the sustain electrode lines S ₁ -S _2n , and has a matrix form. Is arranged.

Each pixel PX, for example, the i-th (i = 1, 2, ..., 2n) general gate line G _j and the j-th (j = 1, 2, ..., m) data line ( D _j pixels (PX) connected to) is also the liquid crystal capacitor, connected to the signal line (G _i, the switching element (Q) connected to D _j) and hence, as shown in 2 (liquid crystal capacitor) (Clc), and the switching and a storage capacitor element (storage capacitor) (Cst) connected to the (Q) and the i-th sustain electrode line (S _i).

The switching element Q is a three-terminal element of a thin film transistor or the like provided in the lower panel 100, the control terminal of which is connected to the gate line G _i , and the input terminal of which is connected to the data line D _j . The output terminal is connected to the liquid crystal capacitor Clc and the storage capacitor Cst.

The liquid crystal capacitor Clc has two terminals, the pixel electrode 191 of the lower panel 100 and the common electrode 270 of the upper panel 200, and the liquid crystal layer 3 between the two electrodes 191 and 270 is a dielectric material. Function as. The pixel electrode 191 is connected to the switching element Q, and the common electrode 270 is formed on the front surface of the upper panel 200 and receives the common voltage Vcom. The common voltage Vcom is a direct current (DC) voltage having a predetermined magnitude. Unlike in FIG. 2, the common electrode 270 may be provided in the lower panel 100. In this case, at least one of the two electrodes 191 and 270 may be formed in a linear or bar shape.

Maintained for an auxiliary role of the liquid crystal capacitor (Clc), the capacitor (Cst) is performed by the pixel electrode 191 and the sustain electrode lines (S _i) are overlapped with an insulator in between.

On the other hand, in order to implement color display, each pixel PX uniquely displays one of the primary colors (spatial division) or each pixel PX alternately displays the primary colors over time (time division). The desired color is recognized by the spatial and temporal sum of these primary colors. Examples of the primary colors include three primary colors such as red, green, and blue. FIG. 2 illustrates that each pixel PX includes a color filter 230 representing one of the primary colors in an area of the upper panel 200 corresponding to the pixel electrode 191 as an example of spatial division. Unlike in FIG. 2, the color filter 230 may be disposed above or below the pixel electrode 191 of the lower panel 100.

The liquid crystal panel assembly 300 is provided with at least one polarizer (not shown).

Referring back to FIG. 1, the gray voltage generator 800 generates a total gray voltage related to the transmittance of the pixel PX or a limited number of gray voltages (hereinafter referred to as a “reference gray voltage”). The reference gray level voltage may include a positive value and a negative value with respect to the common voltage Vcom.

The gate driver 400 includes first and second gate driver circuits 400a and 400b disposed at both sides of the liquid crystal panel assembly 300, for example, at right and left ends thereof.

The first gate driving circuit 400a is connected at one end with odd-numbered general gate lines G ₁ , G ₃ , and G _2n-1 , and the second gate driving circuit 400b has an even-numbered gate line ( G ₂ , G ₄ ,, G _2n ) is connected at one end. However, the present invention is not limited thereto, and on the contrary, odd-numbered gate lines G ₁ , G ₃ , and G _{2n-1 are} connected to the second gate driving circuit 400b and even-numbered gate lines G ₂ , G ₄ , and G _2n ) may be connected to the first gate driving circuit 400a.

The first and second gate driving circuits 400a and 400b apply gate signals formed of a combination of the gate on voltage Von and the gate off voltage Voff to the connected gate lines G ₁ -G _2n .

The gate driver 400 is integrated in the liquid crystal panel assembly 300 along with the signal lines G ₁ -G _2n , D ₁ -D _m , S ₁ -S _2n , and the thin film transistor switching element Q. However, the gate driver 400 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or mounted on a flexible printed circuit film (not shown) to form a TCP carrier. It may be attached to the liquid crystal panel assembly 300 in the form of a package) or mounted on a separate printed circuit board (not shown).

The sustain signal generator 700 is disposed adjacent to both sides of the liquid crystal panel assembly 300, for example, the first and second gate driving circuits 400a and 400b, respectively, so that the first and second gate driving circuits are adjacent to each other. First and second sustain signal generation circuits 700a and 700b receiving gate signals from 400a and 400b.

That is, the first sustain signal generation circuit 700a is disposed on the left side of the liquid crystal panel assembly 300 so that the even-numbered sustain electrode lines S ₂ , S ₄ , S _2n , and the odd-numbered gate lines G ₁ , G ₃ , , G _2n-1 ), and a sustain signal having a high level voltage and a low level voltage is applied to even-numbered sustain electrode lines S ₂ , S ₄ , and S _2n . On the other hand, the second sustain signal generation circuit 700b is disposed on the right side of the liquid crystal panel assembly 300 so that the odd-numbered sustain electrode lines S ₁ , S ₃ ,, S _2n-1 , and the even _- numbered gate lines G ₂ , G ₄ , and G _2n ), and a sustain signal having a corresponding state is applied to odd-numbered sustain electrode lines S ₁ , S ₃ , and S _2n-1 . However, a connection relationship between the arrangement positions of the first and second sustain signal generation circuits 700a and 700b and the gate lines G ₁ -G _2n and the sustain signal lines S ₁ -S _2n is not limited thereto.

The sustain signal generator 700 is integrated into the liquid crystal panel assembly 300 along with the signal lines G ₁ -G _2n , D ₁ -D _m , S ₁ -S _2n , and the thin film transistor switching element Q. However, the sustain signal generator 700 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or mounted on a flexible printed circuit film (not shown). The tape carrier package may be attached to the liquid crystal panel assembly 300 or mounted on a separate printed circuit board (not shown).

The data driver 500 is connected to the data lines D ₁ -D _m of the liquid crystal panel assembly 300, and selects a gray voltage from the gray voltage generator 800 and uses the data line D as the data voltage. ₁ -D _m ). However, when the gray voltage generator 800 does not provide all the gray voltages but provides only a limited number of reference gray voltages, the data driver 500 divides the reference gray voltages to generate a desired data voltage.

The signal controller 600 controls the gate driver 400, the data driver 500, the sustain signal generator 700, and the like.

Each of the driving devices 500, 600, and 800 may be mounted directly on the liquid crystal panel assembly 300 in the form of at least one integrated circuit chip, or mounted on a flexible printed circuit film (not shown). And attached to the liquid crystal panel assembly 300 in the form of a tape carrier package (TCP) or mounted on a separate printed circuit board (not shown). Alternatively, the driving apparatuses 500, 600, and 800 may include the liquid crystal panel assembly 300 together with the signal lines G ₁ -G _2n , D ₁ -D _m , S ₁ -S _2n , and the thin film transistor switching element Q. ) May be integrated. In addition, the driving apparatuses 500, 600, and 800 may be integrated into a single chip, in which case at least one of them or at least one circuit element constituting them may be outside the single chip.

Next, the operation of the liquid crystal display will be described in detail.

The signal controller 600 receives input image signals R, G, and B and an input control signal for controlling the display thereof from an external graphic controller (not shown). The input image signals R, G, and B contain luminance information of each pixel PX, and the luminance is a predetermined number, for example, 1024 (= 2 ¹⁰ ), 256 (= 2 ⁸ ), or 64 (= 2 ⁶ ) It has gray. Examples of the input control signal include a vertical sync signal Vsync, a horizontal sync signal Hsync, a main clock signal MCLK, and a data enable signal DE.

The signal controller 600 properly processes the input image signals R, G, and B according to operating conditions of the liquid crystal panel assembly 300 based on the input image signals R, G, and B and the input control signal, and controls the gate. After generating the signal CONT1, the data control signal CONT2, the sustain control signal CONT3, and the like, the gate control signal CONT1 is sent to the gate driver 400, and the data control signal CONT2 and the processed image signal ( The DAT is sent to the data driver 500, and the maintenance control signal CONT3 is sent to the maintenance signal generator 700.

The gate control signal CONT1 includes scan start signals STV1 and STV2 that indicate scan start and at least one clock signal that controls the output period of the gate-on voltage Von. In this case, the scan start signal STV1 may be applied to the first gate driving circuit 400a and the scan start signal STV2 may be applied to the second gate driving circuit 400b. The gate control signal CONT1 may also further include an output enable signal OE that defines the duration of the gate-on voltage Von.

The data control signal CONT2 applies analog data voltages to the horizontal synchronization start signal STH and the data lines D ₁ -D _m indicating the start of the transmission of the digital image signal DAT for one row of pixels PX. It includes a load signal LOAD and a data clock signal HCLK to be applied. The data control signal CONT2 also inverts the signal RVS which inverts the polarity of the data voltage with respect to the common voltage Vcom (hereinafter referred to as "polarity of the data voltage" by reducing the "polarity of the data voltage with respect to the common voltage"). It may further include.

According to the data control signal CONT2 from the signal controller 600, the data driver 500 receives the digital image signal DAT for the pixel PX in one row, for example, the i-th row, and receives each digital signal. The digital image signal DAT is converted into an analog data voltage by selecting a gray voltage corresponding to the image signal DAT, and then applied to the data lines D ₁ -D _m .

The gate driver 400 is a gate signal applied to one of the general gate lines G ₁ -G _2n , for example, the i-th gate line G _i , according to the gate control signal CONT1 from the signal controller 600. Is switched to the gate-on voltage Von to turn on the switching element Q connected to the gate line G _i . Then, the data voltage applied to the data lines D ₁ -D _m is applied to the pixels PX in the i th row through the turned-on switching element Q, and thus the liquid crystal capacitor Clc in the pixels PX The holding capacitor Cst is charged.

The charging voltage of the liquid crystal capacitor Clc, that is, the pixel voltage is almost equal to the difference between the data voltage applied to the pixel PX and the common voltage Vcom. The arrangement of the liquid crystal molecules varies depending on the magnitude of the pixel voltage, thereby changing the polarization of light passing through the liquid crystal layer 3. This change in polarization is represented by a change in the transmittance of light by the polarizer, through which the pixel PX displays the luminance represented by the gray level of the image signal DAT.

After one horizontal period (also referred to as "1H" and equal to one period of the horizontal sync signal Hsync and the data enable signal DE), the data driver 500 causes the pixel of the (i + 1) th row ( When the data voltage for PX is applied to the data lines D ₁ -D _m , the gate driver 400 changes the gate signal applied to the i-th gate line G _i to the gate-off voltage Voff and then. The gate signal applied to the gate line G _{i + 1} is changed to the gate-on voltage Von.

As a result, the switching element Q of the i-th pixel row is turned off, thereby causing the pixel electrode 191 to be in a floating state.

The sustain signal generator 700 may partially retain the electrode lines S ₁ -S _2n in response to a voltage rise between the sustain control signal CONT3 and the gate signals applied to the gate lines G ₁ -G _2n from the signal controller 600. Change the voltage level of the sustain signal applied to Then, the pixel electrode 191, which is one terminal of the storage capacitor Cst of the pixel row in which the voltage level of the sustain signal is changed, changes its voltage according to the voltage change of the corresponding storage electrode lines S ₁ -S _2n that are the other terminals. Change.

By repeating this process for every pixel row, the liquid crystal display displays an image of one frame.

When one frame ends, the next frame starts and the state of the inversion signal RVS applied to the data driver 500 is controlled so that the polarity of the data voltage applied to each pixel PX is opposite to the polarity of the previous frame. (“Invert frame”). In addition, the polarities of the data voltages applied to the pixels PX of one row are all the same, and the polarities of the data voltages applied to the pixels PX of two adjacent rows are opposite (“row inversion”).

As described above, since the liquid crystal display according to the present exemplary embodiment performs frame inversion and row inversion, the data voltages applied to the pixels PX of any one row are either positive or negative, and the polarity is changed in units of frames. In this case, the sustain signal generator 700 changes the sustain signal applied to the odd-numbered or even-numbered pixel rows in which the negative data voltage is charged in the pixel electrode 191 from the high level voltage to the low level voltage. Therefore, the voltage of the pixel electrode 191 is further lowered, and the voltage range of the pixel electrode 191 is wider than the range of the gray scale voltage which is the basis of the data voltage, and thus a wide range of luminance can be realized even with a low basic voltage. In contrast, the sustain signal generator 700 may change the sustain signal applied to the odd-numbered or even-numbered pixel rows in which the positive data voltage is charged in the pixel electrode 191 from the low level voltage to the high level voltage. In this case, the voltage of the pixel electrode 191 rises further.

Meanwhile, the first and second sustain signal generating circuits 700a and 700b may include a plurality of signal generating circuits 710 respectively connected to the sustain electrode lines S ₁ -S _2n , respectively. An example of the signal generation circuit 710 will be described in detail with reference to FIGS. 3 to 5B.

3 is a circuit diagram of a signal generation circuit according to an embodiment of the present invention, and FIG. 4 is a layout view illustrating input and output relationships between the signal generation circuit, the gate signal, and the sustain signal according to an embodiment of the present invention. FIG. 5A is a timing diagram of a signal used in the liquid crystal display including the signal generation circuit shown in FIG. 3 in the odd-numbered frame, and FIG. 5B is a signal generation circuit shown in FIG. 3 in the even-numbered frame. A timing diagram of a signal used in a liquid crystal display device including a.

As shown in FIG. 3, the signal generation circuit 710 has two input terminals IP11 and IP12, an enable terminal IP13, a disable terminal IP14, and one output terminal OP.

If the i-th signal generating circuit of the liquid crystal panel assembly 300, the first sustain signal generating circuit (700a) is disposed on one side, e.g., left, and connected to the i-th sustain signal (S _i) of the first input stage (IP11 ) Is connected to the (i + 1) th gate line G _{i + 1 and} receives the (i + 1) th gate signal g _{i + 1} as an input signal, and the second input terminal IP12 is connected to (i-1 ) Is connected to the (i-1) th gate line (G _i-1 ) and receives the (i-1) th gate signal (g _i-1 ) as an input signal, and the output terminal (OP) is connected to the i-th sustain electrode line (S _i ). The second sustain signal Vs _i is output. As described above, these gate signals g _i-1 and g _{i + 1} are all disposed in the same direction as the first sustain signal generating circuit 700a, for example, the first gate driving circuit 400a. Is output from Similarly, the (i +) of the second sustain signal generation circuit 700b disposed on the other side of the liquid crystal panel assembly 300, for example, on the right side and connected to the (i + 1) th sustain signal line Si _{i + 1} . 1) In the case of the first signal generation circuit, the first input terminal IP11 is connected to the (i + 2) th gate line G _{i + 2} to receive the (i + 2) th gate signal g _{i + 2} . The second input terminal IP12 is connected to the i-th gate line G _i to receive the i-th gate signal g _i as an input signal, and the output terminal OP is the (i + 1) th storage electrode line S. _{i + 1} ) to output the (i + 1) th holding signal Vs _{i + 1} . These gate signals g _i and g _{i + 2} are also output from the gate driving circuit, for example, the second gate driving circuit 400b, disposed in the same direction as the second sustain signal generating circuit 700b.

The signal generation circuit 710 is a kind of the maintenance control signal CONT3 from the signal controller 600 and has first to third clock signals having high level voltages Vh1, Vh2 and Vh3 and low level voltages V1, Vll2 and Vl3. The signal CK1, CK1B, CK2, the enable signal VBE_L or VBE_R, and the disable signal VBD_L or VBD_R are input, and a high voltage AVDD and a low voltage AVSS are received from the signal controller 600 or the outside. In this case, the signals VBE_L and VBD_L of the enable and disable signals VBE_L or VBE_R, and VBD_L or VBD_R are generated by the first sustain signal generation circuit 700a disposed on the left side of the liquid crystal panel assembly 300. Received through the enable and disable terminals IP13 and IP14 of the circuit, respectively, and the remaining signals VBE_R and VBD_R are signals of the second sustain signal generation circuit 700b disposed on the right side of the liquid crystal panel assembly 300. It is input through the enable and disable terminals IP13 and IP14 of the generation circuit, respectively.

As shown in FIGS. 5A and 5B, the pulse widths of the first to third clock signals CK1, CK1B, and CK2 may be about 1H and the duty ratio may be about 50%. The first clock signal CK1 and the second clock signal CK1B are inverted signals having a phase difference of about 180 °, and the phases of the second clock signal CK1B and the third clock signal CK2 are the same. . In addition, the waveforms of the first to third clock signals CK1, CK1B, and CK2 are inverted in units of frames.

The high level voltage Vh1 of the first and second clock signals CK1 and CK1B may be about 15V, the low level voltage V1 may be about 0V, and the high level voltage Vh2 of the third clock signal CK2 is about 5V. And the low level voltage Vl2 may be about 0V. The high voltage AVDD may be about 5 V equal to the high level voltage Vh2 of the third clock signal CK2 and the low voltage AVSS may be about 0 V equal to the low level voltage V1 of the third clock signal CK2. .

The enable and disable signals (VBE_L or VBE_R, and VBD_L or VBD_R) have an inverse relationship with each other, and these signal states are inverted in units of frames, respectively. In the present embodiment, in the odd frame, the enable signal VBE_L maintains the low level voltage Vl3, the disable signal VBD_L maintains the high level voltage Vh3, and the enable signal VBE_R Maintains high level voltage Vh3 and disable signal VBD_R maintains low level voltage Vl3, and vice versa for even frames, but such enable and disable signals VBE_L or VBE_R, and VBD_L or The relationship between the voltage level of VBD_R) and the frame is not limited to this and can be changed according to the polarity state of the pixel row or the like.

The signal generation circuit 710 includes seven transistors Tr1-Tr7 and two capacitors C1 and C2 each having a control terminal, an input terminal, and an output terminal.

The control terminal of the transistor Tr1 is connected to the output terminals of the transistors Tr7 and Tr8 connected to each other, the input terminal is connected to the third clock signal CK2, and the output terminal is connected to the output terminal OP. It is.

The control terminals of the transistors Tr2 / Tr3 are connected to the output terminals of the transistors Tr7 and Tr8 which are connected to each other, and the input terminals are connected to the first / second clock signals CK1 / CK1B.

The control terminals of the transistors Tr4 / Tr5 are connected to the output terminals of the transistors Tr2 / Tr3, the input terminals are connected to the low voltage (AVSS) / high voltage (AVDD), and the output terminals are connected to the output terminal (OP). It is.

The control terminal of the transistors Tr6 / 'Tr7 is connected to the enable / disable terminal IP13 / IP14, and the input terminal is connected to the input terminal IP11IP12.

The capacitor C1 / C2 is connected between the control terminal of the transistors Tr4 / Tr5 and the low voltage AVSS / high voltage AVDD.

The transistors Tr1-Tr7 may be formed of amorphous silicon or poly crystalline silicon thin film transistors.

The high level voltage Vh3 of the enable and disable signals VBE_L or VBE_R and VBD_L or VBD_R is such that the transistors Tr6 and Tr7 can be turned on, and the low level voltage Vl3 is the transistors Tr6 and Tr7. ) Is a voltage that can turn off.

As described above, each signal generating circuit 710 of the first and second sustain signal generating circuits 700a and 700b is a corresponding signal from the first or second gate driving circuits 400a and 400b respectively disposed in the same direction. The gate signal of the gate line disposed below and adjacent to and below the generation circuit 710 is applied. An example of a connection relationship between the signal generation circuit 710 of the first and second sustain signal generation circuits 700a and 700b and the gate signal is illustrated in FIG. 4.

As shown in FIG. 4, the signal of the last signal generation circuit and the second sustain signal generation circuit 700b connected to the last sustain electrode line S _2n among the signal generation circuits 710 of the first sustain signal generation circuit 700a. The first input terminal IP11 of the first signal generation circuit connected to the first sustain electrode line S ₁ of the generation circuit 710 may have a signal other than the gate signal, for example, the first and second gate driving circuits 400a. The control signals STVL and STVR based on the vertical synchronization start signals STV1 and STV2 applied to the signal 400b may be received, but are not limited thereto.

The operation of such a signal generating circuit will be described in detail.

As shown in FIGS. 5A and 5B, the application time of the gate-on voltage Von applied to two adjacent gate lines overlaps, and at this time, the overlap-time of the gate-on voltage Von may be about 1H. As a result, the pixels PX of all rows are charged for about 1H with the data voltage applied to the pixels PX of the immediately previous row, but are charged with their data voltages for the remaining about 1H, and the image display operation is normally performed. .

First, in the case of the odd-numbered frame, the operation of the signal generation circuit will be described with reference to FIG. 5A. In this embodiment, in the odd-numbered frame, a negative data voltage is applied to the odd-numbered pixel rows, and a positive data voltage is applied to the even-numbered pixel rows.

As shown in FIG. 5A, in the case of an odd frame, the enable signal VBE_L and the disable signal VBD_R have a low level voltage Vl3, and the enable signal VBE_R and the disable signal VBD_L have a high level voltage. (Vh3).

As a result, the transistor Tr6 of the signal generation circuit 710 of the first sustain signal generation circuit 700a disposed on the left side of the liquid crystal panel assembly 300 is turned off, the transistor Tr7 is turned on, and the liquid crystal panel is turned on. The transistor Tr6 of the signal generation circuit 710 of the second sustain signal generation circuit 700b disposed on the right side of the assembly 300 is turned on, and the transistor Tr7 is turned off.

Accordingly, when the odd-numbered frame, the current pixel row, for example, after the i-th pixel row gate signal (g _i) to the application, then the burn-in (i + 1) gate signal (g _{i + 1)} th pixel row When the signal is applied to the input terminal IP11, the signal generation circuit is operated. Therefore, the first sustain signal generation circuit 700a disposed on the left side of the liquid crystal panel assembly 300 is in a disabled state and the liquid crystal panel assembly ( The second holding signal generating circuit 700b disposed on the right side of the 300 is enabled, and the odd holding signal lines S ₁ , S ₃ , and S ₅ connected to the second holding signal generating circuit 700b are enabled. In other words, the sustain signal is changed from the high level voltage to the low level voltage in the pixel row to which the negative data voltage is applied.

The operation of this signal generation circuit will be described in more detail.

In the case of a signal generation circuit connected to an odd-numbered pixel row, for example, the i-th pixel row, a gate signal g _{i + 1} applied to an input signal, that is, the (i + 1) th gate line G _{i + 1} When the gate-on voltage Von is reached, the first to third transistors Tr1-Tr3 are turned on. The turned-on transistor Tr1 transfers the third clock signal CK2 to the output terminal OP so that the voltage level of the sustain signal Vs _i is high by the high level voltage Vh2 of the third clock signal CK2. (V +). Meanwhile, the turned-on transistor Tr2 transfers the first clock signal CK1 to the control terminal of the transistor Tr4, and the turned-on transistor Tr3 transmits the second clock signal CK1B to the control terminal of the transistor Tr5. To pass.

Since the first clock signal CK1 and the second clock signal CK1B are inverted with each other, the transistors Tr4 and Tr5 operate opposite to each other. That is, when the transistor Tr4 is turned on, the transistor Tr5 is turned off. On the contrary, when the transistor Tr4 is turned off, the transistor Tr5 is turned on. When the transistor Tr4 is turned on and the transistor Tr5 is turned off, the low voltage AVSS is transmitted to the output terminal OP. When the transistor Tr4 is turned off and the transistor Tr5 is turned on, the high voltage AVDD is turned on. It is delivered to the output terminal OP.

The gate-on voltage Von state of the gate signal g _{i + 1} is maintained for 2H, for example, the first half 1H is referred to as the first half T1 and the second half 1H is referred to as the second half T2.

Since the first clock signal CK1 is the low level voltage V1 during the first half period T1, and the second and third clock signals CK1B and CK2 are the high level voltages Vh1 and Vh2, the transistor Tr1 transfers them. The output terminal OP, to which the high level voltage Vh2 of the third clock signal CK2 is applied, receives the high voltage AVDD transmitted by the transistor Tr5. Therefore, the sustain signal Vs _i becomes the high level voltage V + having the same magnitude as the high level voltage Vh2 and the high voltage AVDD. Meanwhile, during the first half period T1, the capacitor C2 is charged with a voltage equal to the difference between the high level voltage Vh1 and the high voltage AVDD of the second clock signal CK1B, and the capacitor C1 is charged with the first clock signal. The voltage corresponding to the difference between the low level voltage V1 and the low voltage AVSS of CK1 is charged.

Since the first clock signal CK1 is the high level voltage Vh1 and the second and third clock signals CK1B and CK2 are the low level voltages V1 and Vl2 during the second half period T2, the first clock signal CK1 is opposite to the first half period T1. Transistor Tr4 is turned on and transistor Tr5 is turned off.

As a result, the output terminal OP receives the low level voltage V1 of the third clock signal CK2 transmitted through the turned-on transistor Tr1, and the sustain signal Vs _i is applied at the low level voltage V + to the low level voltage. The low-level voltage V- at the same level as V1 is changed. In addition, a low voltage AVSS having the same level as the low level voltage V− is applied to the output terminal OP through the turned-on transistor Tr4.

On the other hand, the charging voltage of the capacitor C2 discharges until the low level voltage V1 and the high voltage AVDD of the second clock signal CK1B become equal. Since the voltage level of the first clock signal CK1 and the voltage level of the low voltage AVSS are the same during the first half 1H, the capacitor C1 has a charging voltage of zero. However, since the first clock signal CK1 has the high level voltage Vh1 during the second half of 1H, the voltage corresponding to the difference between the high level voltage Vh1 and the low voltage AVSS is charged.

When the second half period T2 ends and the gate signal g _{i + 1} is changed from the gate on voltage Von to the gate off voltage Voff, the transistors Tr1-Tr3 are turned off. Therefore, the output terminal of the transistor Tr1 is in an isolated state, and the electrical connection between the transistor Tr1 and the output terminal OP is in an isolated state, and the output terminals of the transistors Tr2 and Tr3 are in an isolated state. The control terminals of the transistors Tr4 and Tr5 are also in an isolated state.

Since the voltage is not charged in the capacitor C2, the transistor Tr5 remains turned off. However, since the voltage is charged in the capacitor C1 due to the difference between the high level voltage Vh1 and the low voltage AVSS of the first clock signal CK1, when the voltage is greater than or equal to the threshold voltage of the transistor Tr4, the transistor Tr4 is charged. Remains turned on. Accordingly, the low voltage AVSS is transmitted to the output terminal OP and output as the sustain signal Vs _i . Therefore, the sustain signal Vs _i maintains the low level voltage V-.

Next, the operation of the (i + 1) -th signal generation circuit connected to the even-numbered pixel rows will be described.

As described above, the signal generation circuit connected to the even-numbered pixel rows operates according to the gate signal applied through the input terminal IP12 since the transistor Tr6 is turned off and the transistor Tr7 is turned on.

Therefore, when the gate-on voltage Von of the i-th gate signal g _i is applied to the (i + 1) -th signal generation circuit (not shown), the transistors Tr1-Tr3 are turned on, and thus, the first to the first to first transistors are turned on. The state of the sustain signal line VS _{i + 1} output to the output terminal OP varies depending on the voltage levels of the three clock signals CK1, CK1B, CK2. When the gate signal g _i becomes the gate-on voltage Von, the states of the first to third clock signals CK1, CK1B, and CK2 at this time are the (i + 1) th gate signals g _{i + 1} . The state opposite to that at the gate-on voltage Von is reversed.

Therefore, the operation when the first gate-on voltage Von period T1 of the i-th gate signal g _i is performed in the second half-gate-on voltage Von of the (i + 1) th gate signal g _{i + 1} . In the same manner as the operation in the period T2, the low level voltage Vl2 and the low voltage AVSS of the third clock signal CK2 are connected to the output terminal OP by the turn-on operation of the transistors Tr1, Tr2, and Tr4. The sustain signal Vs _{i + 1} becomes the low level voltage V +.

However, the operation in the second half gate-on voltage Von period T2 of the i-th gate signal g _i is performed in the first half gate-on voltage Von period (i + 1) -th gate signal g _{i + 1} . In the same manner as in operation T1, the high level voltage Vl3 and the high voltage AVDD of the third clock signal CK2 are applied to the output terminal OP by the turn-on operation of the transistors Tr1, Tr3, and Tr5. The sustain signal Vs _{i + 1 changes} from the low level voltage V− to the high level voltage V + and maintains the state until the next frame. Therefore, the gate-on voltage Von is applied to the (i + 1) th gate signal g _{i + 1} to complete the charging operation of the data voltage in the (i + 1) th pixel row, and then maintain the (i + 1) th The voltage level of the signal line _{Si + 1} does not change. For this reason, since the voltage change of the pixel electrode 191 of the (i + 1) th pixel row is not performed by the sustain signal VS _{i + 1} , the pixel electrode voltage is not changed.

Due to the voltage change of the sustain signal Vs, the pixel electrode voltage Vp decreases. In the following, capacitors and correction capacities of these capacitors are denoted by the same reference numerals.

That is, the pixel electrode voltage Vp is obtained as shown in Equation 1 below. In Equation 1, V _D is a data voltage, Clc and Cst are capacitances of a liquid crystal capacitor and a storage capacitor, respectively, V + is a high level voltage of the sustain signal Vs, and V- is a low level of the sustain signal Vs. Voltage.

As can be seen from Equation 1, the pixel electrode voltage Vp has a change amount Δ determined by the voltage change of the capacitances Clc and Cst and the sustain signal Vs of the capacitor to the data voltage VD. The value is added or subtracted.

Accordingly, the change amount Δ of the sustain signal Vs is subtracted from the charged data voltage VD to the pixel electrode voltage Vp, and when the charge is performed at the positive data voltage, the change level of the sustain signal does not change. (Δ) becomes " 0 ", so that the pixel electrode voltage Vp does not change, while the sustain signal changes from the high level voltage V + to the low level voltage V− when charged with the negative data voltage. The pixel electrode voltage Vp is decreased by the change amount Δ which is a change of the sustain signal. For this reason, the change in the pixel voltage is wider than the range of the gradation voltage by the reduced pixel electrode voltage Vp, and the luminance range expressed is also widened.

Next, in the even-numbered frame, the operation of the signal generation circuit will be described with reference to FIG. 5B. In the present embodiment, in the even-numbered frame, a positive data voltage is applied to the odd-numbered pixel rows, and a negative data voltage is applied to the even-numbered pixel rows.

In addition, as shown in FIG. 5B, waveforms of the enable signals VBE_L and VBE_R and the disable signals VBD_L and VBD_R applied to the enable terminal IP13 and the disable terminal IP14 are respectively divided into odd-numbered frames. Is reversed. Accordingly, in contrast to the odd-numbered frame, the transistors Tr6 of each signal generator of the liquid crystal panel assembly 300 and the first sustain signal generator 700a disposed on the left side are turned on and the transistors Tr7 are turned off. The transistors Tr6 of each signal generator of the liquid crystal panel assembly 300 and the second sustain signal generator 700b disposed on the right side are turned off and the transistors Tr7 are turned on. Therefore, in the even-numbered frame, the operation of the first sustain signal generator 700a is the same as that of the second sustain signal generator 700b of the odd-numbered frame, and the operation of the second sustain signal generator 700b is Since the operations of the first sustain signal generator 700a of the odd-numbered frame are the same, the operations of the sustain signal generators 700a and 700b are omitted.

By the operation of the first and second sustain signal generators 700a and 700b, the data voltage is charged in the even-numbered pixel rows, as opposed to the odd-numbered frame, and then the first sustain signal generator ( The voltage level of the corresponding sustain signal output from 700a is changed to further reduce the voltage level of the pixel electrode voltage. However, since the voltage level of the corresponding sustain signal output from the second sustain signal generator 700b is not changed, the pixel electrode voltage after the data voltage is charged in the odd pixel rows is not changed.

In this embodiment, only the voltage level of the sustain signal of the pixel row to which the negative data voltage is applied is changed. Alternatively, the voltage level of the sustain signal of the pixel row to which the positive data voltage is applied may be changed. In this case, after the gate-on voltage of the corresponding pixel row is applied and the charging operation to the data voltage is completed, the voltage level of the sustain signal is changed from the low level voltage to the high level voltage. As a result, the pixel electrode voltage increases by the amount of change in the voltage of the sustain signal.

According to this embodiment, since the polarity of the data voltage is inverted not only in the frame but also in the pixel row unit, image quality deterioration due to deterioration of the liquid crystal is reduced.

In addition, since the common voltage is fixed at a constant voltage, power consumption is reduced than when applying a low voltage and a high voltage alternately.

Further, after fixing the common voltage Vcom to a voltage having a predetermined magnitude, the voltage level of the sustain signal applied to the sustain electrode line is changed to increase the range of the pixel electrode voltage, thereby widening the range of the pixel voltage, thereby representing gray scale. Since the range of voltage to be widened, the image quality is improved.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (12)

A plurality of gate lines transferring a gate signal including a gate on voltage and a gate off voltage, A plurality of data lines for transferring data voltages, A plurality of sustain electrode lines for transmitting a sustain signal, A matrix including a switching element connected to the gate line and the data line, a liquid crystal capacitor connected between the switching element and a common voltage, and a storage capacitor connected between the switching element and the storage electrode line, respectively. A plurality of pixels arranged in A plurality of first signal generation circuits disposed in a first direction of the liquid crystal panel assembly and generating the sustain signal based on at least one control signal and at least one gate signal, and applying the sustain signal to a plurality of first sustain electrode lines; and A plurality of electrodes arranged in a second direction opposite to the first direction and generating the sustain signal based on at least one control signal and at least one gate signal to apply the sustain signal to a plurality of second sustain electrode lines; Second signal generation circuit Including The sustain signal applied to each pixel formed in the first or second pixel row is changed in voltage level immediately after charging of the data voltage to the liquid crystal capacitor and the sustain capacitor, Polarities of the data voltages applied to the first pixel row and the second pixel row are opposite to each other. Liquid crystal display. In claim 1, And when the charged data voltage is negative, the sustain signal changes from a high level to a low level. In claim 1, And when the charged data voltage is positive, the sustain signal changes from a low level to a high level. In claim 1, 2. A liquid crystal display device in which polarities of data voltages applied to the same pixel row are inverted for each frame. In claim 4, And a plurality of pixel rows in which the voltage level of the sustain signal is changed in two adjacent frames. In claim 1, The common voltage has a constant value. In claim 1, A first gate driver disposed in the first direction and configured to apply the gate signal to a plurality of first gate lines, and disposed in the second direction and configured to apply the gate signal to a plurality of second gate lines Further comprising a second gate driver, The first signal generation circuit receives a gate signal from the first gate driver, and the second signal generation circuit receives a gate signal from the second gate driver. In claim 1, Each of the first and second signal generation circuits may be A signal input unit to which first and second control signals and first and second gate signals are input; A sustain signal applying unit which is applied with a first clock signal and operates according to a drive control signal from the signal input unit to output the first control signal as a sustain signal; A control unit to which second and third clock signals are applied and operate according to the driving control signal; and A signal holding unit for holding the holding signal output from the holding signal applying unit for a predetermined time according to the operation of the controller. Liquid crystal display comprising a. In claim 8, And a waveform of first and second control signals applied to the first signal generation circuit and the first and second control signals applied to the second signal generation circuit are opposite to each other. In claim 9, The waveforms of the first and second control signals are opposite to each other. In claim 10, The waveform of the first and second control signals are inverted every frame. In claim 8, And a difference between a gate-on voltage application timing of the first gate signal and a gate-on voltage application timing of the second gate signal is about 2H.

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