KR102018114B1 - Display device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device that can convert a gate control signal output from a general gate driver main driver using a GIP method into a signal required by a gate driver using a sharing GIP method. It is technical problem to provide. To this end, the display device according to the present invention comprises: a panel in which pixels are formed in respective regions defined by intersections of gate lines and data lines; A gate driver formed in the panel and connected to at least two gate lines, the gate driver being configured to supply gate signals sequentially to the gate lines; A main driver for outputting a data voltage to the data lines and outputting a gate control signal; And a converter configured to generate panel gate clocks and selection signals, which are gates to be used in the gate driver, using the gate control signal and output the selected gate signals to the gate driver.

Description

Display {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device driven by a gate in panel (GIP) method.

Flat panel displays (FPDs) are used in various types of electronic products, including mobile phones, tablet PCs, and notebook computers. The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), an organic electroluminescent display (OLED), and more recently, an electrophoretic display ( EPD: ELECTROPHORETIC DISPLAY) is also widely used.

Among flat panel display devices (hereinafter, simply referred to as 'display devices'), liquid crystal display devices are most widely commercialized due to the advantages of mass production technology, ease of driving means, and high quality.

Among the display devices, the organic light emitting display device has a high response time with a response speed of 1 ms or less, low power consumption, and self-illumination, so that there is no problem in viewing angle. have.

Fig. 1 is an exemplary view showing the structure of a conventional gate driver. In particular, Fig. 1 is an exemplary view showing the structure of a gate driver using a sharing gate-in panel method. FIG. 2 is an exemplary view showing waveforms of various signals applied to a conventional gate driver, (a) shows waveforms of signals applied to a conventional general gate driver, and (b) shows a sharing gate shown in FIG. The waveforms of signals applied to the in-panel gate driver are shown.

In order to strengthen the design competitiveness of mobile products, the demand for narrow bezel is continuously increasing, and in order to implement such narrow bezel, two gates in one GIP Gate drivers using a sharing gate in panel (GIP) method (hereinafter, simply referred to as 'GIP') that drive more than one gate line have been developed.

The gate driver 10 using the sharing GIP method includes, for example, a plurality of GIPs 11 directly formed on a panel together with other components, as shown in FIG. 1, and the plurality of GIPs. Each of the (11) outputs a scan signal (Gate Out) to the two gate lines.

Therefore, when 1080 gate lines are formed in the panel, the gate driver 10 is composed of 540 GIPs 11.

Meanwhile, the gate driver 10 using the sharing GIP scheme uses signals of a different type from the conventional gate driver using the GIP scheme.

For example, the conventional gate driver using the GIP method uses four gate clocks GCLK1 to GCLK4 that are sequentially output as shown in FIG.

However, the gate driver using the sharing GIP method uses two gate clocks GCLK1 and GCLK2 and two selection signals SEL1 and SEL2 as shown in FIG.

The two gate clocks and the two selection signals applied to the gate driver using the sharing GIP scheme are completely different from the four gate clocks applied to the general gate driver using the GIP scheme.

That is, the gate driver using the sharing GIP method requires the selection signals SEL1 and SEL2 to drive the sharing transistor. In addition, the pulse width of each of the two gate clocks GCL1 and GCL2 is formed to correspond to a horizontal period corresponding to the number of shared gate lines. For example, as shown in FIG. 1, the pulse width of each of the two gate clocks applied to a gate driver in which one GIP is formed to share two gate lines is shown in FIG. 2B. As shown, it has a size corresponding to two horizontal periods.

On the other hand, as described above, since the gate driver using the sharing GIP method uses a different type of gate clocks and selection signals than the gate clocks applied to the general gate driver using the GIP method, the gate using the sharing GIP method is used. In order to use the driver, a new type of main driver that can output gate clocks and selection signals of the type described above has to be developed.

For this reason, the development period of the display device is delayed, and the manufacturing cost of the display device is also rising.

The present invention has been proposed to solve the above-described problems, which can be used by converting a gate control signal output from a general gate driver main driver using a GIP method into a signal required by a gate driver using a sharing GIP method. It is a technical problem to provide a display device.

According to an aspect of the present invention, there is provided a display device including: a panel in which pixels are formed in respective regions defined by intersections of gate lines and data lines; A gate driver formed in the panel and connected to at least two gate lines, the gate driver being configured to supply gate signals sequentially to the gate lines; A main driver for outputting a data voltage to the data lines and outputting a gate control signal; And a converter configured to generate panel gate clocks and selection signals, which are gates to be used in the gate driver, using the gate control signal and output the selected gate signals to the gate driver.

According to the present invention, since a new main driver does not need to be developed for the gate driver using the sharing GIP method, the cost can be reduced and the development period of the display device can be shortened.

In addition, according to the present invention, since a conversion unit for converting clock signals output from a general gate driver main driver using a GIP method into signals required by a gate driver using a sharing GIP method can be formed in the panel, No additional cost is required.

1 is an exemplary view showing a configuration of a conventional gate driver.
2 is an exemplary view showing waveforms of various signals applied to a conventional gate driver.
3 schematically illustrates a display device according to the present invention;
4 is an exemplary view illustrating a configuration of a main driver, a converter, and a gate driver applied to the display device according to the present invention.
5 is an exemplary view showing various waveforms applied to the display device according to the present invention.
6 is an exemplary view illustrating a configuration of a gate-in panel applied to a display device according to the present invention and waveforms of scan signals output from the gate-in panel.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention. The present invention can be applied to both a liquid crystal display device and a display device such as an organic light emitting diode. In the following, for convenience of explanation, the present invention will be described with an example of a liquid crystal display device.

3 is a view schematically showing a display device according to the present invention, FIG. 4 is an exemplary view showing the configuration of a main driver, a converter and a gate driver applied to the display device according to the present invention, and FIG. An exemplary view showing various waveforms applied to the display device according to the embodiment.

In the liquid crystal display according to the present invention, as shown in FIG. 3, a panel 100 in which pixels are formed in each region defined by the intersection of the gate lines GL1 to GLg and the data lines DL1 to DLd. And gate in panel (GIP) 210 formed on the panel 100 and connected to at least two gate lines to sequentially supply scan signals to the gate lines. A gate-in panel to be used in the gate driver 200 by using a gate driver 200 for outputting a data voltage to the data lines, a main driver 500 for outputting a gate control signal, and the gate control signal. The converter 600 generates gate clocks and selection signals and outputs the generated gate clocks to the gate driver 200.

First, the panel 100 includes pixels formed in regions defined by intersections of the gate lines GL1 to GLg and the data lines DL1 to DLd formed in the display area 110, and each of the pixels A thin film transistor TFT and a pixel electrode are formed thereon.

The thin film transistor TFT supplies a data voltage supplied from the data line to the pixel electrode in response to a scan signal supplied from the gate line. The transmittance of light is controlled by driving the liquid crystal positioned between the pixel electrode and the common electrode in response to the data voltage.

As for the liquid crystal mode of the panel applied to this invention, not only TN mode, VA mode, IPS mode, FFS mode but any kind of liquid crystal mode is possible. In addition, the liquid crystal display according to the present invention may be implemented in any form, such as a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display.

Next, the main driver 500 outputs a data voltage to the data lines and outputs a gate control signal. The main driver 500 is formed of an integrated circuit and is formed in the non-display area of the liquid crystal panel 100. Can be mounted.

The main driver 500 may include a function of a data driver for outputting the data voltage, a data control signal for controlling the data driver, and a timing controller for outputting the gate control signal.

The data driver converts the digital image data transmitted from the timing controller into a data voltage and supplies the data lines for one horizontal line to the data lines every horizontal period during which a scan signal is supplied to the gate line.

The data driver converts the image data into the data voltage using the gamma voltages supplied from a gamma voltage generator (not shown) and outputs the converted data to the data line. To this end, the data driver includes a shift register unit, a latch unit, a digital-to-analog converter (DAC), and an output buffer.

The shift register unit outputs a sampling signal using data control signals SSC and SSP received from the timing controller.

The latch unit latches the digital image data Data sequentially received from the timing controller, and simultaneously outputs the digital image data to the digital analog converter DAC.

The digital-to-analog converter converts the image data transmitted from the latch unit into a positive or negative data voltage at the same time and outputs the data voltage. That is, the digital-to-analog converter determines the image data according to the polarity control signal POL transmitted from the timing controller 400 by using the gamma voltage supplied from the gamma voltage generator (not shown). The data voltage is converted into a polarity or a negative data voltage and output to the data lines. In this case, the gamma voltage generation unit converts the image data into the data voltage using the input voltage Vdd.

The output buffer transmits the data voltage DL of the panel according to the source output enable signal SOE transmitted from the timing controller 400 to the positive or negative data voltage transmitted from the digital analog converter. Output to

The timing controller uses an timing signal input from an external system, that is, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and the like to operate the timing of the gate driver 200. The gate control signal GCS for controlling the data and the data control signal DCS for controlling the operation timing of the data driver 300 are generated, and the image data to be transmitted to the data driver 300 is generated.

To this end, the timing controller, a receiving unit for receiving input image data and timing signals from the external system, a control signal generator for generating various control signals, rearranged by rearranging the input image data, And a data alignment unit for outputting image data, and an output unit for outputting the control signals and the image data.

That is, the timing controller rearranges input image data input from the external system according to the structure and characteristics of the panel 100 and transmits the rearranged image data to the data driver 300. . This function may be executed in the data alignment unit.

The timing controller uses timing signals transmitted from the external system, that is, data for controlling the data driver by using a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. A control signal DCS and a gate control signal GCS for controlling the gate driver are generated to transmit the control signals to the data driver and the gate driver. Such a function may be executed in the control signal generator.

The data control signals generated by the control signal generator include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, a polarity control signal POL, and the like.

The gate control signals GCS generated by the control signal generator include a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a gate start signal VST, and a gate clock GCLK. Etc.

In particular, as shown in FIG. 4, the gate clocks GCLK generated by the control signal generator include the gate-in panel gate clocks GCLK A and GCLK B and the selection signals SEL1, which are gated by the converter 600. SEL2). The gate-in panel gate clocks GCLK A and GCLK B and the selection signals SEL1 and SEL2 converted by the conversion unit 600 are input to respective gate-in panel GIPs forming the gate driver 200. And used to generate a scan signal.

Gate clocks GCLK generated by the control signal generator are sequentially output as shown in FIG. 5. In addition, the pulse width of the gate clock corresponds to one horizontal period, which is a period during which the data voltage is output to the data line.

When the gate-in panel GIP forming the gate driver 200 is connected to two gate lines and configured to sequentially output scan signals to the two gate lines, the gate clock GCKL. The number of fields may be four.

However, the number of the gate clocks is not limited to four. That is, the number of gate clocks may be variously set by the structure of the gate-in panel (GIP) 210 and the number of gate lines connected to the gate-in panel 210. Hereinafter, for convenience of description, the present invention will be described with an example in which the main driver 500 outputs four gate clocks GCKL.

Meanwhile, in the main driver 500 as described above, the main driver 500 used for the general gate driver using the conventional gate-in-panel (GIP) method may be used as it is.

That is, the gate-in panel (GIP) 210 applied to the present invention is a sharing gate-in panel connected to at least two gate lines, and outputs at least two scan signals. Different signals are used in the panel.

Therefore, in order to drive the gate-in panel (GIP) 210 applied to the present invention, a main driver of a type different from the main driver used in the related art should be used.

However, the present invention is characterized in that the main driver used for the general gate driver using the gate-in panel method is used as it is. Accordingly, the gate clocks GCLK among the gate control signals output from the main driver 500 are the same signals as the gate clocks output from the main driver used for the general gate driver.

Next, the gate driver 200 uses the gate control signals transmitted from the main driver 500 and the gate-in panel gate clocks and the selection signals transmitted through the converter, and the gate lines GL1 through. GLg) sequentially supplies gate-on signals to each.

The gate-on signal refers to a voltage capable of turning on the switching thin film transistors connected to the gate lines. The voltage capable of turning off the switching thin film transistor is called a gate-off signal, and the gate-on signal and the gate-off signal are collectively called a scan signal.

When the thin film transistor is N type, the gate on signal is a high level voltage, and the gate off signal is a low level voltage. When the thin film transistor is a P type, the gate on signal is a low level voltage, and the gate off signal is a high level voltage.

The gate driver 200 includes gate in panel (GIP) 210 mounted in the panel 100.

Each of the gate-in panel (GIP) 210 sequentially outputs the scan signal to at least two gate lines by using the gate-in panel gate clocks and the selection signals.

In addition, the gate-in panel GIPs sequentially output scan signals to gate lines formed in the panel.

As described above, the gate driver 200 including the gate in panel 210 connected to at least two gate lines is referred to as a gate driver using a sharing gate in panel method.

In order to drive the gate-in panel 210, at least two gate-in panel gate clocks GCLK and at least two selection signals are required.

The pulse width of the gate-in panel gate clocks corresponds to horizontal periods corresponding to the number of gate lines connected to the gate-in panel, and the pulse width of the selection signals corresponds to one horizontal period.

Finally, the converter 600 generates the gate-in panel gate clocks and select signals to be used in the gate driver 200 by using the gate clock among the gate control signals, and the gate driver 200. )

To this end, the converter 600 may be formed of a plurality of OR gates.

As illustrated in FIG. 3, the converter 600 may be formed in a non-display area of the panel 100. However, the converter 600 may be formed inside the main driver 500. In the latter case, the configuration of the main driver 500 is not exactly the same as the configuration of the main driver conventionally used for the gate-in panel. However, by adding only the conversion unit 600 to the conventional main driver, a new type of main driver can be easily manufactured.

Hereinafter, as an example, the gate-in panel 210 is connected to two gate lines to sequentially supply scan signals to the two gate lines, and the conversion unit 600 and the gate in The configuration of the panel 210 is described. That is, the gate-in-panel (GIP) 210 applied to the sharing gate-in-panel gate driver 200 is connected to at least two or more gate lines and sequentially scans the two or more gate lines. For the sake of convenience, the present invention will be described with reference to the panel 210 which is a gate in which two gate lines are connected.

In this case, the main driver 500 sequentially outputs the first gate clock GCLK1, the second gate clock GCLK2, the third gate clock GCLK3, and the fourth gate clock GCLK4.

The conversion unit 600 uses the four gate clocks GCLK1, GCKL2, GCKL3, and GCKL4 input from the main driver 500 as the gate control signal to control two gate-in panel gate clocks ( GCLK A and GCKL B and two selection signals SEL1 and SEL2 are generated and supplied to each gate-in panel GIP 210.

To this end, as illustrated in FIG. 4, the converter 600 may be supplied to the gate driver 200 by using the first gate clock GCLK1 and the second gate clock GCLK2. By using the first logical sum gate ORG1, the third gate clock GCLK3 and the fourth gate clock GCLK4 for generating a one-gate panel panel clock GCLK A, the gate driver 200 is connected to the gate driver 200. The gate driver may be formed using the second logic gate ORG2 for generating the panel gate clock GCKL B, which is to be supplied, and the first gate clock GCLK1 and the third gate clock GCLK3. The gate driver 200 using the third logical sum gate ORG3, the second gate clock GCLK2, and the fourth gate clock GCKL4 for generating the first selection signal SEL1 to be supplied to the 200. A fourth logical sum gate ORG4 for generating the second selection signal SEL2 to be supplied to the.

Each of the logic sum gates ORG outputs 1 when any one of two input signals is 1, and outputs 0 when all input signals are 0.

Accordingly, in FIG. 5, the first logic gate ORG1 receiving the first gate clock GCL1 and the second gate clock GCLK2 is a panel gate clock that is a first gate of a high signal for two horizontal periods. Outputs (GCLK A).

In addition, the second logic gate ORG2 receiving the third gate clock GCLK3 and the fourth gate clock GCLK4 may have the gate clock GCLK A, which is the first gate, converted into a low signal. In this case, the panel gate clock GCLK B, which is the second gate of the high signal, is output for two horizontal periods.

In addition, the third logic gate ORG3 that receives the first gate clock GCLK1 and the third gate clock GCLK3 has a high signal when the first gate clock and the third gate clock are high signals. The first selection signal SEL1 is output.

The fourth logic gate ORG4, which receives the second gate clock GCLK2 and the fourth gate clock GCKL4, has a high signal when the second gate clock and the fourth gate clock are high signals. The second select signal SEL2 is output.

In this case, the pulse widths of the first gate in panel gate clock GCLK A and the second gate in panel gate clock GCLK B correspond to two horizontal periods, and the first selection signal SEL1 and the first gate signal GCLK A correspond to two horizontal periods. The pulse width of the second selection signal SEL2 corresponds to one horizontal period.

That is, as shown in FIG. 5, the first to fourth gate clocks GCLK1 to GCLK4 are sequentially output with a pulse width corresponding to one horizontal period, and the panel gate clock as the first gate. GCLK A and the panel gate clock GCLK B, which is the second gate, have a pulse width corresponding to two horizontal periods, and the first selection signal SEL1 and the second selection signal SEL2 are one horizontal. It has a pulse width corresponding to the period.

Here, the first gate in panel gate clock GCLK A and the second gate in panel gate clock GCLK B have opposite phases, and the first selection signal SEL1 and the second selection signal are opposite to each other. (SEL2) also has opposite phases.

6 is an exemplary view illustrating a configuration of a gate-in panel applied to a display device according to the present invention and a waveform of a scan signal output from the gate-in panel.

As described above, among the gate control signals output from the general gate driver main driver 500 using the gate-in panel method, the gate clocks are required in the gate driver using the sharing GIP method. And GCLK A and GCLK B and the selection signals SEL1 and SEL2, and the conversion is performed in the conversion unit 600.

On the other hand, the gate-in panel (GIP) 210 is connected to at least two or more gate lines to sequentially output the scan signal to the two or more gate lines, as shown in Figure 6, It may be configured to be connected to two gate lines.

In addition, the configuration of the gate-in-panel (GIP) 210 connected to the two gate lines is not limited to that shown in FIG. 6, but for convenience of description, the gate-in-panel panel illustrated in FIG. The present invention is described by taking GIP) 210 as an example.

First, as described above, when the main driver 500 outputs four gate clocks GCLK1 to GCLK4, the conversion unit 600 uses the four gate clocks to open two gate-in panel gate clocks. (GCLK A, GCLK B) and two selection signals (SEL1, SEL2) are output.

Next, as shown in (a) of FIG. 6, the gate-in panel (GIP) 210, as shown in (b) of FIG. 6, a high level first gate-in panel gate clock (GCLKA). ) And the first selection signal SEL1 are output to the first gate line.

That is, when the first transistor T1 is turned on by the start signal Prev, the high potential driving voltage VDD is applied to the gate of the second transistor TSG_E, and the second transistor TSG_E is turned on.

When the second transistor TSG_E is turned on, the first select signal SEL1 of the high level becomes the first scan signal Vout1 and is output to the first gate line.

In this case, since the panel gate clock GCLK B, which is the second gate, is at the low level, the third transistor T3N is turned off.

Finally, when the panel gate clock GLCK B and the second selection signal SEL2 that are the second gates of the high level are input, the second scan signal Vout2 is output to the second gate line.

That is, when the first transistor T1 is turned on by the start signal Prev, the high potential driving voltage VDD is applied to the gate of the fourth transistor TSG_O, and the fourth transistor TSG_O is turned on.

When the fourth transistor TSG_O is turned on, the second selection signal SEL2 of the high level becomes the second scan signal Vout2 and is output to the second gate line.

In this case, since the first selection signal SEL1 is switched to the low level, a gate low voltage is output to the first gate line.

The configuration and operation method of the gate-in panel (GIP) 210 applied to the present invention is not limited to the configuration shown in FIG. have.

Briefly summarized the present invention as described above is as follows.

The present invention relates to a display device using a gate driver 200 driven by a sharing gate in panel (GIP) method.

The present invention is characterized by generating a gate-in panel gate clock and a selection signal required by a sharing gate-in panel (GIP) using a main driver applied to a conventional display device using a gate-in panel (GIP). .

That is, the present invention combines the gate clocks output through the conventional main driver 500, the gate-in panel gate clocks (GCLK A, GCLK B) that can drive the sharing gate in panel (GIP) 210 and The selection signals SEL1 and SEL2 are generated.

According to the present invention as described above, the configuration applied to the conventional display device is not changed at all, only the conversion unit 600 is formed on the panel 100, the display device using a sharing gate-in panel (GIP) method Can be developed, so no cost increase occurs.

In particular, in order to drive the sharing gate-in-panel (GIP) 210, it is not necessary to develop a separate main driver, thereby reducing development costs according to the development of a new main driver.

Those skilled in the art to which the present invention pertains will understand that the present invention can be implemented in other specific forms without changing the technical spirit or essential features. Therefore, it is to be understood that the embodiments described above are exemplary in all respects and not restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be construed as being included in the scope of the present invention. do.

100: panel 200: gate driver
500: main driver 600: converter
210: gate in panel (GIP)

Claims (10)

A panel in which pixels are formed in each region defined by the intersection of the gate lines and the data lines;
A gate driver including a plurality of gate-in-panels (GIPs) connected to at least two gate lines of the gate lines;
A main driver for supplying a data voltage to the data lines and outputting a gate control signal; And
A converting unit configured to generate gate-in-panel gate clocks and selection signals using the gate control signal and to supply the gate driver to the gate driver,
Each of the plurality of gate-in panel (GIP) sequentially supplies at least two or more scan signals to the at least two gate lines based on the gate-in panel gate clocks and the selection signals. The method of claim 1,
And the gate control signal is a plurality of gate clocks. delete The method of claim 1,
The pulse width of the gate-in panel gate clocks corresponds to horizontal periods corresponding to the number of gate lines connected to the gate-in panel. The method of claim 1,
And a pulse width of the selection signals corresponds to one horizontal period. The method of claim 1,
And the conversion unit includes a plurality of OR gates. The method of claim 1,
And the converting unit generates two gate-in panel gate clocks and two selection signals using four gate clocks input to the gate control signal, and supplies the gate-in panel to the gate-in panel. The method of claim 1,
The main driver sequentially outputs a first gate clock, a second gate clock, a third gate clock, and a fourth gate clock.
The conversion unit,
A first logic gate for generating a panel gate clock which is a first gate to be supplied to the gate driver by using the first gate clock and the second gate clock;
A second logic gate for generating a panel gate clock which is a second gate to be supplied to the gate driver using the third gate clock and the fourth gate clock;
A third logical sum gate for generating a first selection signal to be supplied to the gate driver using the first gate clock and the third gate clock; And
And a fourth logical sum gate for generating a second selection signal to be supplied to the gate driver by using the second gate clock and the fourth gate clock. The method of claim 8,
Each gate-in panel formed in the gate driver sequentially outputs a scan signal to two gate lines. The method of claim 9,
The pulse widths of the first gate-in panel gate clock and the second gate-in panel gate clock correspond to two horizontal periods.
And a pulse width of the first selection signal and the second selection signal corresponds to one horizontal period.

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