KR101946350B1 - Liquid crystal panel, liquid crystal display device using the same and driving method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal display device that drives a liquid crystal using two data voltages supplied to two data lines formed in one pixel and two gate-on voltages supplied to two gate lines A liquid crystal panel using the same, and a driving method thereof. To this end, the liquid crystal panel according to the present invention includes: a common electrode to which a common voltage is supplied; An auxiliary pixel electrode formed on the top of the common electrode with a first insulator interposed therebetween; And a pixel electrode formed on the upper side of the auxiliary pixel electrode via a second insulator and including a pixel electrode for driving the liquid crystal together with the common electrode using a data voltage supplied through the data line, And the data lines are formed at intersecting regions of the data lines.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal panel, a liquid crystal display using the liquid crystal panel, and a driving method thereof. BACKGROUND OF THE INVENTION 1. Field of the Invention [0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display, and more particularly, to a liquid crystal panel capable of high voltage driving, a liquid crystal display using the same, and a driving method thereof.

Flat panel displays (FPDs) are used in various types of electronic products including mobile phones, tablet PCs, and notebook computers. The flat panel display includes a liquid crystal display (LCD), a plasma display panel (PDP), and an organic electroluminescence display (OLED). Recently, an electrophoretic display device EPD: ELECTROPHORETIC DISPLAY) is also widely used.

Among the flat panel display devices, liquid crystal display devices are most widely commercialized at present because of advantages of mass production technology, ease of driving means, and realization of high image quality.

The liquid crystal display device drives the liquid crystal panel by various inversion methods in order to prevent the deterioration of the liquid crystal and to improve the display quality. Inversion methods include a frame inversion system, a line inversion system, a column inversion system, a dot inversion system, or a Z-inversion system Z-Inversion System) method.

FIG. 1 is an exemplary view showing a panel configuration of a conventional liquid crystal display device, and FIG. 2 is an exemplary view showing an equivalent circuit of one pixel of a conventional liquid crystal display device.

1, a conventional liquid crystal display device uses a single data line and a single thin film transistor (TFT) to charge a data voltage Vd to one pixel.

When the data voltage Vd for driving the pixel is supplied through the data line, the gate-on voltage Vg is supplied to the corresponding pixel through the gate line, as shown in FIGS. 1 and 2, The thin film transistor is operated. As a result, a voltage is charged in the storage capacitor Cst and the liquid crystal capacitor Clc in the pixel, and the light transmittance of the liquid crystal is changed, thereby outputting the image.

FIG. 1 shows a structure of a panel driven according to a currently used Z-inv. Method or a column inv. Method. As described above, various inversion methods can be applied to a liquid crystal display device, but in order to reduce power consumption, a Z-inversion method or a column inversion method is widely used rather than a dot inversion method.

3 is a diagram illustrating waveforms applied to a conventional liquid crystal display device. In the case where a symmetrical data voltage is applied to the panel based on the common voltage Vcom in the Z-inversion method or the column inversion method or the like And various waveforms are generated. Particularly, FIGS. 3 (d) and 3 (e) show waveforms of the pixel voltages Vp1 and Vp2, taking into consideration that a voltage drop of 1 V occurs when the gate of the thin film transistor is driven.

3 (a) and 3 (b) show waveforms of data voltages supplied to the data lines. When the common voltage VC is 7V, the 16V positive data voltage Vd1 + and the 0V negative data voltage Vd2- are used in consideration of the voltage drop.

Next, FIG. 3C shows the waveform of the gate voltage (scan signal) supplied to the gate line. The gate voltage can be configured with a gate-on voltage of about 26V and a gate-off voltage of -5V.

Next, data voltages (Vd1 +, Vd2-) and a common voltage as described above are applied to the data voltage Vd and the common voltage VC between the data voltage Vd and the common voltage VC, as shown in FIGS. 3 (d) A voltage difference (liquid crystal driving voltage) is generated. On the other hand, in the liquid crystal display device, since the data voltages symmetric with respect to the common voltage VC are used as described above, the data driver must be driven at 16V.

On the other hand, in recent years, since the liquid crystal display device is becoming larger in size, the necessity for high voltage driving is increasing.

However, since the currently used data driver has been developed in consideration of a liquid crystal display device driven by 16V as described above, a data driver driven at a high voltage must be newly developed for a liquid crystal display device driven at a high voltage .

That is, as the liquid crystal display device becomes larger and higher definition, the data voltage Vd for driving the liquid crystal is rising, and accordingly, a data driver driven at a higher voltage is required. However, since there is a limit to the data voltage that the conventional data driver can output, a new high voltage data driver must be developed every time the data voltage is increased. Therefore, the manufacturing cost of the liquid crystal display device is inevitably increased as a whole, and the data drivers used in the past must be discarded without being used.

Disclosure of the Invention The present invention has been proposed in order to solve the above-described problems, and it is an object of the present invention to provide a liquid crystal display device using two data voltages supplied to two data lines formed in one pixel and two gate- A liquid crystal panel using the same, and a driving method thereof.

According to an aspect of the present invention, there is provided a liquid crystal panel including: a common electrode to which a common voltage is supplied; An auxiliary pixel electrode formed on the top of the common electrode with a first insulator interposed therebetween; And a pixel electrode formed on the upper side of the auxiliary pixel electrode via a second insulator and including a pixel electrode for driving the liquid crystal together with the common electrode using a data voltage supplied through the data line, And the data lines are formed at intersecting regions of the data lines.

According to an aspect of the present invention, there is provided a liquid crystal display device including a common electrode to which a common voltage is supplied, an auxiliary pixel electrode formed on an upper end of the common electrode through a first insulator, And a pixel electrode formed on the upper side of the auxiliary pixel electrode and including a pixel electrode for driving the liquid crystal together with the common electrode using the data voltage supplied through the data line is connected to the two gate lines and the two data lines A liquid crystal panel formed for each crossing region; A data driver for outputting data voltages to the data lines; And a gate driver for sequentially outputting a gate-on voltage to the gate lines.

According to an exemplary embodiment of the present invention, there is provided a method of driving a liquid crystal display device including forming a first data line and a pixel electrode between a first data line and a pixel electrode in a first driving period of one horizontal period, Applying a gate-on voltage to a second transistor formed between a second data line and an auxiliary pixel electrode of the two data lines; And applying a gate-on voltage to a third transistor formed between the first data line and the auxiliary pixel electrode during a second driving period of the one horizontal period, A data voltage of a different polarity is input to the data line and the second data line, the pixel includes a common electrode to which a common voltage is supplied, an auxiliary pixel electrode formed on an upper end of the common electrode through a first insulator, And a pixel electrode formed on the upper side of the auxiliary pixel electrode with a second insulator therebetween for driving the liquid crystal together with the common electrode using the data voltage supplied through the data line.

According to the present invention, a data voltage three times higher than the data voltage that has been output in the past can be output by using a data driver that has been conventionally used.

1 is an exemplary view showing a panel configuration of a conventional liquid crystal display device.
2 is an exemplary diagram showing an equivalent circuit of one pixel of a conventional liquid crystal display device.
3 is an exemplary view showing waveforms applied to a conventional liquid crystal display device;
4 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.
FIG. 5 is a plan view showing the configuration of two pixels among the pixels shown in FIG. 4; FIG.
FIG. 6 is an exemplary view schematically showing one pixel of the pixels shown in FIG. 4; FIG.
FIG. 7 is an equivalent circuit diagram of an embodiment of a first one of the pixels shown in FIG. 5; FIG.
Fig. 8 is an exemplary view showing waveforms applied to the pixels shown in Fig. 5; Fig.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a plan view showing the configuration of two pixels among the pixels shown in FIG. 4, FIG. 6 is a cross-sectional view of a pixel shown in FIG. 4, and FIG. Fig. 8 is an exemplary diagram showing one pixel in an approximate manner.

4 to 6, the liquid crystal display according to the present invention includes a common electrode 110 to which a common voltage VC is supplied, a first electrode And a data electrode (Vd) formed on an upper portion of the auxiliary pixel electrode (120) with a second insulator (not shown) interposed therebetween, A pixel P including a pixel electrode 130 for driving a liquid crystal together with two gate lines GL1-1 and GL1-2 and two data lines DL1-1 and DL1-2, A liquid crystal panel (100) formed at each intersection region of the liquid crystal panel (100); A data driver 300 for outputting data voltages Vd to the data lines DL1-1, DL1-2, ..., DLd-1, DLd-2; A gate driver 200 for sequentially outputting a gate-on voltage to the gate lines GL1-1, GL1-2, ..., GLg-1, and GLg-2; And a timing controller (400) for controlling the gate driver (200) and the data driver (300).

First, in the panel 100, the gate lines GL1-1, GL1-2, ..., GLg-1, and GLg-2 and the data lines DL1-1, DL1-2, , DLd-1, and DLd-2, and a pixel P is formed in each of the intersecting regions of two data lines.

The pixel P includes a common electrode 110, an auxiliary pixel electrode 120, a pixel electrode 130, a first transistor TR1, a second transistor TR2, a third transistor TR3, (Not shown) and a second insulator (not shown).

A common voltage is supplied from the common voltage generator (not shown) to the common electrode 110. The common electrode 110 includes a first common electrode 111 covered by a black matrix and a second common electrode 112 formed at an opening of the pixel.

The first common electrode 111 is connected to each pixel as shown in Fig.

The second common electrode 112 extends from the first common electrode 111, as shown in FIG. 5, and is formed at one of the pixels, particularly at the opening. The second common electrode 112 is formed in a finger shape. The second common electrode 112 forms an electric field together with the first pixel electrode 131 forming the pixel electrode 130 and the second pixel electrode 132 of the second pixel electrode 132, . That is, the second pixel electrode 132 and the second common electrode 112 are turned on by the data voltage supplied to the second pixel electrode 132 and the common voltage supplied to the second common electrode 112, And the transmissivity of light is controlled.

In the region facing the first common electrode 111 with the opening of the pixel P interposed therebetween, a third common electrode 112 connected to the second common electrode 112 of each pixel P An electrode 113 may be further formed.

The auxiliary pixel electrode 120 is formed on the top of the common electrode with a first insulator (not shown) therebetween. The auxiliary pixel electrode 120 is formed in a shape corresponding to the first common electrode 111. That is, the auxiliary pixel electrode 120 does not include the structure corresponding to the second common electrode 112.

A first capacitor Cst1 is formed between the auxiliary pixel electrode 120 and the common electrode 110 and a second capacitor Cst2 is formed between the auxiliary pixel electrode 120 and the pixel electrode 130. [ do.

The pixel electrode 130 is formed on the upper side of the auxiliary pixel electrode 120 with a second insulator (not shown) therebetween. The pixel electrode 130 is formed on the common electrode 110 using the data voltage Vd supplied through the data line. And the liquid crystal is driven.

The pixel electrode 130 includes a first pixel electrode 131 formed to correspond to the auxiliary pixel electrode with the second insulator (not shown) therebetween, and a second pixel electrode 132 formed at the opening of the pixel ). As described above, by the data voltage supplied to the second pixel electrode 132 and the common voltage supplied to the second common electrode 112, the second pixel electrode 132, The transmissivity of light is controlled by driving the liquid crystal located between the liquid crystal layer 112 and the liquid crystal layer.

4 to 6, two gate lines GL1-1 and GL1-2 are adjacent to each other and two data lines DL1-1 and DL1-2 are connected to each other with an opening therebetween Are shown as being spaced apart. However, the two gate lines and the two data lines may be formed on the panel in various forms.

A first gate line GL1-1 of the two gate lines GL1-1 and GL1-2 is connected between the first data line DL1-1 and the pixel electrode 130 among the two data lines constituting one pixel P, The first transistor TR1 is turned on by the gate-on voltage supplied to the first data line DL1-1 and the auxiliary pixel electrode 120. The first transistor TR1 is turned on by the gate- A third transistor TR3 turned on by the gate-on voltage supplied to the second gate line GL1-2 is formed, and the second data line DL1-2 of the two data lines, A second transistor TR2 turned on by the gate-on voltage supplied to the first gate line GL1-1 is formed between the electrodes 120. [

Next, the gate driver 200 applies the gate control signals GCS generated by the timing controller 400 to the gate lines GL1-1, GL1-2, ..., GLg-1, On voltage is sequentially supplied to each of the gate electrodes GLg-1 and GLg-2.

Here, the gate-on voltage refers to a voltage capable of turning on the first to third transistors TR1, TR2 and TR3 connected to the gate lines. The voltage that can turn off the transistor is referred to as a gate off voltage, and the gate on voltage and the gate off voltage are generically referred to as a scan signal.

When the transistor is N type, the gate-on voltage is a high level voltage (VGH) and the gate-off voltage is a low level voltage (VGL). When the thin film transistor is of the P type, the gate-on voltage is a low level voltage (VGL) and the gate-off voltage is a high level voltage (VGH). Hereinafter, the present invention will be described by way of example in which the transistors are formed in N-type.

The gate driver 200 may be formed of a gate drive IC, in which case the gate drive IC may be connected to the panel 100 via a tape carrier package (TCP) or a flexible printed circuit board (FPCB) And may be mounted directly on the non-display area of the panel 100. [ In addition, the gate driver 200 may be configured as a gate-in-panel (GIP) method in which the panel 100 is mounted.

The gate driver 200 may be formed only in one of the non-display areas of the panel 100, but may be formed in two non-display areas facing each other.

Meanwhile, the gate driver 200 is formed between the first data line DL1-1 and the pixel electrode 130 of the two data lines during a first driving period DR1 of one horizontal period On voltage is applied to the first transistor (TR1) and the second transistor (TR2) formed between the second data line (DL1-2) and the auxiliary pixel electrode (120) of the two data lines On voltage is applied to the third transistor TR3 formed between the first data line DL1-1 and the auxiliary pixel electrode 120 during the second driving period DR2 of the one horizontal period do.

That is, the gate driver 200 divides one horizontal period in which the data voltage is output to the panel into a first driving period and a second driving period, and first, in the first driving period DR1, the first gate line GL1- 1) to turn on the first transistor TR1 and the second transistor TR2 connected to the first gate line GL1-1, and in the second driving period DR2, On voltage to the second gate line GL1-2 and turns on the third transistor TR3 connected to the second gate line GL1-2.

Next, the data driver 300 converts the digital image data transmitted from the timing controller 400 into a data voltage and supplies the data voltages to the two gate lines GL1-1 and GL1-2 ) To the data lines for one horizontal line in each horizontal period in which gate-on voltages are supplied.

The data driver 300 may include at least one source driver IC connected to the panel 100 in a chip-on-film (COF) form.

The data driver 300 converts the image data into the data voltage using gamma voltages supplied from a gamma voltage generator (not shown), and outputs the data voltage to the data line. To this end, the data driver 300 includes a shift register unit, a latch unit, a digital-analog converter (DAC), and an output buffer.

The shift register unit outputs a sampling signal using data control signals (SSC, SSP, etc.) received from the timing controller (400).

The latch unit latches the digital image data Data sequentially received from the timing controller 400 and simultaneously outputs the latched digital image data Data to the digital-analog converter (DAC) 330.

The digital-to-analog converter converts the image data transmitted from the latch unit into a data voltage of positive or negative polarity and outputs the same. That is, the digital-analog converter uses the gamma voltage supplied from the gamma voltage generator (not shown) to generate the image data according to the polarity control signal POL transmitted from the timing controller 400 Polarity or negative polarity data voltage and outputs the data voltage to the data lines. In this case, the gamma voltage generator converts the image data into the data voltage using the input voltage Vdd.

The output buffer outputs a positive or negative polarity data voltage transmitted from the digital-analog converter to the data line DL of the panel according to a source output enable signal SOE transmitted from the timing controller 400, .

The data driver 300 may be configured to apply a positive data voltage Vd1 + and a negative data voltage Vd1-, which are symmetrical to a common voltage applied to the common electrode, To the first data line DL1-1 and the second data line DL1-2. In this case, the data voltages supplied to the first data line DL1-1 and the second data line DL1-2 are symmetrical to the common voltage VC supplied to the pixels. For example, when the common voltage is 6V and the data voltage supplied to the first data line DL1-1 is + 10V, the difference between the data voltage and the common voltage is +4V. Therefore, as the second data line DL1-2, +2 V which is different from the common voltage by -4 V is supplied as the data voltage. In this case, +10 V becomes a positive (+ polarity) data voltage, and +2 V becomes a negative (- polarity) data voltage.

In addition, the data driver 300 changes polarities supplied to the first data line and the second data line after a predetermined period of time elapses. For example, during the first frame, the positive data voltage Vd1 + is supplied to the first data line DL1-1 and the negative data voltage Vd1- is supplied to the second data line DL1-2. A negative data voltage may be supplied to the first data line and a positive data voltage may be supplied to the second data line during the second frame. The preset period may be variously set in consideration of the characteristics of the panel.

Lastly, the timing controller 400 uses the timing signals input from the external system, that is, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE, The data driver 300 generates a gate control signal GCS for controlling the operation timing of the data drivers 300 and a data control signal DCS for controlling the operation timings of the data drivers 300, And generates data.

To this end, the timing controller 400 includes a receiver for receiving input image data and timing signals from the external system, a control signal generator for generating various control signals, A data arrangement unit for outputting rearranged image data Data, and an output unit for outputting the control signals and the image data.

That is, the timing controller 400 rearranges the input image data input from the external system according to the structure and characteristics of the panel 100, and outputs the rearranged image data to the data driver 300, Lt; / RTI > Such a function can be executed in the data arrangement section.

The timing controller 400 controls the timing of the data driver 300 using the timing signals transmitted from the external system, that is, the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, and the data enable signal DE. ) And a gate control signal (GCS) for controlling the gate driver 200, and transmits the control signals to the data driver and the gate driver . This function can be executed in the control signal generation unit.

The gate control signals GCS generated by the control signal generator include a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE, a gate start signal VST, a gate clock GCLK, .

The data control signals generated by the control signal generator include a source start pulse SSP, a source shift clock signal SSC, a source output enable signal SOE, and a polarity control signal POL.

The gate driver 200 may output two gate-on voltages to be transferred to two gate lines during one horizontal period, as described above, using the gate control signals transmitted from the timing controller 400 .

In addition, the data driver 300 uses the data control signals transmitted from the timing controller 400 to generate two data voltages Vd1 + and Vd1- that are symmetrical to the common voltage during one horizontal period, And outputs it to two data lines.

Hereinafter, a method of driving a liquid crystal display device according to the present invention will be described in detail with reference to Figs. 4 to 8. Fig.

FIG. 7 is an equivalent circuit diagram of an embodiment of a first one of the pixels shown in FIG. FIG. 8 is a diagram illustrating waveforms applied to the pixels shown in FIG. 5, in which (a) shows a first data line DL1-1 and a second data line DL1-2 of the first pixel P1, (B) shows a first gate-on voltage supplied to the first gate line GL1-1, and (c) shows a first gate-on voltage supplied to the first gate line GL1-1. (D) shows the first node voltage Vp1 of the first pixel P1, and (e) shows the second gate voltage supplied to the second gate line GL1-2. And the first node voltage Vp2 of the two pixels P2. The first node voltage Vp1 of the first pixel P1 and the first node voltage Vp2 of the second pixel P2 become the pixel voltage for driving the liquid crystal together with the common voltage. Hereinafter, for convenience of explanation, the present invention will be described by taking the first pixel P1 shown in Figs. 5 to 7 as an example.

That is, in the method of driving a liquid crystal display device according to the present invention, in a first driving period of one horizontal period, a first transistor formed between a first data line and a pixel electrode among two data lines formed in a pixel, Applying a gate-on voltage to a second transistor formed between a second data line and an auxiliary pixel electrode of the two data lines, and applying a gate-on voltage to the first data line and the auxiliary pixel electrode during a second driving period of the one horizontal period, And applying a gate-on voltage to the third transistor formed between the auxiliary pixel electrodes. This will be described in detail as follows.

In the first step, when the first gate-on voltage Vg1-1 is supplied to the first gate line GL1-1 during the first driving period DR1 of one horizontal period, as shown in Figs. 5 to 7 , The first transistor TR1 and the second transistor TR2 are turned on.

In this case, data voltages are supplied to the first data line and the second data line. The positive data voltage Vd1 + supplied through the first data line DL1-1 is supplied to the pixel electrode 130 to be charged in the first capacitor Cst1 and the second data line DL1-2 The negative data voltage Vd1- supplied to the auxiliary pixel electrode 120 is charged to the second capacitor Cst2.

Accordingly, the first node voltage Vp1 and the second node voltage Vc1 of the first pixel P1 are expressed by Equation (1).

In the second step, when the first gate-on voltage Vg1-1 supplied to the first gate line GL1-1 is turned off after the first driving period DR1 is terminated, the first node voltage Vp is turned on, A voltage drop dVp due to gate-off occurs, and a second node voltage Vc and a voltage drop dVc are generated.

Therefore, the first node voltage Vp1 of the first pixel P1 in consideration of the voltage drop due to the first gate-on voltage Vg1-1 is expressed by Equation (2).

In the third step, when the second driving period DR2 is started and the second gate-on voltage Vg1-2 is supplied to the second gate line GL1-2, the second node voltage Vc becomes negative data Is charged from the voltage Vd1- to the positive data voltage Vd +.

At this time, since the potential difference formed by the first capacitor Cst1 is maintained by the characteristic of the capacitor, the first node voltage Vp becomes the variation amount (Vd +) - (Vd -)).

At this time, in consideration of the voltage drop as shown in Equation (2), the first node voltage Vp1 of the first pixel P1 is changed as shown in Equation (3).

In the fourth step, when the second driving period DR1 is ended and the second gate-on voltage Vg1-2 supplied to the second gate line GL1-2 is turned off, the first node voltage Vp1, A voltage drop dVp1 due to gate-off occurs, and a second node voltage Vc and a voltage drop dVc are generated.

Accordingly, the first node voltage Vp1 of the first pixel P1 considering the voltage drop due to the second gate-on voltage Vg1-2 is finally expressed as shown in Equation (4).

Here, dVp is the voltage drop of the first node voltage Vp1 due to the first gate voltage Vg1-1, dVc1 is the voltage drop of the second node voltage Vc1 due to the first gate voltage Vg1-1, And dVc2 is the voltage drop of the second node voltage Vc1 due to the second gate voltage Vg1-2.

Hereinafter, a liquid crystal display device driving method according to the present invention as described above will be described in detail with reference to Fig. That is, FIG. 8 shows data voltages (Vd1 +, Vd1-), gate-on voltages (Vg1-1, Vg1-2) applied to the liquid crystal display according to the present invention driven by the Z- And the first node voltages Vp1 and Vp2.

Here, since the waveforms shown in Figs. 8A to 8D are the waveforms related to the first pixel P1, first, a description will be given of Figs. 5 to 7 and Figs. 8A to 8D , The first node voltage Vp2 of the second pixel P2 is described with reference to FIG. 8 (e).

That is, the waveform shown in FIG. 8E shows the first node voltage Vp2 of the second pixel P2 as described above. As shown in FIG. 5, the waveform of the first data line The first node voltage Vp2 when the polarity of the data voltage supplied to the first data line DL2-1 and the second data line DL2-2 is opposite to the first pixel. Therefore, the first node voltage Vp2 of the second pixel P2 shown in (e) has a characteristic opposite to the first node voltage Vp1 of the first pixel P1 shown in (d) .

In the following description, it is assumed that the voltage drops of dVp and dVc fall by 1V and 0.5V, respectively, by Vg1-1 and Vg1-2.

In the following description, the present invention is described as an example in which the positive data voltage (Vd1 +) is 16V and the negative data voltage (Vd1-) is 0V for white display.

In the first step S1, the first gate-on voltage Vg1-1 is applied to the first gate line GL1-1 during the first driving period DR1, as shown in Fig. 8 (b) The first transistor TR1 and the second transistor TR2 shown in FIG. 7 are turned on.

In this case, the first data line and the second data line are supplied with the positive data voltage (Vd1 + = 16V) and the negative data voltage (Vd1- = 0V) as shown in FIG. 8A.

Therefore, the first node voltage Vp1 of the first pixel P1 becomes 16V as shown in Fig. 8 (d) by the following equation (1).

That is, since Vp1 = Vd1 +, the first node voltage Vp1 becomes 16V (Vd1 +).

In the second step S2, when the first driving period DR1 is ended and the first gate-on voltage Vg1-1 supplied to the first gate line GL1-1 is turned off, The voltage drop dVp due to gate-off is generated in the node Vp, and the second node voltage Vc and the voltage drop dVc are generated.

Therefore, when the voltage drop dVp due to the first gate-on voltage Vg1-1 is 1V, the first node voltage Vp1 of the first pixel P1 is expressed by the following equation (2) 15V, as shown in (d) of Fig.

That is, since Vp1 = (Vd1 +) - (dVp), the first node voltage Vp1 becomes 15V (16V-1V).

In the third step S3, when the second driving period DR2 is started and the second gate-on voltage Vg1-2 is supplied to the second gate line GL1-2, the second node voltage Vc is applied, Is charged from the negative data voltage Vd1- to the positive data voltage Vd +.

At this time, since the potential difference formed by the first capacitor Cst1 is maintained by the characteristic of the capacitor, the first node voltage Vp becomes the variation amount (Vd +) - (Vd -)).

Therefore, the first node voltage Vp1 of the first pixel P1 becomes 31 V by the formula (3).

That is, the first node voltage Vp1 is 31V ([16V-1V] + [16V - 0V]) since Vp1 = [(Vd1 +) - (dVp)] + [(Vd1 + .

In the fourth step, when the second driving period DR1 is ended and the second gate-on voltage Vg1-2 supplied to the second gate line GL1-2 is turned off, the second node voltage Vc A voltage drop (dVc) is generated.

Therefore, the first node voltage Vp1 of the first pixel P1 considering the voltage drop due to the second gate-on voltage Vg1-2 is finally 31V by Equation (4).

That is, since the first node voltage Vp1 is 31V ([16V (Vd1 +) - (dVp)] because Vp1 = [(Vd1 +) - (dVp)] + -1V] + [16V-0.5V-0V + 0.5V]). Here, the voltage drop (dVc1) at the second node due to the first gate-on voltage and the voltage drop (dVc2) at the second node due to the second gate-on voltage are canceled.

Therefore, a difference of 24 V occurs between the first node voltage Vp1 of 31 V and the common voltage of 7 V. 3 (d), in the conventional liquid crystal display device, the difference between the first node voltage Vp1 and the common voltage is 8 V, but it is 24 V in the liquid crystal display device according to the present invention.

Thus, the liquid crystal display device according to the present invention can drive the liquid crystal at a higher voltage.

Hereinafter, the present invention as described above will be briefly summarized.

As the size of liquid crystal display devices is increased, demands for high-voltage driving are becoming stronger. The present invention addresses this need, and particularly changes the pixel driving method so that a conventional data driver can be used.

That is, the maximum driving voltage of the liquid crystal display device does not exceed the driving voltage VDD of the currently used data driver. Therefore, it is necessary to develop a high-voltage data driver in order to cope with a high voltage.

However, the present invention proposes a method of tripling the driving voltage of a pixel by using the VDD voltage and the gamma voltage which are conventionally used.

That is, in order to drive the 8V liquid crystal, VDD is supplied at 16V and the liquid crystal voltage is generated by +/- 8V symmetry based on the VCOM. In the present invention, however, the voltage of both polarities of the data voltage is charged, Capacitance can be used to charge the data voltage one more time and the liquid crystal driving voltage can be tripled.

Therefore, according to the present invention, the output voltage and the gate-on voltage of the current data driver can be used as they are, and a flexible driving voltage can be applied. That is, it is possible to generate a liquid crystal driving voltage equal to 3/2 of the VDD voltage.

In addition, the present invention can be applied to a liquid crystal display device such as LTPS, Oxide or the like which can reduce the TFT size and a liquid crystal display device which requires high voltage driving.

Further, according to the present invention, the applied data voltage for pixel driving can be raised to three times the voltage in the pixel.

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

100: liquid crystal panel 200: gate driver
300: Data driver 400: Timing controller

Claims (10)

A common electrode to which a common voltage is supplied;
An auxiliary pixel electrode formed on the top of the common electrode with a first insulator interposed therebetween; And
A pixel including a pixel electrode for driving a liquid crystal together with the common electrode using a data voltage supplied through a data line, the pixel electrode being formed on the upper side of the auxiliary pixel electrode with a second insulator therebetween,
Wherein the first and second data lines are formed at intersecting regions of two gate lines and two data lines. The method according to claim 1,
Wherein the common electrode includes a first common electrode covered by a black matrix and a second common electrode formed in an opening of the pixel,
Wherein the pixel electrode includes a first pixel electrode formed to correspond to the auxiliary pixel electrode with the second insulator therebetween, and a second pixel electrode formed in an opening of the pixel,
Wherein the liquid crystal is driven by the common voltage supplied to the second common electrode and the data voltage supplied to the second pixel electrode. The method according to claim 1,
A first transistor turned on by a gate-on voltage supplied to a first one of the two gate lines is formed between the first data line and the pixel electrode of the two data lines,
A third transistor which is turned on by a gate-on voltage supplied to a second one of the two gate lines is formed between the first data line and the auxiliary pixel electrode,
And a second transistor which is turned on by a gate-on voltage supplied to the first gate line is formed between the second data line and the auxiliary pixel electrode of the two data lines. A common electrode to which a common voltage is supplied, an auxiliary pixel electrode formed on an upper end of the common electrode with a first insulator interposed therebetween, and a data line formed on the upper side of the auxiliary pixel electrode, A pixel including a pixel electrode for driving a liquid crystal together with the common electrode using a voltage is formed for each intersection region of two gate lines and two data lines;
A data driver for outputting data voltages to the data lines; And
And a gate driver for sequentially outputting a gate-on voltage to the gate lines. 5. The method of claim 4,
A first transistor turned on by a gate-on voltage supplied to a first one of the two gate lines is formed between the first data line and the pixel electrode of the two data lines,
A third transistor which is turned on by a gate-on voltage supplied to a second one of the two gate lines is formed between the first data line and the auxiliary pixel electrode,
And a second transistor which is turned on by a gate-on voltage supplied to the first gate line is formed between the second data line and the auxiliary pixel electrode of the two data lines. 5. The method of claim 4,
The gate driver includes:
A first transistor formed between the first data line and the pixel electrode of the two data lines and a second transistor formed between the second data line and the auxiliary pixel electrode, On voltage is applied to the second transistor formed between the first transistor and the second transistor,
On voltage is applied to a third transistor formed between the first data line and the auxiliary pixel electrode during a second driving period of the one horizontal period. The method according to claim 6,
The data driver includes:
Wherein a positive data voltage and a negative data voltage symmetrical to a common voltage applied to the common electrode are supplied to the first data line and the second data line. 8. The method of claim 7,
The data driver includes:
And changes a polarity supplied to the first data line and the second data line when a predetermined period elapses. A first transistor formed between a first data line and a pixel electrode of the two data lines formed in the pixel and a second transistor formed between the second data line and the second data line, Applying a gate-on voltage to a second transistor formed between the pixel electrodes; And
And applying a gate-on voltage to a third transistor formed between the first data line and the auxiliary pixel electrode during a second driving period of the one horizontal period,
A data voltage having a different polarity is input to the first data line and the second data line during one horizontal period,
Wherein the pixel is formed on a common electrode to which a common voltage is supplied, an auxiliary pixel electrode formed on an upper end of the common electrode with a first insulator therebetween, and a second insulator disposed on the upper side of the auxiliary pixel electrode, And a pixel electrode for driving the liquid crystal together with the common electrode using the data voltage supplied through the common electrode. 10. The method of claim 9,
Wherein data voltages supplied to the first data line and the second data line are symmetrical to a common voltage supplied to the pixel.

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