KR101951298B1 - Liquid crystal display device and method of fabricating the same - Google Patents

Abstract

A liquid crystal display device and a method of manufacturing the same according to the present invention are a gate in panel (GIP) type liquid crystal display device in which a gate driver is directly mounted in an array substrate, an array substrate divided into an active region in which an image is displayed and a GIP circuit portion in which a gate driver is mounted, for implementing a narrow bezel by reducing a channel size by applying a double gate structure. A color filter substrate bonded to the array substrate so as to be opposite to each other; A thin film transistor formed on the array substrate of the active region, the thin film transistor including a gate electrode, an active layer, and a source / drain electrode; And a GIP circuit part thin film transistor formed on the array substrate of the GIP circuit part, the GIP circuit part gate electrode being composed of a GIP circuit part active layer and a GIP circuit part source / drain electrode, And a second GIP circuit part gate electrode located on the upper part of the active layer of the GIP circuit part.

Description

TECHNICAL FIELD [0001] The present invention relates to a liquid crystal display device and a method of manufacturing the same,

The present invention relates to a liquid crystal display device and a method of manufacturing the same, and more particularly, to a liquid crystal display device using a gate in panel (GIP) method in which a gate driver using an amorphous silicon thin film transistor is directly mounted in an array substrate, And a manufacturing method thereof.

2. Description of the Related Art In general, a liquid crystal display device is a display device that displays a desired image by individually supplying data signals according to image information to pixels arranged in a matrix form and adjusting the light transmittance of the pixels.

To this end, the liquid crystal display device includes a liquid crystal display panel in which pixels are arranged in a matrix form, and a driving circuit for driving the pixels.

In the liquid crystal display panel, an array substrate on which a thin film transistor array is formed and a color filter substrate on which a color filter is formed are bonded together to maintain a uniform cell gap, And a liquid crystal layer is formed therebetween.

At this time, an alignment film is formed on the surface of the array substrate opposite to the color filter substrate, and rubbing is performed so that the liquid crystal of the liquid crystal layer is aligned in a predetermined direction.

In addition, the array substrate and the color filter substrate are bonded together by an actual pattern formed along the outer periphery of the pixel portion, and a polarizing plate, a retardation plate, and the like are provided on the outer surface of the array substrate and the color filter substrate, By selectively configuring the elements, a liquid crystal display panel having high luminance and contrast characteristics can be constituted by changing the progress of light or changing the refractive index.

Hereinafter, a liquid crystal display device configured as above will be described in detail with reference to the drawings.

Fig. 1 is an exemplary view schematically showing a structure of a general liquid crystal display device.

As shown in the figure, a typical liquid crystal display device comprises a liquid crystal display panel 10 and a driving circuit unit 30 for supplying various signals necessary for image formation of the liquid crystal display panel 10.

The liquid crystal display panel 10 includes a first substrate and a second substrate which are adhered to each other with the liquid crystal layer and the liquid crystal layer interposed therebetween. An array element for driving the liquid crystal . That is, a plurality of gate lines 16 and data lines 17 are arranged on the array substrate to define pixels in a matrix form, and thin film transistors are provided at the intersections of the gate lines 16 and the data lines 17 to form pixel electrodes One to one.

In addition, on the inner surface of the second substrate, which is called a color filter substrate, a color filter for color implementation as well as a color filter element such as a common electrode facing the pixel electrode with a liquid crystal layer therebetween are provided. As a result, The electrode and the common electrode constitute a liquid crystal capacitor.

Next, the driving circuit unit 30 includes a timing controller 35, a gate driver 31 and a data driver 32, and further includes an interface, a reference voltage A generator, a power supply voltage generator, and the like.

At this time, the interface relays the timing controller 35 with an external drive system such as a personal computer, and the timing controller 35 controls the timing controller 35 to transmit the frame control signal And the image data and the image control signal transmitted to the data driver 32, respectively.

The gate driver 31 and the data driver 32 are connected to the liquid crystal display panel 10 through a TCP (Tape Carrier Package) or the like so that the gate line 16 and the data line 17 can be connected to each other. And the double gate driver 31 generates a gate signal for sequentially enabling the gate line 16 in every frame in response to the frame control signal of the timing controller 35 And controls the on / off of the thin film transistor for each gate line 16 in response to the image data and the image control signal inputted from the timing controller 35. The data driver 32 controls the on / The reference voltages are selected and supplied to the data line 17.

Accordingly, when the thin film transistor selected for each gate line 16 is turned on by the gate signal of the gate driver 31, the data signal of the data driver 32 is transferred to the pixel through the thin film transistor, The liquid crystal is driven by the electric field between the electrode and the common electrode. During this process, the reference voltage generating unit generates a DAC (Digital To Analog Converter) reference voltage of the data driver 32, and the power source voltage generating unit generates the power source voltage for each element of the driving circuit unit 35, And supplies the common voltage to the common electrode of the second transistor.

In general, a thin film transistor for a liquid crystal display may be classified into an amorphous silicon thin film transistor and a polycrystalline silicon thin film transistor depending on the kind of a semiconductor layer serving as a conductive channel. When the double amorphous silicon is used as the semiconductor layer of the thin film transistor, the gate driver 31 and the data driver 32 are manufactured separately from the liquid crystal display panel 10 as shown in the drawing, and a TAB (Tape Automated Bonding) To the gate line 16 and the data line 17, respectively.

Since the gate driver 31 and the data driver 32 are separately manufactured and attached to the liquid crystal display panel 10 through the TAB method, the liquid crystal display device including the amorphous silicon thin film transistor increases the cost and process do.

In recent years, there has been a demand for a bezel reduction and cost reduction of a high-resolution model, and a gate-in-panel (GIP) type liquid crystal display device having the gate driver incorporated in a liquid crystal display panel has been developed.

Thin film transistors (hereinafter, referred to as GIP circuit thin film transistors) provided in the built-in gate driver occupy a large area unlike thin film transistors provided in a liquid crystal display panel and the like, while a liquid crystal display device incorporating the gate driver has reliability The conventional GIP circuit thin film transistor has a general structure having one channel, and the characteristics of the thin film transistor depend on the type of the semiconductor layer. Thus, the characteristics of the thin film transistor The size of the bezel will be determined accordingly.

The present invention provides a gate-in-panel (GIP) type liquid crystal display device in which a gate driver using an amorphous silicon thin film transistor is directly mounted in a thin film transistor array substrate and a method of manufacturing the same .

It is another object of the present invention to provide a liquid crystal display device in which a channel size is reduced by applying a double gate structure to a GIP circuit portion thin film transistor in the GIP type liquid crystal display device and a method of manufacturing the same.

Other objects and features of the present invention will be described in the following description of the invention and claims.

According to an aspect of the present invention, there is provided a liquid crystal display device comprising: an array substrate divided into an active region in which an image is displayed and a gate in panel (GIP) circuit portion in which a gate driver is mounted; A color filter substrate bonded to the array substrate so as to be opposite to each other; A thin film transistor formed on the array substrate of the active region, the thin film transistor including a gate electrode, an active layer, and a source / drain electrode; And a GIP circuit part thin film transistor formed on the array substrate of the GIP circuit part, the GIP circuit part gate electrode being composed of a GIP circuit part active layer and a GIP circuit part source / drain electrode, And a second GIP circuit part gate electrode located on the upper part of the active layer of the GIP circuit part.

In this case, a pixel electrode and a common electrode formed on the array substrate of the active region are further included.

In this case, the pixel electrodes are formed on the array substrate on a pixel-by-pixel basis, and the common electrodes are formed integrally on the entire surface of the array substrate excluding the plurality of slits.

In this case, the gate electrode of the second GIP circuit part is formed simultaneously with the conductive material constituting the common electrode when forming the common electrode.

And the gate electrode of the second GIP circuit part is formed simultaneously with the conductive material constituting the pixel electrode when forming the pixel electrode.

And the second GIP circuit part gate electrode is electrically connected to the gate electrode of the first GIP circuit part under the gate insulating film and the contact hole formed in the protective film.

A method of manufacturing a liquid crystal display of the present invention includes the steps of: providing an array substrate divided into an active area in which an image is displayed and a GIP circuit part in which a gate driver is mounted; Forming a thin film transistor on the array substrate of the active region, the thin film transistor including a gate electrode, an active layer, and a source / drain electrode; Forming a GIP circuit portion thin film transistor formed on the array substrate of the GIP circuit portion, the GIP circuit portion gate electrode being composed of a GIP circuit portion active layer and a GIP circuit portion source / drain electrode; And bonding the color filter substrate to the array substrate, wherein the GIP circuit portion gate electrode comprises a first GIP circuit portion gate electrode located below the GIP circuit portion active layer and a second GIP circuit portion gate electrode located above the GIP circuit portion active layer And a gate electrode of the second GIP circuit portion.

The method may further include forming a pixel electrode and a common electrode on the array substrate of the active region.

In this case, the pixel electrodes are formed on the array substrate on a pixel-by-pixel basis, and the common electrodes are formed integrally on the entire surface of the array substrate excluding the plurality of slits.

At this time, the gate electrode of the second GIP circuit part is formed simultaneously with the conductive material constituting the common electrode when forming the common electrode.

And the gate electrode of the second GIP circuit part is formed simultaneously with the conductive material constituting the pixel electrode when forming the pixel electrode.

And the second GIP circuit part gate electrode is electrically connected to the gate electrode of the first GIP circuit part under the gate insulating film and the contact hole formed in the protective film.

As described above, the liquid crystal display device and the manufacturing method thereof according to the present invention provide a cost and a process saving effect by directly mounting a gate driver in a thin film transistor array substrate.

Further, in the liquid crystal display device and the method of manufacturing the same according to the present invention, a double gate structure is applied to the GIP circuit portion thin film transistor in the GIP type liquid crystal display device to reduce the channel size and increase the mobility, A narrow bezel is implemented and a response time such as a rising time and a falling time is reduced.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an exemplary view schematically showing the structure of a general liquid crystal display device. Fig.
BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a liquid crystal display device.
3 is a view schematically showing a part of a cross section of the GIP type liquid crystal display device shown in FIG. 2;
4 is a graph showing the transfer characteristics of the GIP circuit portion thin film transistor.
5 is a graph showing the output characteristics of the GIP circuit portion thin film transistor.
6A to 6G are sectional views sequentially showing a method of manufacturing a liquid crystal display of a GIP type according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The present invention may be embodied in many different forms and is not limited to the embodiments described herein.

FIG. 2 is a schematic view illustrating a structure of a liquid crystal display device according to an embodiment of the present invention. Referring to FIG. 2, a gate-in-panel (GIP) method in which a gate driver using an amorphous silicon thin film transistor is directly mounted in an array substrate And shows a liquid crystal display device.

As shown in the figure, the GIP type liquid crystal display device according to the embodiment of the present invention includes a liquid crystal display panel 100 and a driving circuit 130 for supplying various signals necessary for realizing the image.

The liquid crystal display panel 100 includes a liquid crystal layer and first and second substrates bonded together with the liquid crystal layer sandwiched therebetween. An array element and a color filter element are provided on the inner surface of each substrate. A gate line 116 in the horizontal direction and a data line 117 in the vertical direction are vertically and horizontally intersecting each other as an array element on the inner surface of the first substrate, A thin film transistor is provided so as to correspond one-to-one with the pixel electrodes formed in the respective pixels.

For example, red (R), green (G), and blue (B) light, which selectively transmit light of a specific wavelength band as a color filter element, are formed on the inner surface of the second substrate, A color filter composed of color sub-color filters and a color filter element such as a common electrode facing the pixel electrode with the liquid crystal layer interposed therebetween. As a result, the pixel electrode including the liquid crystal layer and the common electrode form a liquid crystal capacitor do. In this case, in the case of an in-plane switching (IPS) liquid crystal display device in which a liquid crystal molecule is driven in a horizontal direction with respect to a substrate to improve a viewing angle, the common electrode is formed in the array substrate together with the pixel electrode.

Next, the driving circuit unit 130 includes a timing controller 135, a gate driver 131, and a data driver 132. In addition, an interface for relaying the external driving system and the timing controller 135, the data driver 132 A power supply voltage generating unit configured to generate a power supply voltage for supplying a common voltage to the common electrode of the liquid crystal display panel 100 and an operation power for each component of the driving circuit unit 130; .

Accordingly, the image and the control signal transmitted from the external driving system are relayed to the timing controller 135 by the interface. In this case, the image signal contains the luminance information of the image to be displayed through the pixels of the liquid crystal display panel 100, The control signal includes a vertical synchronous signal (Vsync) indicating the start or end of the frame picture, a horizontal synchronous signal (Hsync) indicating the start or end of the horizontal pixel column, a valid (Data Enable) for displaying a data interval, and a data clock (DCLK) for indicating a period of effective data.

These image and control signals are transformed into a proper form by the timing controller 135 and supplied to the gate driver 131 and the data driver 132. Thereby, the gate driver 131 sequentially outputs horizontal pixel columns for every frame And the data driver 132 generates a data signal for charging the pixels opened by the gate signal and supplies the data signal to each data line 117 .

Therefore, in the liquid crystal display according to the embodiment of the present invention, when a pixel selected for each gate line 116 is opened by the gate signal of the gate line 116, the data signal of the data line 117 is transmitted to the corresponding pixel, The liquid crystal is driven by the electric field between the pixel electrode and the common electrode to realize a difference in transmittance.

To this end, the timing controller 135 includes a gate shift clock (GSC) for specifying a time when the thin film transistor is turned on, a gate output enable (GOE) for controlling the output of the gate driver 121, A Gate Start Pulse (GSP) signal indicating the horizontal pixel column, and transmits the generated frame control signal to the gate driver 131. In addition, a source control signal for SSC (Source Sampling Clock ), A data latch signal SOE indicating a transfer time point of data latched by the SSC, an SSP (Source Start Pulse) indicating a start point of data in one horizontal signal, a polarity reversal signal synchronized by the SOE And transmits a picture control signal containing a POL or the like alternately indicating positive (+) polarity and negative (-) polarity for determining polarity to the data driver 132.

Meanwhile, the liquid crystal display according to the embodiment of the present invention uses amorphous silicon as a semiconductor layer, which is a conduction channel of a thin film transistor, while a part or all of the gate driver 131 is connected to a first substrate of the liquid crystal display panel 100 The shift resister portion of the gate driver 131 is mounted in the first substrate and can be completed together during the array element manufacturing process.

That is, the gate driver 131 includes a shift register unit including a plurality of flip-flops for outputting a predetermined signal according to an input state of a set and a reset, In the conventional GIP method, at least the shift register unit is mounted on the first substrate. In this case, the shift register unit includes a plurality of gate lines 116 connected in a one-to-one correspondence with the gate lines 116 And shows the shape of the shift resist element group (group) in which the shift resist unit elements are arranged in rows.

Part or all of the gate driver 131 mounted in the liquid crystal display panel 100 can be completed during the manufacturing process for the array elements of the first substrate, thus reducing cost and process.

In addition, a GIP type liquid crystal display device according to an embodiment of the present invention can realize a narrow bezel by reducing a channel size by applying a double gate structure to a GIP circuit portion thin film transistor, which will be described in detail with reference to the drawings.

Reference numeral 115 denotes an active area in which an image is displayed. The area where the gate driver 131 is mounted may be defined as a GIP circuit part, which is located at one side edge of the active area 115.

FIG. 3 is a schematic view showing a part of a cross section of the liquid crystal display device of the GIP type shown in FIG. 2, and shows a part of the GIP circuit part located on the left side of the liquid crystal display panel and a starting point of the active area.

As shown in the drawing, a liquid crystal display panel according to an embodiment of the present invention can be largely divided into an active area in which an image is displayed and a GIP circuit part located at one side edge of the active area and having a gate driver mounted thereon.

The liquid crystal display panel is divided into a liquid crystal layer 105 and an array substrate 110. The color filter substrate 105 and the array substrate 110 are bonded together by a liquid crystal layer, (Not shown in the drawing), the gate lines in the horizontal direction and the data lines in the vertical direction as the array elements are formed on the inner surface of the array substrate 110 of the active area, And a thin film transistor is provided at the intersection of the gate line and the data line and is connected to the pixel electrode 118 formed in each pixel in a one-to-one correspondence manner.

A common electrode 108 is formed on the inner surface of the array substrate 110 to apply an electric field to the liquid crystal layer together with the pixel electrode 118 and to connect the color filter substrate 105 and the array substrate 110 to each other. Polarizing plates 101 and 111 are formed on the outer surface of the polarizing plate 101, respectively. At this time, the pixel electrode 118 is formed on the array substrate 110 on a pixel-by-pixel basis, while the common electrode 108 is formed integrally on the entire surface of the array substrate 110 except for a plurality of slits 108s. Therefore, by controlling the voltage applied to the pixel electrode 118 in the state where the voltage is applied to the common electrode 108, the light transmittance of the pixels can be individually adjusted.

The fringe field formed between the pixel electrode 118 and the common electrode 108 passes through the slit 108s and is electrically connected to the pixel and the common electrode 108. In the liquid crystal display panel according to an embodiment of the present invention, For example, a Fringe Field Switching (FFS) liquid crystal display device that implements an image by driving liquid crystal molecules located on a liquid crystal display (LCD). However, the present invention is not limited thereto, and may be applied to a liquid crystal display device of a twisted nematic (TN) type in which nematic liquid crystal molecules are driven in a direction perpendicular to a substrate as well as a general transverse electric field liquid crystal display device It is possible.

In a pixel in which a scanning signal is supplied to a gate electrode 121 of the thin film transistor through a gate line, a conduction channel is formed between the source electrode 122 and the drain electrode 123 of the thin film transistor, A data signal supplied to the source electrode 122 of the thin film transistor is supplied to the pixel electrode 118 via the drain electrode 123 of the thin film transistor. At this time, amorphous silicon may be applied to the active layer 124 in which the conduction channel of the thin film transistor is formed.

Reference numerals 115a and 115b denote gate insulating films and protective films, respectively. Reference numeral 125n denotes a source / drain region formed between the source / drain regions of the active layer 124 and the source / drain electrodes 122 and 123, Lt; RTI ID = 0.0 > ohmic-contact < / RTI >

Thin film transistors of the gate driver are formed on the inner surface of the array substrate 110 of the GIP circuit portion. The thin film transistors of the gate driver include GIP circuit portion gate electrodes 121p-1 and 121p-2, GIP circuit portion source electrodes 122p, And a GIP circuit portion drain electrode 123p. The thin film transistor of the gate driver is connected between the GIP circuit part source electrode 122p and the GIP circuit part drain electrode 123p by a gate voltage supplied to the GIP circuit part gate electrodes 121p-1 and 121p- And a GIP circuit active layer 124p that forms a gate electrode.

A reference numeral 125np is formed between the source / drain region of the GIP circuit active layer 124p and the source / drain electrodes 122p and 123p of the GIP circuit portion to form a GIP circuit portion ohmic contact layer .

The GIP circuit part gate electrodes 121p-1 and 121p-2 according to the embodiment of the present invention are connected to the first GIP circuit part gate electrode 121p-1 located under the GIP circuit part active layer 124p, And a second GIP circuit portion gate electrode 121p-2 located on the upper layer 124p. That is, in the embodiment of the present invention, a dual gate structure in which a gate electrode (that is, a second GIP circuit portion gate electrode 121p-2) is further formed on the GIP circuit active layer 124p in a bottom gate structure, Structure.

The second GIP circuit part gate electrode 121p-2 can be formed simultaneously through the same mask process when forming the common electrode 108 in the active area. However, the present invention is not limited to this. When the pixel electrode is located at the upper portion instead of the common electrode, the second GIP circuit portion gate electrode 121p- Can be formed at the same time. This eliminates the need for additional masking processes.

The second GIP circuit portion gate electrode 121p-2 can be electrically connected to the first GIP circuit portion gate electrode 121p-1 disposed below the second GIP circuit portion gate electrode 121p-2 through a contact hole formed in the gate insulating film 115a and the protective film 115b have.

On the inner surface of the color filter substrate 105, there are provided a color filter 107 composed of a plurality of sub-color filters which selectively transmit light of a specific wavelength band, for example, colors of red, green and blue as color filter elements A black matrix 106 for separating the sub-color filters from each other and blocking light transmitted through the liquid crystal layer, and an overcoat layer 109 formed on the color filter 107.

At this time, a predetermined seal pattern 140 for attaching the color filter substrate 105 and the array substrate 110 to each other is positioned at the edge of the active area

In order to maintain the cell gap therebetween, the color filter substrate 105 and the array substrate 110 having such a structure are formed with a predetermined column spacer 145 in the active area. In addition, At least one pressing spacer (not shown) may be formed between the column spacers 145.

In the liquid crystal display according to the embodiment of the present invention configured as described above, the GIP circuit portion thin film transistor having the dual gate structure described above has the on-current (on-current) The field effect mobility of the thin film transistor is increased, and the channel size of the thin film transistor can be reduced compared to the conventional structure by increasing the mobility.

That is, in the dual gate structure of the present invention, even if the channel size of the thin film transistor is reduced, the same thin film transistor characteristics as the conventional single gate structure can be obtained.

This enables a narrow bezel by reducing the width of the GIP circuit part. As the ON current of the thin film transistor is improved, a response time such as a rising time and a falling time is increased .

FIG. 4 is a graph showing transfer characteristics of the GIP circuit part thin film transistor. The transfer characteristic of the thin film transistor of the dual gate structure (embodiment) of the present invention is compared with the transfer characteristic of the thin film transistor of the conventional single gate structure .

4 illustrates transfer characteristics of the thin film transistor having the channel length L and the width W of 6 占 퐉 and 1000 占 퐉, respectively.

FIG. 4 also shows transfer characteristics of the thin film transistor located at the center and the thin film transistor located at the edge based on the mother substrate.

Referring to the drawing, it can be seen that the on-current of the thin film transistor which determines the charging / discharging characteristics when driving the liquid crystal display panel is improved by about 46.5% in the case of the thin film transistor of the comparative example.

That is, the on-state current at the gate voltage of 20V and 15V at 25 캜 dark was measured to be about 213.8 평균 averagely in the case of the embodiment while it was measured to be about 146.0 평균 averagely in the comparative example, %.

In addition, although the OFF characteristic is superior to that of the thin film transistor located at the edge based on the mother substrate, the ON characteristic is superior to the edge positioned thin film transistor.

As described above, the characteristics of the dual gate structure thin film transistor considering the distribution of the thin film transistor in the mother substrate are improved by 40.9% ~ 67.1% compared to that of the single gate structure thin film transistor.

5 is a graph showing the output characteristics of the GIP circuit portion thin film transistor. The output characteristics of the thin film transistor of the embodiment are compared with the output characteristics of the thin film transistor of the comparative example.

5 illustrates the output characteristics of the thin film transistor having the channel length L and the width W of 6 占 퐉 and 1000 占 퐉, respectively.

Referring to the drawings, it can be seen that the on-current characteristics of the thin film transistor of the comparative example and the comparative example are improved by about 54%, and the field effect mobility characteristics are also improved.

In addition, when a thin film transistor with a dual gate structure having on-current improved by about 40% is applied, the rising / shortening time is shortened by 0.54 / 2.54 μs in the simulation result. In case of applying the thin film transistor of the dual gate structure improved by 80% And the rising / polling time was shortened by 0.93 / 6.27 占 퐏, respectively.

From the simulation results, it is expected that the embodiment of the present invention can reduce the rising time as well as the falling time.

Hereinafter, a method of manufacturing a liquid crystal display device according to an embodiment of the present invention will be described in detail with reference to the drawings.

6A to 6G are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display of a GIP type according to an embodiment of the present invention.

6A to 6G illustrate a method of manufacturing the above-described fringe field type liquid crystal display device. However, the present invention is not limited thereto, and the present invention is applicable to a twisted nematic liquid crystal display device as well as a general transverse electric field liquid crystal display device.

6A, a gate electrode 121 and a gate line (not shown) are formed in an active region of an array substrate 110 made of a transparent insulating material such as glass, and a GIP pixel A first GIP pixel portion gate electrode 121p-1 is formed.

The gate electrode 121, the gate line, and the first GIP pixel unit gate electrode 121p-1 are formed by depositing a first conductive film on the entire surface of the array substrate 110 and then selectively performing a photolithography process (first mask process) As shown in FIG.

At this time, the first conductive film is formed of aluminum (Al), aluminum alloy (Al alloy), tungsten (tungsten) or the like to form the gate line 121 and the first GIP pixel portion gate electrode 121p- Resistant opaque conductive material such as copper (Cu), chromium (Cr), molybdenum (Mo), and molybdenum alloy. The first conductive layer may have a multi-layer structure in which two or more low-resistance conductive materials are stacked.

6B, a gate insulating layer 115a and an amorphous silicon layer (not shown) are formed on the entire surface of the array substrate 110 on which the gate electrode 121, the gate line, and the first GIP pixel portion gate electrode 121p- To form a thin film and an n + amorphous silicon thin film.

Thereafter, the gate insulating film 115a, the amorphous silicon thin film and the n + amorphous silicon thin film are selectively removed through a photolithography process (a second mask process) to form an active layer 124 of the amorphous silicon thin film on the gate electrode 121 ).

At this time, an n + amorphous silicon thin film pattern 125 formed of the n + amorphous silicon thin film and patterned substantially in the same manner as the active layer 124 is formed on the active layer 124.

The amorphous silicon thin film and the n + amorphous silicon thin film are selectively removed through the second mask process to selectively remove the gate insulating film 115a, the amorphous silicon thin film, and the n + amorphous silicon thin film, Thereby forming the circuit portion active layer 124p.

At this time, a GIP circuit part n + amorphous silicon thin film pattern 125p formed of the n + amorphous silicon thin film and patterned in substantially the same form as the GIP circuit active layer 124p is formed on the active layer 124p of the GIP circuit part do.

6C, a source electrode 122, a drain electrode 123, and data (not shown) are formed in an active region of the array substrate 110 on which the active layer 124 and the n + amorphous silicon thin film pattern 125 are formed. A GIP circuit part source electrode 122p and a GIP circuit part drain 125b are formed in the GIP circuit part of the array substrate 110 on which the GIP circuit part active layer 124p and the GIP circuit part n + amorphous silicon thin film pattern 125p are formed. Thereby forming an electrode 123p.

The source electrode 122, the drain electrode 123, the data line, the source electrode 122p and the GIP circuit portion drain electrode 123p are formed on the active layer 124, the n + amorphous silicon thin film pattern 125, The GIP circuit active layer 124p and the GIP circuit portion n + amorphous silicon thin film pattern 125p are formed on the entire surface of the array substrate 110 and then selectively patterned through a photolithography process (a third mask process).

At this time, the second conductive layer may be formed of aluminum, an aluminum alloy, tungsten, copper, chromium, or the like to form the source electrode 122, the drain electrode 123, the data line, the source electrode 122p and the GIP circuit portion drain electrode 123p. , Molybdenum and molybdenum alloys, and the like. The second conductive layer may be formed in a multi-layered structure in which two or more low-resistance conductive materials are stacked.

At this time, the n + amorphous silicon thin film is patterned between the active layer 124 and the source / drain electrodes 122 and 123 to have substantially the same shape as the source / drain electrodes 122 and 123, An ohmic contact layer 125 for ohmic-contacting the source / drain region of the layer 124 and the source / drain electrodes 122 and 123 is formed.

The n + amorphous silicon thin film is formed between the active layer 124p of the GIP circuit and the source / drain electrodes 122p and 123p of the GIP circuit part and is substantially the same as the source / drain electrodes 122p and 123p of the GIP circuit part. The GIP circuit portion ohmic-contact layer 125np for ohmic-contacting the source / drain region of the GIP circuit active layer 124p and the source / drain electrodes 122p and 123p of the GIP circuit portion is formed.

In this case, the third mask process according to the embodiment of the present invention may use a half-tone mask or a diffraction mask. In this case, the second mask process and the third mask process may be performed by one mask process. That is, the active layer 124, the source / drain electrodes 122 and 123, the GIP circuit active layer 124p and the GIP circuit source / drain electrodes 122p and 123p may be formed together through a single mask process have.

6D, the active layer 124, the source / drain electrodes 122 and 123, the GIP circuit active layer 124p, and the GIP circuit source / drain electrodes 122p and 123p are formed A third conductive film is formed on the entire surface of the array substrate 110.

Thereafter, the third conductive film is selectively removed through a photolithography process (fourth mask process) to form a pixel electrode 118 electrically connected to the drain electrode 123 in the active region.

The third conductive layer may be formed of a transparent conductive material having a high transmittance such as indium tin oxide (ITO) or indium zinc oxide (IZO) to form the pixel electrode 118 .

Next, as shown in FIG. 6E, a protective layer 115b is formed on the entire surface of the array substrate 110 on which the pixel electrode 118 is formed.

Then, the gate insulating film 115a and the protective film 115b of the GIP circuit portion are selectively removed through a photolithography process (fifth mask process) to expose a part of the first GIP circuit portion gate electrode 121p-1 To form a hole (H).

6F, a fourth conductive layer is formed on the entire surface of the array substrate 110, and then selectively patterned through a photolithography process (sixth mask process) to form active A common electrode 108 made of the fourth conductive film is formed. At this time, the common electrode 108 may be formed to have a plurality of slits 108s in each pixel.

In addition, the fourth conductive layer is selectively patterned through the sixth mask process to electrically connect the GIP active layer 124p to the first GIP circuit portion gate electrode 121p-1 through the contact hole H The second GIP circuit portion gate electrode 121p-2 to be connected is formed.

At this time, the fourth conductive layer may be formed of a transparent conductive material having excellent transmittance such as indium-tin-oxide or indium-zinc-oxide.

As described above, the present invention is also applicable to a case where a common electrode is formed on a lower portion and a pixel electrode having a plurality of slits is formed on the upper portion.

Next, as shown in FIG. 6G, the array substrate 110 and the color filter substrate 105 manufactured as described above form a predetermined column spacer 145 in the active region to maintain the cell gap therebetween On the other hand, a predetermined seal pattern 140 is formed at the edges of the active region and is attached to each other.

At this time, the color filter substrate 105 is provided with a color filter 107 composed of a plurality of sub-color filters which selectively transmit light of a specific wavelength band, for example, colors of red, green and blue as color filter elements A black matrix 106 for separating the sub-color filters from each other and blocking light transmitted through the liquid crystal layer, and an overcoat layer 109 formed on the color filter 107 are formed.

Polarizing plates 101 and 111 are formed on the outer surfaces of the color filter substrate 105 and the array substrate 110, respectively.

The present invention can be applied not only to liquid crystal display devices but also to other display devices manufactured using thin film transistors, for example, organic electroluminescent display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors .

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

105: color filter substrate 110: array substrate
118: pixel electrodes 121, 121p-1, 121p-2:
122, 122p: source electrode 123, 123p: drain electrode
124, 124p: active layer

Claims (12)

An array substrate divided into an active area in which an image is displayed and a gate in panel (GIP) circuit part in which a gate driver is mounted;
A color filter substrate bonded to the array substrate so as to be opposite to each other;
A thin film transistor formed on the array substrate of the active region, the thin film transistor including a gate electrode, an active layer, and a source / drain electrode;
A pixel electrode and a common electrode formed on the array substrate of the active region; And
And a GIP circuit part thin film transistor formed on the array substrate of the GIP circuit part and consisting of a gate electrode of a GIP circuit part, an active layer of a GIP circuit part, and a source / drain electrode of a GIP circuit part,
The gate electrode of the GIP circuit part is composed of a first GIP circuit part gate electrode located under the active layer of the GIP circuit part and a second GIP circuit part gate electrode located above the active layer of the GIP circuit part,
And the gate electrode of the second GIP circuit part is formed of the same material as the common electrode by the same process. delete The liquid crystal display device according to claim 1, wherein the pixel electrodes are formed on an array substrate on a pixel-by-pixel basis, and the common electrodes are formed integrally on an entire surface of the array substrate excluding a plurality of slits. delete delete The liquid crystal display of claim 1, wherein the gate electrode of the second GIP circuit part is electrically connected to the gate electrode of the first GIP circuit part below the gate insulating film and the contact hole formed in the protective film. Forming an active region in which an image is displayed and an array substrate divided into a GIP circuit portion in which a gate driver is mounted; forming a gate electrode and a first GIP circuit portion gate electrode in an active region and a GIP circuit portion of the array substrate, respectively;
Forming an active layer and an active layer, a source electrode / drain electrode, and a source / drain electrode of a GIP circuit portion in the active region and the GIP circuit portion, respectively;
Forming a pixel electrode in the active region;
Simultaneously forming a common electrode made of the same material and a second GIP circuit part gate electrode on the pixel electrode of the active area and on the GIP circuit part active layer of the GIP circuit part, respectively; And
And attaching the color filter substrate to the array substrate opposite to the array substrate. delete 8. The method of claim 7, wherein the pixel electrodes are formed on an array substrate on a pixel-by-pixel basis, and the common electrodes are formed integrally on an entire surface of the array substrate excluding a plurality of slits. delete delete The method of claim 7, wherein the gate electrode of the second GIP circuit part is electrically connected to the gate electrode of the first GIP circuit part below the gate insulating film and the contact hole formed in the protective film.

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