KR101996038B1 - Flat panel display device - Google Patents

Abstract

The flat panel display of the present invention is a flat panel display of a gate in panel (GIP) type in which a gate driver is directly mounted in an array substrate, A thin film transistor layout of a coplanar structure is optimized by applying an oxide semiconductor having a high mobility and a small parasitic capacitance to improve the performance of a GIP circuit thin film transistor and to improve the performance of a narrow bezel An array substrate divided into an active area in which an image is displayed and a GIP circuit part in which a gate driver is mounted; A color filter substrate bonded to the array substrate so as to be opposite to each other; An active layer formed of an oxide semiconductor on an array substrate of the GIP circuit portion; A gate electrode formed in a zigzag form on the active layer via a gate insulating film; A protective film formed on the array substrate on which the gate electrode is formed and including first and second contact holes exposing an active layer outside the gate electrode; And a source electrode and a drain electrode formed on the protective film and electrically connected to the source region and the drain region of the active layer through the first contact hole and the second contact hole, 2 contact holes are respectively located above and below the active layer outside the gate electrode, and the source region and the drain region are alternately arranged between the gate electrodes of the zigzag shape.

Description

[0001] FLAT PANEL DISPLAY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a flat panel display, and more particularly, to a gate panel (GIP) type flat panel display in which a gate driver using an oxide semiconductor thin film transistor is directly mounted in an array substrate.

In recent years, there has been a growing interest in information display and a demand for a portable information medium has increased, and a lightweight flat panel display (FPD) that replaces a cathode ray tube (CRT) And research and commercialization are being carried out.

In the field of flat panel display devices, liquid crystal display devices (LCDs), which are light and consumed less power, have attracted the greatest attention, but organic electroluminescent display devices are self- Since it has excellent viewing angle and contrast ratio and does not require a backlight, it can be made lightweight and thin, and is also advantageous from the viewpoint of power consumption.

However, for convenience of explanation, a liquid crystal display device will be described as one of the flat panel display devices.

2. Description of the Related Art In general, a liquid crystal display device is a display device that displays a desired image by individually supplying data signals according to image information to pixels arranged in a matrix form and adjusting the light transmittance of the pixels.

To this end, the liquid crystal display device includes a liquid crystal display panel in which pixels are arranged in a matrix form, and a driving circuit for driving the pixels.

In the liquid crystal display panel, an array substrate on which a thin film transistor array is formed and a color filter substrate on which a color filter is formed are bonded together to maintain a uniform cell gap, A liquid crystal layer is formed in the cell gap between the electrodes.

At this time, an alignment film is formed on the surface of the array substrate opposite to the color filter substrate, and rubbing is performed so that the liquid crystal of the liquid crystal layer is aligned in a predetermined direction.

In addition, the array substrate and the color filter substrate are bonded together by an actual pattern formed along the outer periphery of the pixel portion, and a polarizing plate, a retardation plate, and the like are provided on the outer surface of the array substrate and the color filter substrate, By selectively configuring the elements, a liquid crystal display panel having high luminance and contrast characteristics can be constituted by changing the progress of light or changing the refractive index.

Hereinafter, a liquid crystal display device configured as above will be described in detail with reference to the drawings.

Fig. 1 is an exemplary view schematically showing a structure of a general liquid crystal display device.

As shown in the figure, a typical liquid crystal display device comprises a liquid crystal display panel 10 and a driving circuit unit 30 for supplying various signals necessary for image formation of the liquid crystal display panel 10.

The liquid crystal display panel 10 includes a first substrate and a second substrate which are adhered to each other with the liquid crystal layer and the liquid crystal layer interposed therebetween. An array element for driving the liquid crystal . That is, a plurality of gate lines 16 and data lines 17 are arranged on the array substrate so as to define pixels in a matrix form, and thin film transistors are provided at the intersections of the gate lines 16 and the data lines 17 to correspond to the pixel electrodes formed on each pixel one- Respectively.

In addition, on the inner surface of the second substrate, which is called a color filter substrate, a color filter for color implementation as well as a color filter element such as a common electrode facing the pixel electrode with a liquid crystal layer therebetween are provided. As a result, The electrode and the common electrode constitute a liquid crystal capacitor.

Next, the driving circuit unit 30 includes a timing controller 35, a gate driver 31 and a data driver 32, and further includes an interface, a reference voltage A generator, a power supply voltage generator, and the like.

At this time, the interface relays the timing controller 35 with an external drive system such as a personal computer, and the timing controller 35 controls the timing controller 35 to transmit the frame control signal And the image data and the image control signal transmitted to the data driver 32, respectively.

The gate driver 31 and the data driver 32 are connected to the liquid crystal display panel 10 through a TCP (Tape Carrier Package) or the like so that the gate line 16 and the data line 17 can be connected to each other. And the double gate driver 31 generates a gate signal for sequentially enabling the gate line 16 in every frame in response to the frame control signal of the timing controller 35 And controls the on / off of the thin film transistor for each gate line 16 in response to the image data and the image control signal inputted from the timing controller 35. The data driver 32 controls the on / The reference voltages are selected and supplied to the data line 17.

Accordingly, when the thin film transistor selected for each gate line 16 is turned on by the gate signal of the gate driver 31, the data signal of the data driver 32 is transferred to the pixel through the thin film transistor, The liquid crystal is driven by the electric field between the electrode and the common electrode. During this process, the reference voltage generating unit generates a DAC (Digital To Analog Converter) reference voltage of the data driver 32, and the power source voltage generating unit generates the power source voltage for each element of the driving circuit unit 35, And supplies the common voltage to the common electrode of the second transistor.

On the other hand, an amorphous silicon thin film transistor and a polycrystalline silicon thin film transistor are mainly used in general liquid crystal display devices depending on the kind of a semiconductor layer which serves as a conductive channel. When the double amorphous silicon is used as the semiconductor layer of the thin film transistor, the gate driver 31 and the data driver 32 are manufactured separately from the liquid crystal display panel 10 as shown in the drawing, and a TAB (Tape Automated Bonding) To the gate line 16 and the data line 17, respectively.

Since the gate driver 31 and the data driver 32 are separately manufactured and attached to the liquid crystal display panel 10 through the TAB method, the liquid crystal display device including the amorphous silicon thin film transistor increases the cost and process do.

In recent years, there has been a demand for a bezel reduction and cost reduction of a high-resolution model, and a gate-in-panel (GIP) type liquid crystal display device having the gate driver incorporated in a liquid crystal display panel has been developed.

Thin film transistors (hereinafter, referred to as GIP circuit thin film transistors) provided in the built-in gate driver have a large size, unlike a thin film transistor provided in a liquid crystal display panel and the like, The conventional GIP circuit thin film transistor adopts a back channel etch (BCE) type among the bottom gate structure.

However, since a high-resolution, large-screen, and high-speed driving products are required, an oxide semiconductor thin film transistor having a high mobility is required. In this case, an etch stopper (ES) Structure is widely used.

FIGS. 2 and 3 are plan views schematically showing the layout of a GIP circuit portion thin film transistor in a general GIP type liquid crystal display device, for example, showing the layout of a GIP circuit portion thin film transistor to which two thin film transistors are connected.

Here, FIG. 2 schematically shows a layout part of the GIP circuit part thin film transistor of the BCE structure, and FIG. 3 schematically shows a part of the layout of the GIP circuit part thin film transistor of the ES structure.

Referring to the drawings, a thin film transistor of a bottom gate structure includes gate electrodes 21 'and 21' 'and a gate insulating film (not shown) formed on a substrate, and active layers 24' and 24 ") Is formed. The source / drain electrodes 22 ', 22' ', and 23' 'are formed on the active layers 24' and 24 ' , 23 ") are deposited and etched, the underlying active layers 24 'and 24" may be damaged and denatured.

Thus, the GIP circuit portion thin film transistor of the ES structure further forms an etch stopper 25 on the active layer 24 ''. In this case, the channel length L of the thin film transistor is controlled by the etch stopper 25 Quot;) increases (L? L).

At this time, in order to exhibit the same performance, the channel width W "must also be increased (W '→ W") in proportion to the increase of the channel length L ", and as a result, the area occupied by the GIP circuit thin film transistor And the width of the bezel increases.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a gate in panel (GIP) type flat panel display device in which a gate driver using an oxide semiconductor thin film transistor is directly mounted in a thin film transistor array substrate .

It is another object of the present invention to provide a flat panel display in which a thin film transistor layout is optimized by applying a coplanar structure to a GIP circuit thin film transistor in the GIP type flat panel display.

Other objects and features of the present invention will be described in the following description of the invention and claims.

According to an aspect of the present invention, there is provided a flat panel display comprising: an array substrate divided into an active area for displaying an image and a GIP circuit part for mounting a gate driver; A color filter substrate bonded to the array substrate so as to be opposite to each other; An active layer formed of an oxide semiconductor on an array substrate of the GIP circuit portion; A gate electrode formed in a zigzag form on the active layer via a gate insulating film; A protective film formed on the array substrate on which the gate electrode is formed and including first and second contact holes exposing an active layer outside the gate electrode; And a source electrode and a drain electrode formed on the protective film and electrically connected to the source region and the drain region of the active layer through the first contact hole and the second contact hole, 2 contact holes are respectively located above and below the active layer outside the gate electrode, and the source region and the drain region are alternately arranged between the gate electrodes of the zigzag shape.

In this case, the active layer is formed of an amorphous zinc oxide semiconductor.

The channel length of the thin film transistor is determined by the width of the gate electrode, and the source region and the drain region are separated by the gate electrode.

And the plurality of channels are connected in parallel to each other by the active layer.

Wherein the active layer comprises a first region in a rectangular shape protruding from a second region of a rectangular shape in which the channel is located and a central upper portion of the second region.

In this case, the active layer has a shape in which the left and right oxide semiconductors on the active layer where the first region is located are removed in a rectangular shape as a whole.

In this case, a first open region is formed under the first region of the active layer except for the left and right source regions, and the oxide semiconductor is removed. And the removed second open region is formed.

At this time, the gate electrode of the zigzag shape is formed such that the gate electrode extending in the direction perpendicular to the longitudinal direction of the channel extends upward so that one end thereof is out of the second region of the active layer, Direction is formed in the first and second open regions of the active layer in the upper and lower portions, respectively.

The first and second contact holes are located outside the first and second open regions to expose the active layer outside the first and second open regions.

At this time, the first contact hole exposes the active layer on the upper side of the first open region, and the second contact hole exposes the active layer on the lower side of the second open region.

And there is no overlap between the gate electrode and the source / drain electrode.

And the source electrode or the drain electrode or the source / drain electrode overlaps with the gate electrode.

At this time, the source electrode, the drain electrode, or the source / drain electrode extend toward the gate electrode to constitute the first or second or first and second extending portions, and the first, second, And the second extending portion overlaps with the gate electrode.

As described above, the flat panel display device according to the present invention provides the effect of reducing the cost and the process by directly mounting the gate driver in the thin film transistor array substrate.

Also, in the GIP type flat panel display device, an oxide semiconductor having a large mobility and a small parasitic capacitance is applied to a GIP circuit thin film transistor having a large size to form a thin film of a coplanar structure By optimizing the transistor layout, the performance of the GIP circuit thin film transistor is improved and the narrow bezel is realized.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an exemplary view schematically showing the structure of a general liquid crystal display device. Fig.
2 and 3 are plan views schematically showing the layout of a GIP circuit portion thin film transistor in a general GIP type liquid crystal display device.
4 is a view schematically showing a structure of a liquid crystal display of the GIP system according to the present invention.
5 is a plan view schematically showing a layout of a GIP circuit portion thin film transistor according to the first embodiment of the present invention.
6 is a plan view schematically showing a layout of a GIP circuit portion thin film transistor according to a second embodiment of the present invention.
7 is a cross-sectional view schematically showing a layout of a GIP circuit portion thin film transistor according to a second embodiment of the present invention.
8A to 8D are plan views sequentially illustrating a method of manufacturing a GIP circuit portion thin film transistor according to a second embodiment of the present invention shown in FIG.
9A to 9D are sectional views sequentially illustrating a method of manufacturing a GIP circuit portion thin film transistor according to a second embodiment of the present invention shown in FIG.
10 to 12 are plan views illustrating layouts of GIP circuit thin film transistors according to a third embodiment of the present invention.

Hereinafter, preferred embodiments of the flat panel display according to the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention. The present invention may be embodied in many different forms and is not limited to the embodiments described herein.

4 is a schematic view illustrating the structure of a liquid crystal display device according to the present invention, and shows a GIP type liquid crystal display device in which a gate driver using an oxide semiconductor thin film transistor is directly mounted in an array substrate.

As described above, the liquid crystal display device will be described as one of the flat panel display devices for convenience of explanation, but the present invention is not limited thereto. For example, the present invention is applicable to an organic electroluminescent display device.

As shown in the figure, the GIP type liquid crystal display device according to the present invention includes a liquid crystal display panel 100 and a driving circuit unit 130 for supplying various signals necessary for realizing the image.

Although not shown in detail, the liquid crystal display panel 100 is composed of a liquid crystal layer and first and second substrates bonded together with the liquid crystal layer interposed therebetween, and array elements and color filter elements are provided on the inner surfaces of the substrates. On the inner surface of the first substrate called the array substrate, a matrix-shaped pixel is defined by the horizontal direction gate line 116 and the vertical direction data line 117 as array elements crossing vertically and horizontally, and the gate line 116, A thin film transistor is provided at the intersection of the data lines 117 and is connected to the pixel electrodes formed on the respective pixels in a one-to-one correspondence.

For example, red (R), green (G), and blue (B) light, which selectively transmit light of a specific wavelength band as a color filter element, are formed on the inner surface of the second substrate, A color filter composed of color sub-color filters and a color filter element such as a common electrode facing the pixel electrode with the liquid crystal layer interposed therebetween. As a result, the pixel electrode including the liquid crystal layer and the common electrode form a liquid crystal capacitor do. In this case, in the case of an in-plane switching (IPS) liquid crystal display device in which a liquid crystal molecule is driven in a horizontal direction with respect to a substrate to improve a viewing angle, the common electrode is formed in the array substrate together with the pixel electrode.

Next, the driving circuit unit 130 includes a timing controller 135, a gate driver 131, and a data driver 132. In addition, an interface for relaying the external driving system and the timing controller 135, the data driver 132 A power supply voltage generating unit configured to generate a power supply voltage for supplying a common voltage to the common electrode of the liquid crystal display panel 100 and an operation power for each component of the driving circuit unit 130; .

Accordingly, the image and the control signal transmitted from the external driving system are relayed to the timing controller 135 by the interface. In this case, the image signal contains the luminance information of the image to be displayed through the pixels of the liquid crystal display panel 100 , The control signal includes a vertical synchronous signal (Vsync) indicating a start or end of a frame picture, a horizontal synchronous signal (Hsync) indicating a start or end of a horizontal pixel column, (Data Enable) indicating the effective data section in the data stream, and a data clock (DCLK) indicating the period of effective data.

These image and control signals are transformed into an appropriate form by the timing controller 135 and supplied to the gate driver 131 and the data driver 132. As a result, And the data driver 132 generates a data signal to charge the pixels opened by the gate signal and supplies the data signal to the data lines 117).

Accordingly, in the liquid crystal display according to the present invention, when a pixel selected for each gate line 116 is opened by the gate signal of the gate line 116, the data signal of the data line 117 is transmitted to the corresponding pixel, The liquid crystal is driven by the electric field between the electrode and the common electrode to realize the difference in transmittance.

To this end, the timing controller 135 includes a gate shift clock (GSC) for specifying a time when the thin film transistor is turned on, a gate output enable (GOE) for controlling the output of the gate driver 131, (Gate Start Pulse) indicating a line, and transmits the generated frame control signal to the gate driver 131. In addition, the gate driver 131 receives the SSC (Source A source start pulse (SSP) indicating a start point of data in one horizontal signal, a data start signal (SSP) indicating a start point of data in a horizontal signal, data as a polarity inversion signal synchronized by the SOE And transmits the image control signal containing the POL or the like alternately indicating positive (+) polarity and negative (-) polarity peaks that determine the polarity of the signal to the data driver 132.

Reference numeral 115 denotes an active area in which an image is displayed. The area where the gate driver 131 is mounted may be defined as a GIP circuit part, which is located at one side edge of the active area 115.

Meanwhile, the liquid crystal display according to the present invention uses an oxide semiconductor as a semiconductor layer, which is a conduction channel of a thin film transistor, while a part or all of the gate driver 131 is mounted in the first substrate of the liquid crystal display panel 100 And a shift resister portion of at least the gate driver 131 is mounted in the first substrate and can be manufactured together during the array element manufacturing process.

That is, the gate driver 131 includes a shift register unit having a plurality of flip-flops for outputting a predetermined signal according to a set and reset input states, And a level shifter for amplifying the shift register unit. In the GIP scheme, the shift register unit is mounted on the first substrate. In this case, the shift register unit includes a plurality of shift resister units connected in a one- And shows the shape of the shift resist element group (group) in which the elements are arranged in rows.

Part or all of the gate driver 131 mounted in the liquid crystal display panel 100 can be completed during the manufacturing process for the array elements of the first substrate, thus reducing cost and process.

In addition, the liquid crystal display of the GIP type according to the present invention can realize the narrow bezel by optimizing the layout of the thin film transistor of the coplanar structure in the GIP circuit thin film transistor, which will be described in detail with reference to the drawings.

FIG. 5 is a plan view schematically showing a layout of a GIP circuit portion thin film transistor according to the first embodiment of the present invention, for example, showing the layout of a GIP circuit portion thin film transistor to which two thin film transistors are connected.

FIG. 5 schematically shows a layout of a GIP circuit thin film transistor having a coplanar structure in which a gate electrode and a source / drain electrode are disposed on an active layer.

In other words, as shown in the figure, the thin film transistor of the coplanar structure according to the first embodiment of the present invention includes a buffer layer (not shown) formed on a predetermined substrate, an active layer 124 formed of an oxide semiconductor on the buffer layer, A gate electrode 121 formed on the active layer 124 with an insulating film (not shown) interposed therebetween, and a protective film (not shown) formed on the gate electrode 121 and exposing a source / drain region of the active layer 124 And source / drain electrodes 122 and 123 electrically connected to the source / drain regions of the exposed active layer 124 through the contact hole 140 and the source / drain electrodes 122 and 123, respectively.

At this time, a predetermined region of the active layer 124 made of the oxide semiconductor is exposed when the gate electrode 121 and the gate insulating film are patterned, and the exposed region is reduced in resistance through plasma treatment or heat treatment, Source / drain regions are formed.

Here, the GIP circuit part thin film transistor according to the first embodiment of the present invention is formed by forming the active layer 124 using an amorphous zinc oxide (ZnO) semiconductor to satisfy high mobility and constant current test conditions, And can be applied to a large area display.

The zinc oxide is a material which can realize all three properties of conductivity, semiconductivity and resistance according to oxygen content. An oxide thin film transistor in which an amorphous zinc oxide semiconductor material is applied to an active layer 124 is a liquid crystal display device and an organic electroluminescent And can be applied to a large-area display including a display.

In recent years, a great deal of attention and activity have been concentrated on transparent electronic circuits. The oxide thin film transistor in which the amorphous zinc oxide semiconductor material is applied to the active layer 124 has high mobility and small parasitic capacitance, There is an advantage that it can be used in the transparent electronic circuit.

Particularly, the GIP circuit portion thin film transistor according to the first embodiment of the present invention forms an active layer 124 with an amorphous IGZO semiconductor containing heavy metals such as indium (In) and gallium (Ga) in the zinc oxide can do.

The amorphous IGZO semiconductor is transparent because it can transmit visible light and the oxide thin film transistor made of the amorphous IGZO semiconductor has a mobility of 1 to 100 cm ² / Vs and exhibits a higher mobility characteristic than the amorphous silicon thin film transistor .

In addition, the amorphous IGZO semiconductor can produce a light emitting diode (LED), a white LED and other components having a wide band gap and high color purity and can be manufactured at a low temperature to produce a light and flexible product .

Furthermore, since the oxide thin film transistor fabricated from the amorphous IGZO semiconductor exhibits a uniform characteristic similar to that of an amorphous silicon thin film transistor, the structure of the oxide thin film transistor is as simple as an amorphous silicon thin film transistor and has an advantage that it can be applied to a large area display.

In the GIP circuit portion thin film transistor according to the first embodiment of the present invention, a coplanar structure in which the gate electrode 121 and the source / drain electrodes 122 and 123 are positioned above the active layer 124 is applied The channel region of the oxide semiconductor is not damaged during the etching of the source / drain electrodes 122 and 123, thereby ensuring excellent device characteristics.

The gate electrode 121 is formed in a zigzag shape in order to apply the coplanar structure, while the gate electrode 121 of the zigzag shape is formed in a zigzag shape in the GIP circuit portion thin film transistor according to the first embodiment of the present invention. The source electrode 122 and the drain electrode 123 are alternately arranged in a staggered manner.

In the GIP circuit part thin film transistor according to the first embodiment of the present invention, the channel length of the thin film transistor is determined by the width of the gate electrode 121, while a plurality of channels are connected to each other by the active layer 124 . Further, the source / drain regions for each thin film transistor are separated by the gate electrode 121. [

In order to improve the disadvantages of the conventional bottom gate structure, especially the ES structure, a top gate coplanar structure can be applied. In this case, the contact hole 140 is located between the channels of the thin film transistor And there is a limit in size reduction of the thin film transistor.

Accordingly, the GIP circuit part thin film transistor according to the second embodiment of the present invention is characterized in that a contact hole for limiting a decrease in the size of the thin film transistor is formed outside the gate electrode and an open area is formed on the upper and lower sides of the active layer, The thin film transistor layout can be optimized, which will be described in detail with reference to the following drawings.

6 is a plan view schematically showing a layout of a GIP circuit portion thin film transistor according to a second embodiment of the present invention. For example, the layout of a GIP circuit portion thin film transistor to which two thin film transistors T1 and T2 are connected is shown.

7 is a cross-sectional view schematically showing a layout of a GIP circuit portion thin film transistor according to a second embodiment of the present invention. The cross-sectional view taken along line A-A 'of the GIP circuit portion thin film transistor shown in FIG. Respectively.

6 and 7, in the same manner as in the first embodiment of the present invention, the gate electrode and the source / drain electrode are disposed on the active layer, And has a coplanar structure.

For reference, the arrows P 'and P "shown in FIG. 6 schematically show the direction of current flow.

Referring to the drawings, a GIP circuit part thin film transistor according to a second embodiment of the present invention includes a buffer layer 211 formed on a substrate 210, an active layer 224 formed of an oxide semiconductor on the buffer layer 211, A gate electrode 221 formed on the active layer 224 with an insulating film 215 interposed therebetween, a protective film 215b formed on the gate electrode 221 and exposing a source / drain region of the active layer 224, And source / drain electrodes 222 and 223 electrically connected to the source / drain regions of the exposed active layer 224 through contact holes 240 'and 240' '.

The GIP circuit part thin film transistor according to the second embodiment of the present invention is composed of two thin film transistors of a first thin film transistor T1 and a second thin film transistor T2 which are sequentially arranged along a gate electrode 221 However, the present invention is not limited thereto, and the present invention is applicable to a structure in which two or more thin film transistors are connected.

The contact holes 240 'and 240 "may include a first contact hole 240' for electrically connecting the source region of the exposed active layer 224 and the source electrode 222, And a second contact hole 240 " for electrically connecting the drain region of the second electrode 224 and the drain electrode 223.

At this time, a predetermined region of the active layer 224 made of the oxide semiconductor is exposed when patterning the gate electrode 221 and the gate insulating film 215a thereon, and the exposed region is subjected to a plasma treatment or a heat treatment, Thereby forming a source / drain region which is a contact region. At this time, the channel region of the active layer 224 is formed between the source region and the drain region of the active layer 224, that is, the unexposed oxide semiconductor under the gate electrode 221.

In the GIP circuit part thin film transistor according to the second embodiment of the present invention, since the active layer 224 is formed using the amorphous zinc oxide semiconductor in the same manner as the first embodiment of the present invention, And it has the advantage that it can be applied to a large area display because the uniform characteristics are secured.

Recently, a great deal of attention and activity have been concentrated on transparent electronic circuits. Since an oxide thin film transistor using the amorphous zinc oxide semiconductor material as an active layer 224 has high mobility and small parasitic capacitance and can be manufactured at a low temperature There is an advantage that it can be used in the transparent electronic circuit.

In particular, the GIP circuit part thin film transistor according to the second embodiment of the present invention can form an amorphous IGZO semiconductor active layer 224 containing heavy metals such as indium and gallium in the zinc oxide.

The GIP circuit part thin film transistor according to the second embodiment of the present invention having such characteristics has a gate electrode 221 and a source / drain electrode 222 on the active layer 224, as in the first embodiment of the present invention, And 223 are located, the channel region of the oxide semiconductor is not damaged during the etching of the source / drain electrodes 222 and 223, so that excellent device characteristics can be secured.

In addition, the GIP circuit portion thin film transistor according to the second embodiment of the present invention has a structure in which the gate electrode 221 is formed in a zigzag shape in order to apply the coplanar structure described above, And the region and the drain region are alternately arranged in a staggered manner.

In the GIP circuit portion thin film transistor according to the second embodiment of the present invention, the channel length of the thin film transistor is determined by the width of the gate electrode 221, while a plurality of channels are parallel to each other by the active layer 224 Respectively. In addition, the source / drain regions for the respective thin film transistors are separated by the gate electrode 221.

Particularly, the active layer 224 according to the second embodiment of the present invention is formed in a rectangular shape protruding from a central portion of the second region 224 " and a second region 224 " And a first region 224 '.

That is, the active layer 224 according to the second embodiment of the present invention has a shape in which a part of the left and right oxide semiconductors on the upper part of the active layer 224 in which the first region 224 ' do. However, the present invention is not limited thereto, and the positions of the first region 224 'and the second region 224' of the active layer 224 may be reversed. In this case, the active layer 224 May have a shape in which a part of the left and right oxide semiconductors in the lower portion of the active layer 224 in which the first region 224 'is located is removed in a rectangular shape as a whole.

At this time, a first open region A1 in which a predetermined oxide semiconductor is removed is formed under the first region 224 'of the active layer 224 except for the left and right source regions, and the active layer 224 is formed, A second open region A2 in which a predetermined oxide semiconductor is removed is formed on the left and right sides of the second region 224 "

At this time, the zigzag gate electrode 221 is formed in a direction perpendicular to the channel, that is, in a direction perpendicular to the longitudinal direction of the channel, in order to partition a plurality of channels into the second region 224 '' of the active layer 224 The gate electrode 221 of the active layer 224 extends upwardly so that one end of the gate electrode 221 is out of the second region 224 "of the active layer 224, while a portion of the gate electrode 221 in the direction parallel to the channel, The gate electrode 221 is formed so as to be disposed in the first and second open regions A1 and A2 of the active layer 224 in the upper and lower portions, respectively.

The first and second contact holes 240 'and 240' 'according to the second embodiment of the present invention may be formed outside the gate electrode 221, specifically, the first and second contact holes 240' The active layer 224 is located outside the first and second open regions A1 and A2 to expose the active layer 224 outside the first and second open regions A1 and A2. 'Expose the active layer 224 above the first open area A1 and the second contact hole 240' 'exposes the active layer 224 below the second open area A2. do.

In order to improve the disadvantages of the conventional bottom gate structure, particularly the ES structure, a top-gate coplanar structure can be applied. In the case of the second embodiment of the present invention, the first and second contact holes 240 ' 240 "are formed outside the gate electrode 221 without being formed between the channels of the thin film transistor, and the first and second open regions A and A2 are formed on the upper and lower sides of the active layer 224 By partitioning the plurality of channels in the second region 224 "of the active layer 224, it becomes possible to optimize the thin film transistor layout of the coplanar structure.

Meanwhile, the GIP circuit part thin film transistor according to the second embodiment of the present invention is characterized in that parasitic capacitance is not formed because there is no overlap between the gate electrode 221 and the source / drain electrodes 222 and 223, But is not limited thereto. The present invention is also applicable to the case where the source electrode or the drain electrode or the source / drain electrode overlaps with the gate electrode, and there may be no active layer between the overlapped source / drain electrode and the gate electrode.

Hereinafter, a method of manufacturing a liquid crystal display device according to an embodiment of the present invention will be described in detail with reference to the drawings.

8A to 8D are plan views sequentially illustrating a method of manufacturing a liquid crystal display of a GIP type according to a second embodiment of the present invention shown in FIG.

9A to 9D are cross-sectional views sequentially illustrating a method of manufacturing a liquid crystal display of the GIP type according to the second embodiment of the present invention shown in FIG.

Although not shown in the figure, since the active region in which the image is displayed is manufactured through substantially the same process as the GIP circuit portion, the fabrication method of the array substrate of the active region is described together with the manufacturing method of the array substrate of the GIP circuit portion do.

8A and 9A, an active layer 224 is formed in a GIP pixel portion of an array substrate 210 made of a transparent insulating material such as glass, and an active layer 224 is formed in an active region of the array substrate 210, Thereby forming an active layer.

At this time, the active layer 224 and the pixel active layer are formed by selectively depositing a predetermined oxide semiconductor on the array substrate 210 and then performing a photolithography process (a first mask process).

At this time, a predetermined buffer layer 211 may be formed on the array substrate 210 before the oxide semiconductor is deposited.

As described above, the oxide semiconductor includes an amorphous zinc oxide semiconductor.

At this time, the amorphous zinc oxide semiconductor, particularly, the amorphous IGZO semiconductor is formed by a sputtering method using a composite target of gallium oxide (Ga ₂ O ₃ ), indium oxide (In ₂ O ₃ ) and zinc oxide (ZnO) In addition, it is also possible to use a chemical vapor deposition method such as chemical vapor deposition or atomic layer deposition (ALD).

The amorphous zinc oxide semiconductor used in the oxide thin film transistor according to the second embodiment of the present invention can be used for a low temperature process such as a plastic substrate and a soda lime glass. In addition, since it exhibits amorphous characteristics, it is possible to use a substrate for a large-area display.

As described above, the active layer 224 according to the second embodiment of the present invention includes a rectangular second region 224 " and a rectangular region 224 " And a first region 224 '.

That is, the active layer 224 according to the second embodiment of the present invention has a shape in which a part of the left and right oxide semiconductors on the upper part of the active layer 224 in which the first region 224 ' do. However, the present invention is not limited thereto, and the positions of the first region 224 'and the second region 224' of the active layer 224 may be reversed. In this case, the active layer 224 May have a shape in which a part of the left and right oxide semiconductors in the lower portion of the active layer 224 in which the first region 224 'is located is removed in a rectangular shape as a whole.

At this time, a first open region A1 in which a predetermined oxide semiconductor is removed is formed under the first region 224 'of the active layer 224 except for the left and right source regions, and the active layer 224 is formed, A second open region A2 in which a predetermined oxide semiconductor is removed is formed on the left and right sides of the second region 224 "

Next, as shown in FIGS. 8B and 9B, a predetermined insulating film and a first conductive film are deposited on the array substrate 210 on which the active layer 224 and the pixel active layer are formed, and then a photolithography process 2 mask process) to form a gate electrode 221 made of the first conductive film on the active layer 224, and a gate electrode 221 made of the first conductive film is formed in the active region of the array substrate 210 And a gate line is formed.

At this time, the gate electrode 221 and the pixel portion gate electrode are formed on the active layer 224 and the pixel portion active layer, respectively, with the gate insulating layer 215a made of the insulating layer therebetween, and the active layer 224 ) And the pixel active layer and the gate electrode 221 and the pixel portion gate electrode may be formed through a single mask process by using a diffraction mask or a half-tone mask.

The insulating layer may be formed of an inorganic insulating layer such as a silicon nitride layer or a silicon oxide layer or a high dielectric oxide layer such as hafnium oxide or aluminum oxide. And etching is used. When an insulating film is formed of an oxide series such as SiOx, HfOx, or AlOx, the surface treatment or heat treatment may be performed before the deposition of the insulating film.

In this case, when the insulation layer is etched through the oxygen plasma process to pattern the gate insulation layer 215a, the exposed active layer 224 and the pixel active layer are reduced in resistance by the oxygen plasma, And a predetermined source / drain region and a pixel portion source / drain region are formed in the pixel portion active layer. However, the present invention is not limited thereto. The gate insulating layer 215a may be patterned and then the resistance of the active layer 224 and the pixel active layer exposed through the surface treatment or the heat treatment such as oxygen plasma may be changed .

Al, Al, tungsten, copper, nickel, nickel, chromium, or chromium are used as the first conductive film. A low resistance opaque conductive material such as molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta) The first conductive layer may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or the like. Layer structure.

As described above, in the GIP circuit portion thin film transistor according to the second embodiment of the present invention, the gate electrode 221 is formed in a zigzag shape in order to apply the coplanar structure, and the gap between the gate electrodes 221 in the zigzag shape And the source region and the drain region are alternately arranged in a staggered manner.

In the GIP circuit portion thin film transistor according to the second embodiment of the present invention, the channel length of the thin film transistor is determined by the width of the gate electrode 221, while a plurality of channels are parallel to each other by the active layer 224 Respectively. In addition, the source / drain regions for the respective thin film transistors are separated by the gate electrode 221.

At this time, the zigzag gate electrode 221 is formed in a direction perpendicular to the channel, that is, in a direction perpendicular to the longitudinal direction of the channel, in order to partition a plurality of channels into the second region 224 '' of the active layer 224 The gate electrode 221 of the active layer 224 extends upwardly so that one end of the gate electrode 221 is out of the second region 224 "of the active layer 224, while a portion of the gate electrode 221 in the direction parallel to the channel, The gate electrode 221 is formed so as to be disposed in the first and second open regions A1 and A2 of the active layer 224 in the upper and lower portions, respectively.

In the GIP circuit part thin film transistor according to the second embodiment of the present invention, no parasitic capacitance is formed because there is no overlap between the gate electrode 221 and the source / drain electrodes 222 and 223, The invention is not limited thereto.

8C and 9C, a passivation layer 215b is deposited on the entire surface of the array substrate 210 on which the gate electrode 221, the pixel portion gate electrode, and the gate line are formed, and then a photolithography process A third contact hole 240 'and a second contact hole 240 "are formed to selectively expose a predetermined region of the active layer 224 by selectively patterning the first contact hole 240' and the second contact hole 240".

At this time, the active region of the active region forms a pixel portion first contact hole and a second contact hole exposing a predetermined region of the active region of the pixel portion in the passivation layer 215b.

As described above, the first and second contact holes 240 'and 240' 'according to the second embodiment of the present invention are formed on the outside of the gate electrode 221, 1 and the active layer 224 outside the first and second open regions A1 and A2 is located outside the second open regions A1 and A2. The second contact hole 240 'exposes the active layer 224 above the first open region A1 and the second contact hole 240' exposes the active layer 224 below the second open region A2. .

Next, as shown in FIGS. 8D and 9D, a second conductive layer is formed on the entire surface of the array substrate 210 on which the protective layer 215b is formed.

At this time, the second conductive layer may be formed of a low resistance opaque material such as aluminum, aluminum alloy, tungsten, copper, nickel, chromium, molybdenum, titanium, platinum, tantalum or the like to form data lines with the source / drain electrodes and the pixel portion source / Conductive materials may be used. The second conductive layer may be formed of a transparent conductive material such as indium-tin-oxide or indium-zinc-oxide, or may have a multilayer structure in which two or more conductive materials are stacked.

Then, the second conductive film is selectively patterned through a photolithography process (fourth mask process) to form source / drain regions (not shown) of the active layer 224 through the first and second contact holes 240 ' The source / drain electrodes 222 and 223 are formed.

In this case, the second conductive film is selectively patterned through the fourth mask process to form a pixel portion source / drain region electrically connected to a source / drain region of the pixel portion active layer through the pixel portion first and second contact holes Thereby forming an electrode.

At this time, the source / drain electrodes 222 and 223 are electrically connected to the first and second open regions A1 and A2 of the active layer 224, like the first and second contact holes 240 'and 240' The source electrode 222 is formed on the upper side of the first open region A1 and the drain electrode 223 is formed on the lower side of the second open region A2. .

Next, the array substrate 210 and the color filter substrate manufactured as described above are formed with a predetermined column spacer in the active region to maintain a cell gap therebetween, and a predetermined seal pattern is formed at the edge of the active region So that they are stuck together.

At this time, the color filter substrate is provided with a color filter composed of a plurality of sub-color filters, for example, colors of red, green and blue which selectively transmit only light of a specific wavelength band as color filter elements, A black matrix for separating light passing through the liquid crystal layer and blocking the light transmitted through the liquid crystal layer, and an overcoat layer formed on the color filter.

As described above, the present invention is also applicable to a case where the source electrode, the drain electrode, or the source / drain electrode overlap with the gate electrode, if necessary, and will be described in detail with reference to a third embodiment of the present invention.

FIGS. 10 to 12 are plan views illustrating, for example, layouts of a GIP circuit portion thin film transistor according to a third embodiment of the present invention. For example, the layouts of a GIP circuit portion thin film transistor to which two thin film transistors are connected are shown.

FIG. 10 shows a case where the source electrode and the gate electrode partially overlap each other, and FIG. 11 shows a case where the drain electrode and the gate electrode partially overlap each other. FIG. 12 illustrates a case where the source / For example.

The GIP circuit part thin film transistor according to the third embodiment of the present invention is substantially the same as the above-described second embodiment except that the source electrode, the drain electrode, or the source / It consists of components.

The GIP circuit part thin film transistor according to the third embodiment of the present invention has a coplanar structure in which a gate electrode and a source / drain electrode are located above the active layer, as in the first and second embodiments of the present invention .

As shown in the figure, the GIP circuit part thin film transistor according to the third embodiment of the present invention includes a buffer layer (not shown) formed on a predetermined substrate 310, an active layer 324 formed of an oxide semiconductor on the buffer layer, A gate electrode 321 formed on the active layer 324 with a gate electrode 321 therebetween, a protective film (not shown) formed on the gate electrode 321 and exposing a source / drain region of the active layer 324 And source / drain electrodes 322 and 323 which are electrically connected to the source / drain regions of the exposed active layer 324 through contact holes 340 'and 340'.

Although the GIP circuit part thin film transistor according to the third embodiment of the present invention includes two thin film transistors of a first thin film transistor and a second thin film transistor which are sequentially arranged along the gate electrode 321, The present invention is not limited thereto, and the present invention is applicable to a structure in which two or more thin film transistors are connected.

At this time, the contact holes 340 'and 340' 'include a first contact hole 340' for electrically connecting the source region of the exposed active layer 324 and the source electrode 322, and a second contact hole 340 ' And a second contact hole 340 " for electrically connecting the drain region of the drain electrode 324 and the drain electrode 323.

At this time, a predetermined region of the active layer 324 made of the oxide semiconductor is exposed when the gate electrode 321 and the gate insulating film are patterned, and the exposed region is reduced in resistance through plasma treatment or heat treatment, Source / drain regions are formed. At this time, the channel region of the active layer 324 is formed between the source region and the drain region of the active layer 324, that is, the unexposed oxide semiconductor under the gate electrode 321.

In the GIP circuit part thin film transistor according to the third embodiment of the present invention, since the active layer 324 is formed using the amorphous zinc oxide semiconductor in the same manner as the first and second embodiments of the present invention, And has the advantage of being applicable to a large area display while ensuring uniform characteristics while satisfying the constant current test condition.

In recent years, a great deal of attention and activity have been concentrated on transparent electronic circuits. Since the oxide thin film transistor in which the amorphous zinc oxide semiconductor material is applied to the active layer 324 has high mobility and small parasitic capacitance, There is an advantage that it can be used in the transparent electronic circuit.

In particular, the GIP circuit part thin film transistor according to the third embodiment of the present invention can form an amorphous IGZO semiconductor active layer 324 containing a heavy metal such as indium and gallium in the zinc oxide.

The GIP circuit part thin film transistor according to the third embodiment of the present invention having the above features has the same structure as the first and second embodiments of the present invention except that the gate electrode 321 and the source / The channel region of the oxide semiconductor is not damaged when the source / drain electrodes 322 and 323 are etched by applying the coplanar structure in which the electrodes 322 and 323 are located, thereby securing excellent device characteristics.

In addition, the GIP circuit portion thin film transistor according to the third embodiment of the present invention has a structure in which the gate electrode 321 is formed in a zigzag shape in order to apply the coplanar structure described above, And the region and the drain region are alternately arranged in a staggered manner.

In the GIP circuit portion thin film transistor according to the third embodiment of the present invention, the channel length of the thin film transistor is determined by the width of the gate electrode 321, while the plurality of channels are parallel to each other by the active layer 324 Respectively. Further, the source / drain regions for each thin film transistor are separated by the gate electrode 321. [

The active layer 324 according to the third embodiment of the present invention has a rectangular second region in which a channel is located and a rectangular region that protrudes from a central upper portion of the second region in the same manner as in the second embodiment of the present invention described above And a second region in the form of a first region.

That is, the active layer 324 according to the third embodiment of the present invention has a shape in which a part of the left and right oxide semiconductors on the upper part of the active layer 324 in which the first region is located is removed. However, the present invention is not limited thereto. The first region and the second region of the active layer 324 may be interchanged in position. In this case, the active layer 324 of the present invention may have a rectangular shape, The active layer 324 may have a shape in which a part of the left and right oxide semiconductors under the active layer 324 is removed.

At this time, a first open region in which a predetermined oxide semiconductor is removed is formed under the first region of the active layer 324 except for the left and right source regions, and a second open region is formed under the second region of the active layer 324 A second open region in which a predetermined oxide semiconductor is removed is formed in a state where the drain region is excluded.

At this time, the zigzag gate electrode 321 is formed in the second region of the active layer 324 in a direction perpendicular to the channel, that is, in the direction perpendicular to the longitudinal direction of the channel, 321 extend upward so that one end thereof deviates from the second region of the active layer 324 while the gate electrode 321 in a direction parallel to the channel, that is, in a direction parallel to the longitudinal direction of the channel, And are formed to be disposed in the first and second open regions of the active layer 324 respectively at the bottom.

The first and second contact holes 340 'and 340' 'according to the third embodiment of the present invention may be formed outside the gate electrode 321, specifically, the first and second contact holes 340' The first contact hole 340 'is located outside the second open region and exposes the active layer 324 outside the first and second open regions. That is, the first contact hole 340' And the second contact hole 340 " exposes the active layer 324 below the second open region.

Particularly, in the GIP circuit part thin film transistor according to the third embodiment of the present invention, the source electrode 322, the drain electrode 323, or the source / drain electrodes 322 and 323 are overlapped with the gate electrode 321, At this time, the active layer 324 may not exist between the overlapping source / drain electrodes 322 and 323 and the gate electrode 321.

10, the source electrode 322 extends toward the gate electrode 321 to form a first extended portion 322p, and the first extended portion 322p of the source electrode 322 is connected to the gate electrode 321. In this case, The drain electrode 323 extends to the gate electrode 321 and constitutes a second extended portion 323p in the case of FIG. 11, and the second extended portion 323p of the drain electrode 323 overlaps with a portion of the electrode 321, The portion 323p overlaps with a part of the gate electrode 321.

12, the source electrode 322 and the drain electrode 323 extend toward the gate electrode 321 to form a first extended portion 322p and a second extended portion 323p, The first extended portion 322p and the second extended portion 323p overlap with the gate electrode 321, respectively.

As described above, the present invention can be applied not only to liquid crystal display devices but also to other flat panel display devices manufactured using thin film transistors, for example, an organic light emitting display device (OLED) in which organic light emitting diodes . ≪ / RTI >

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

121, 221, 321: gate electrodes 122, 222, 322:
123, 223, 323: drain electrode 124, 224, 324: active layer
140, 240 ', 240 ", 340', 340": contact holes
322p, 323p: extension part

Claims (13)

An array substrate divided into an active area in which an image is displayed and a gate in panel (GIP) circuit part in which a gate driver is mounted;
An active layer formed of an oxide semiconductor on an array substrate of the GIP circuit portion;
A gate electrode formed in a zigzag form on the active layer via a gate insulating film;
A protective film formed on the array substrate on which the gate electrode is formed and including first and second contact holes exposing an active layer outside the gate electrode; And
And a source electrode and a drain electrode formed on the protective film and electrically connected to the source region and the drain region of the active layer through the first contact hole and the second contact hole,
Wherein the first contact hole and the second contact hole are located on the upper side and the lower side of the active layer outside the gate electrode and the source region and the drain region are alternately arranged between the gate electrodes in a zigzag form Flat panel display. The flat panel display of claim 1, wherein the active layer is made of an amorphous zinc oxide semiconductor. The flat panel display of claim 1, wherein a channel length of the thin film transistor is determined by a width of the gate electrode, and a source region and a drain region are separated by the gate electrode. The flat panel display of claim 1, wherein the plurality of channels are connected in parallel to each other by the active layer. The flat panel display as claimed in claim 1, wherein the active layer comprises a second region of a rectangular shape in which the channel is located, and a first region of a rectangular shape protruded from a central upper portion of the second region. The flat panel display as claimed in claim 5, wherein the active layer has a shape in which the left and right oxide semiconductors on the active layer on which the first region is located are removed in a rectangular shape as a whole. [7] The method of claim 6, wherein a first open region is formed under the first region of the active layer except for the right and left source regions, and a drain region is excluded from the left and right of the second region of the active layer Wherein a second open region is formed in which the oxide semiconductor is removed. 8. The semiconductor device according to claim 7, wherein the gate electrode of the zigzag shape extends upward so that one end of the gate electrode in a direction perpendicular to the longitudinal direction of the channel is out of the second region of the active layer, Direction and the horizontal direction of the gate electrode are formed so as to be arranged in the first and second open regions of the active layer at the upper and lower sides, respectively. The flat panel display as claimed in claim 7, wherein the first and second contact holes are located outside the first and second open regions to expose the active layer outside the first and second open regions. 10. The flat panel display of claim 9, wherein the first contact hole exposes an active layer above the first open region, and the second contact hole exposes an active layer below the second open region. . The flat panel display according to claim 1, wherein there is no overlap between the gate electrode, the source electrode, and the drain electrode. The flat panel display according to claim 1, wherein the source electrode, the drain electrode, or the source / drain electrode overlaps the gate electrode. 13. The semiconductor device according to claim 12, wherein the source electrode or the drain electrode or the source / drain electrode extend toward the gate electrode to form a first or second or first and second extending portions, And the first, second, and third extension portions overlap the gate electrode.

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