CN202421684U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
- Publication number
- CN202421684U CN202421684U CN2012200419793U CN201220041979U CN202421684U CN 202421684 U CN202421684 U CN 202421684U CN 2012200419793 U CN2012200419793 U CN 2012200419793U CN 201220041979 U CN201220041979 U CN 201220041979U CN 202421684 U CN202421684 U CN 202421684U
- Authority
- CN
- China
- Prior art keywords
- grid line
- line
- grid
- array base
- base palte
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The utility model discloses an array substrate and a display device, and is characterized in that grid lines, data lines, and multiple pixel units which are limited by the grid lines and the data lines, are formed on the array substrate, two rows of adjacent pixel units are taken as one group, each group of pixel units share one data line, and grid line outgoing lines are formed between two groups of adjacent pixel units; each grid line on the array substrate is electrically connected with one grid line outgoing line, and is connected to a grid drive signal through the grid line outgoing line. According to the array substrate provided by the utility model, an outer outgoing region of the grid lines is removed, the area of a frame is reduced, a structure of a backlight is simplified, and a design of the narrow frame is realized; by adopting the design of the utility model, the storage capacitance of a pixel electrode region is increased, so that a problem of poor display of a display screen is improved; in addition, the array substrate and the display device, provided by the utility model, have the advantages of reasonable and simple design, easy operation, convenience for mounting and dismounting, and capability of reducing production cost.
Description
Technical field
The utility model relates to the display technique field, relates in particular to a kind of array base palte and display device.
Background technology
At present; Thin Film Transistor-LCD (Thin Film Transistor-Liquid Crystal Display; Be called for short TFT-LCD) have characteristics such as volume is little, low in energy consumption, radiationless, manufacturing cost is relatively low, occupied leading position in current flat panel display market.Tft array substrate is one of vitals of LCD; Its structure is as shown in Figure 1; Mainly comprise substrate, be formed on gate electrode 41 and grid line 10 on the substrate, be formed on gate electrode 41 and the grid line 10 and cover the transparent gate insulation layer (not shown) of whole base plate as substrate; Be formed on semiconductor layer (not shown), the doped semiconductor layer (not shown) of gate electrode top and the source-drain electrode of forming by source electrode 42, drain electrode 43; Form the data line 20 with grid line 10 square crossings simultaneously, the passivation layer (not shown) covers whole base plate, above drain electrode 43, offers passivation layer via hole 44; Pixel electrode 30 is formed on pixel region, and pixel electrode 30 is connected with drain electrode 43 through passivation layer via hole 44.The gate electrode 41 that wherein is connected with grid line 10 is as the switch of active components and parts, the source electrode 42 that is connected with data line 20 and with drain electrode 43 that pixel electrode 30 is connected between form conducting channel, semiconductor layer is as active layer.
In order to reduce the manufacturing cost of TFT-LCD, also there is a kind of Thin Film Transistor-LCD of double grid type in the prior art.As shown in Figure 2, between two adjacent row pixel cells, be provided with two grid lines, i.e. first grid line 101 and second grid line 102.When second grid line 102 above being positioned at the capable pixel cell of N is opened, can be that the pixel of the even column in the capable pixel cell of N writes data through data line 20; When first grid line 101 below being positioned at the capable pixel cell of N is opened, can be that the pixel of the odd column in the capable pixel cell of N writes data through data line 20.Owing to can timesharing open with the odd number of pixels and the even number pixel of delegation's pixel cell; Therefore just can realize utilizing same data lines based on structure shown in Figure 2 is that two adjacent row pixels provide data-signal, thereby reduces the quantity of source electrode driver, the manufacturing cost of reduction TFT-LCD.
In the existing technical scheme, no matter be the traditional LCD or the LCD of double grid type, the extension line of grid need be drawn separately in specific grid outer lead zone, has taken the area of frame, to producing narrow edge frame product very big restriction is arranged.
The utility model content
To the above-mentioned technical matters that prior art exists, the utility model provides the array base palte and the display device of the narrow edge frame product of a kind of suitable making.
A kind of array base palte; The a plurality of pixel cells that on this array base palte, are formed with grid line and data line and limit said grid line and data line; With adjacent two row pixel cells is one group; Every group of shared same data line of pixel cell is formed with the grid line extension line between two groups of adjacent pixel cells; Every grid line on the said array base palte all electrically connects with a said grid line extension line, and inserts gate drive signal through said grid line extension line.
Said grid line extension line and said data line are made with layer.
Said grid line extension line and the parallel distribution of said data line.
Said grid line extension line and said grid line electrically connect through connection electrode in its space crossed position.
Said connection electrode and pixel electrode are made with layer; Said grid line is connected with said connection electrode through first via hole; Said grid line extension line is connected with said connection electrode through second via hole; Said grid line and said grid line extension line are through said first via hole, said second via hole and said connection electrode conducting.
The quantity of said first via hole is two, and the quantity of said second via hole is one.
Said first via hole is distributed in the both sides of said second via hole.
Said grid line extension line and said grid line electrically connect through via hole in its space crossed position.
The utility model also provides a kind of display device, comprises above-mentioned array base palte.
A kind of array base palte and the display device that adopt the utility model to provide have the following advantages:
The utility model is in narrow frame design, and main array substrate has carried out design alteration, on the same layer of original formation data line, forms the grid line extension line; Omitted the grid line extension line of prior art and made separately, drawn the zone, for narrow frame design provides prerequisite thereby removed original grid line; Simplified the structure of backlight; Reduce design difficulty, reduced production cost, be beneficial to dismounting; In addition, the utility model makes the MM CAP in pixel electrode district increase, and shows bad problem thereby improved display.
Description of drawings
Fig. 1 is the structural representation of prior art embodiment;
Fig. 2 is the structural representation of the Thin Film Transistor-LCD of prior art double grid type;
Fig. 3 is the structural representation of the utility model embodiment;
Fig. 4 is the section of structure of Fig. 3 in the A1-A direction;
Fig. 5 is that grid line and the grid line extension line side signal transmission of the utility model embodiment is to synoptic diagram;
Fig. 6 is the structural representation that the utility model embodiment contains many extension lines.
Embodiment
The utility model provides the array base palte and the display device of the narrow edge frame product of a kind of suitable making.
The TFT-LCD that the array base palte that the utility model provides is based on existing double grid type has done further improvement.Particularly; On this array base palte, be formed with grid line with data line, the grid line of mutual vertical and intersection and a plurality of pixel cells that data line limits; Grid line is used for to thin film transistor (TFT) unlatching or shutoff voltage being provided, and thin film transistor (TFT) is used for control data alignment pixel electrode provides data voltage, and the embodiment that the utility model provides is one group with adjacent two row pixel cells specifically; Every group of shared same data line of pixel cell is formed with the grid line extension line between two groups of adjacent pixel cells; Every grid line on the said array base palte all electrically connects with a said grid line extension line, and inserts gate drive signal through said grid line extension line.
Combine a kind of array base palte and the display device that accompanying drawing is introduced the utility model in detail to be provided with specific embodiment below:
As shown in Figure 3, be the structural representation of the utility model embodiment.On substrate, be formed with grid metal level, gate insulation layer, active layer, source leakage metal level, passivation layer and pixel electrode layer successively.Wherein, the grid metal level comprises the grid line 1 of patterning, the grid and the public electrode wire in TFT zone; Active layer comprises semiconductor layer or the semiconductor layer and the ohmic contact layer in TFT zone; Source/drain electrode that metal level comprises patterned data line 4 and TFT zone is leaked in the source; Pixel electrode layer comprises the pixel electrode 5 of patterning.In the utility model embodiment, said source is leaked metal level and is also comprised the grid line extension line made from layer with data line 42.
With adjacent two row pixel cells is one group, and every group of shared same data line 4 of pixel cell is formed with grid line extension line 2 between two groups of adjacent pixel cells; Every grid line 1 on the array base palte all electrically connects with a grid line extension line 2, and inserts gate drive signal through grid line extension line 2.
The implementation that grid line 1 and grid line extension line 2 electrically connect can have but be not limited to following two kinds:
One of which is formed with via hole 3 on the gate insulation layer between grid line 1 and the grid line extension line 2, grid line extension line 2 electrically connects through this via hole 3 in its space crossed position with grid line 1.
Its two, above grid line 1 and with pixel electrode 5, be provided with connection electrode 21 (with reference to Fig. 4) with the position of layer, grid line extension line 2 electrically connects through this connection electrode 21 in its space crossed position with grid line 1.Though above-mentioned connection electrode 21 is made with layer with pixel electrode 5, can not be connected with pixel electrode 5 to avoid grid line and pixel electrode short circuit.
In Fig. 4, among Fig. 3 along A
1The sectional view of-A direction exemplarily respectively is provided with one first via hole 31 in second via hole, 32 both sides; Certainly, in the implementation procedure of reality, the position of first via hole and quantity can be adjusted as required, such as, only the side at second via hole is provided with first via hole.
If adopt above-mentioned first kind of implementation, then need increase the mask lithography technology that once forms grid insulating layer through hole, above-mentioned second kind of implementation then need not to increase new technological process; Therefore, preferably adopt second kind of implementation among the utility model embodiment, promptly be equipped with first via hole 31 in the both sides of second via hole 32.
On substrate 7, be formed with grid line 1, gate insulation layer, semiconductor layer 8 and grid line extension line 2 successively, above grid line extension line 2, also be formed with passivation layer 6 and connection electrode; Grid line extension line 2 is connected with connection electrode 21 through second via hole 32 and makes grid line extension line 2 and connection electrode 21 conductings; Grid line 2 is connected with connection electrode 21 through first via hole 31 and makes grid line 1 and also conducting of connection electrode 21, thereby through first via hole 31 and second via hole 32 grid line 1 and grid line extension line 2 is electrically connected.
As shown in Figure 5; Be connect with the grid line extension line transmission direction synoptic diagram of signal after the conducting of the utility model embodiment grid line; Because grid line of the prior art can only have a grid outer lead zone thereby increased at the grid outer lead conducted signal that is formed on the substrate, carries out narrow frame design thereby limited product; In the specific embodiment that the utility model provides; A plurality of pixel cells that grid line that vertically also intersects each other and data line limit, grid line is used for to thin film transistor (TFT) unlatching or shutoff voltage being provided, and thin film transistor (TFT) is used for control data alignment pixel electrode provides data voltage; With adjacent two row pixel cells is one group, and every group of shared same data line of pixel cell is formed with the grid line extension line between two groups of adjacent pixel cells; Every grid line on the said array base palte all electrically connects with a said grid line extension line, and inserts gate drive signal through said grid line extension line.Every grid line is connected with a grid line extension line; Make signal and to transfer signals to grid along the transmission of the direction of grid line extension line; Thereby transfer gate drive signal to, saved grid outer lead zone, thereby bigger space is provided for designing narrow edge frame product; In addition, the design of the utility model makes the MM CAP in pixel electrode district increase, and the bad problem of demonstration that has reduced display occurs.
As shown in Figure 6; Be many grid line extension lines of the utility model embodiment structural representation, mutual vertical and the grid line 51 of intersection and a plurality of pixel cells that data line 53 limits, grid line 51 is used for to thin film transistor (TFT) unlatching or shutoff voltage being provided; Thin film transistor (TFT) is used for control data line 53 provides data voltage to pixel electrode; With adjacent two row pixel cells is one group, and every group of shared same data line 53 of pixel cell is formed with grid line extension line 52 between two groups of adjacent pixel cells; Every grid line 51 is connected with a grid line extension line 52; Make signal to be transferred to grid through grid line 51 along the direction transmission of grid line extension line 52 and with signal; Thereby transfer gate drive signal to; Saved grid line outer lead zone in the prior art, thereby bigger space is provided for designing narrow edge frame product.
The array base palte that provides in the foregoing description goes for but is not limited to TFT-LCD; In addition, can also be applied to display technique fields such as OLED (Organic Light Emitting Diode, Organic Light Emitting Diode), e-book certainly.
The utility model embodiment also provides a kind of display device, comprises the display device of liquid crystal indicator and other types.Wherein, liquid crystal indicator can be liquid crystal panel, LCD TV, mobile phone, LCD etc., and it comprises the array base palte in color membrane substrates and the foregoing description.Above-mentioned other types display device, such as Electronic Paper, it does not comprise color membrane substrates, but comprises the array base palte in the foregoing description.
Obviously, those skilled in the art can carry out various changes and modification to the utility model and not break away from the spirit and the scope of the utility model.Like this, belong within the scope of the utility model claim and equivalent technologies thereof if these of the utility model are revised with modification, then the utility model also is intended to comprise these changes and modification interior.
Claims (9)
1. array base palte; The a plurality of pixel cells that on this array base palte, are formed with grid line and data line and limit said grid line and data line; With adjacent two row pixel cells is one group; Every group of shared same data line of pixel cell is characterized in that, between two groups of adjacent pixel cells, is formed with the grid line extension line; Every grid line on the said array base palte all electrically connects with a said grid line extension line, and inserts gate drive signal through said grid line extension line.
2. array base palte as claimed in claim 1 is characterized in that, said grid line extension line and said data line are made with layer.
3. array base palte as claimed in claim 2 is characterized in that, said grid line extension line and the parallel distribution of said data line.
4. array base palte as claimed in claim 3 is characterized in that, said grid line extension line and said grid line electrically connect through connection electrode in its space crossed position.
5. array base palte as claimed in claim 4 is characterized in that, said connection electrode and pixel electrode are made with layer;
Said grid line is connected with said connection electrode through first via hole; Said grid line extension line is connected with said connection electrode through second via hole; Said grid line and said grid line extension line are through said first via hole, said second via hole and said connection electrode conducting.
6. array base palte as claimed in claim 5 is characterized in that, the quantity of said first via hole is two, and the quantity of said second via hole is one.
7. array base palte as claimed in claim 6 is characterized in that said first via hole is distributed in the both sides of said second via hole.
8. array base palte as claimed in claim 3 is characterized in that, said grid line extension line and said grid line electrically connect through via hole in its space crossed position.
9. a display device is characterized in that, comprises each described array base palte among the claim 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012200419793U CN202421684U (en) | 2012-02-09 | 2012-02-09 | Array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012200419793U CN202421684U (en) | 2012-02-09 | 2012-02-09 | Array substrate and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202421684U true CN202421684U (en) | 2012-09-05 |
Family
ID=46746430
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012200419793U Expired - Lifetime CN202421684U (en) | 2012-02-09 | 2012-02-09 | Array substrate and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN202421684U (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104253147A (en) * | 2014-09-18 | 2014-12-31 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method and display equipment thereof |
| WO2016179972A1 (en) * | 2015-05-11 | 2016-11-17 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal display panel, and display device |
| CN107342299A (en) * | 2017-08-30 | 2017-11-10 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device and preparation method thereof |
| CN109119028A (en) * | 2018-09-07 | 2019-01-01 | 武汉华星光电半导体显示技术有限公司 | AMOLED display panel and corresponding display device |
| CN110673414A (en) * | 2019-09-25 | 2020-01-10 | 深圳市华星光电技术有限公司 | Array substrate and preparation method thereof |
| US11187950B2 (en) | 2019-09-25 | 2021-11-30 | Tcl China Star Optoelectronics Technology Co., Ltd. | Array substrate and method of manufacturing same |
-
2012
- 2012-02-09 CN CN2012200419793U patent/CN202421684U/en not_active Expired - Lifetime
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016041283A1 (en) * | 2014-09-18 | 2016-03-24 | 京东方科技集团股份有限公司 | Array substrate and preparation method therefor, display device thereof |
| CN104253147B (en) * | 2014-09-18 | 2017-03-15 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
| US9679520B2 (en) | 2014-09-18 | 2017-06-13 | Boe Technology Group Co., Ltd. | Array substrate, method of producing the same, and display apparatus |
| CN104253147A (en) * | 2014-09-18 | 2014-12-31 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method and display equipment thereof |
| WO2016179972A1 (en) * | 2015-05-11 | 2016-11-17 | 京东方科技集团股份有限公司 | Array substrate, liquid crystal display panel, and display device |
| US10629629B2 (en) | 2017-08-30 | 2020-04-21 | Boe Technology Group Co., Ltd. | Array substrate and method for manufacturing the same, display device |
| CN107342299A (en) * | 2017-08-30 | 2017-11-10 | 京东方科技集团股份有限公司 | Array base palte and preparation method thereof, display device and preparation method thereof |
| CN109119028A (en) * | 2018-09-07 | 2019-01-01 | 武汉华星光电半导体显示技术有限公司 | AMOLED display panel and corresponding display device |
| CN109119028B (en) * | 2018-09-07 | 2020-04-28 | 武汉华星光电半导体显示技术有限公司 | AMOLED display panel and corresponding display device |
| US11107871B2 (en) | 2018-09-07 | 2021-08-31 | Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | AMOLED display panel and corresponding display device |
| CN110673414A (en) * | 2019-09-25 | 2020-01-10 | 深圳市华星光电技术有限公司 | Array substrate and preparation method thereof |
| WO2021056732A1 (en) * | 2019-09-25 | 2021-04-01 | Tcl华星光电技术有限公司 | Array substrate and preparation method therefor |
| US11187950B2 (en) | 2019-09-25 | 2021-11-30 | Tcl China Star Optoelectronics Technology Co., Ltd. | Array substrate and method of manufacturing same |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103268878B (en) | The manufacture method of tft array substrate, tft array substrate and display unit | |
| CN202421684U (en) | Array substrate and display device | |
| US10168593B2 (en) | Liquid crystal display panel having dual capacitors connected in parallel to shift register unit and array substrate thereof | |
| CN101833200B (en) | Horizontal electric field type liquid crystal display device and manufacturing method thereof | |
| CN202159214U (en) | Array substrate and liquid crystal display | |
| CN103472647A (en) | Array substrate, liquid crystal display panel and display device | |
| CN105185791A (en) | Array substrate and manufacturing method thereof and display device | |
| CN103268045A (en) | TFT (thin film transistor) array substrate, and production method thereof and liquid crystal display device | |
| CN102193253A (en) | Liquid crystal display panel | |
| CN102981335A (en) | Pixel unit structure, array substrate and display device | |
| CN103676369A (en) | Array substrate, array substrate manufacturing method and display device | |
| CN103439840A (en) | Array substrate, display device and method for manufacturing array substrate | |
| CN101441380A (en) | LCD device of multi-domain vertical orientation mode | |
| CN104049430A (en) | Array substrate, display device and manufacturing method of array substrate | |
| CN109521596B (en) | Array substrate, display panel and control method of display panel | |
| CN103345092A (en) | Array substrate, manufacturing method thereof and display device | |
| CN103235452A (en) | Array substrate and display device | |
| CN102929060A (en) | Array substrate, fabrication method of array substrate, and display device | |
| CN104730781A (en) | ADS array substrate, manufacturing method thereof, and display device comprising same | |
| CN104898342A (en) | Array substrate mother plate and manufacture method thereof | |
| CN102446913A (en) | Array baseplate and manufacturing method thereof and liquid crystal display | |
| CN206039107U (en) | Display panel and display apparatus | |
| CN203232230U (en) | Array substrate and display device | |
| CN103926768A (en) | Array substrate, display panel and display device | |
| CN203299777U (en) | Embedded type touch screen and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: JINGDONGFANG SCIENCE AND TECHNOLOGY GROUP CO., LTD Free format text: FORMER OWNER: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY CO., LTD. Effective date: 20150707 Owner name: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY Effective date: 20150707 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20150707 Address after: 100015 Jiuxianqiao Road, Beijing, No. 10, No. Patentee after: BOE Technology Group Co., Ltd. Patentee after: Beijing BOE Photoelectricity Science & Technology Co., Ltd. Address before: 100176 Beijing city in Western Daxing District economic and Technological Development Zone, Road No. 8 Patentee before: Beijing BOE Photoelectricity Science & Technology Co., Ltd. |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20120905 |