CN102937768A - Array substrate and manufacture method and display device thereof - Google Patents

Abstract

The invention provides an array substrate and a manufacture method and a display device thereof. The array substrate comprises a plurality of grid lines, a plurality of data lines and pixel regions, wherein each pixel region is defined by every two mutually-adjacent gird lines and every two mutually-adjacent data lines, the pixel regions are provided with common electrodes, pixel electrodes and thin film transistors. The array substrate further comprises common electrode lines, wherein the common electrode lines and the data lines are located on the same layer and are not intersected. Passivation layers are arranged on the common electrode lines, the common electrode lines are connected with the common electrodes through passing holes formed on the passivation layers, and the common electrodes are not overlapped with the data lines. By means of the scheme, the overlap capacitance between the data lines and the common electrode lines can be avoided, and accordingly a Greenish phenomenon can be greatly reduced under the driving of high frequency.

Description

A kind of array base palte and preparation method thereof and display device

Technical field

The present invention relates to field of liquid crystal display, refer to especially a kind of array base palte and preparation method thereof and display device.

Background technology

As shown in Figure 1, planimetric map for array base palte in the prior art, array base palte comprises: the grid line 10 on the underlay substrate, data line 20 with described grid line 10 homeotropic alignments, grid line 10 and data line 20 limit pixel region, comprise the pixel electrode 40, block public electrode wire 30 and the thin film transistor (TFT) that are arranged side by side in the pixel region; The long limit of the pixel region of the array base palte of this kind structure is data line 20, and minor face is grid line 10, and described public electrode wire 30 is parallel to the minor face of pixel region and is positioned at a side away from thin film transistor (TFT); There is overlap capacitance between the public electrode wire 30 of data line 40 and its below.

Present large scale TV(TV) product and 3D product are the development trends that present TV is made the field.Yet want to realize the smooth exploitation of large scale product and 3D product, be increased to 120Hz or even 240Hz such as the product driving frequency from 60Hz.

Yet the array base palte that said structure is shown in Figure 1, because the existence of the overlap capacitance between data line 20 and the public electrode wire 30, when high-frequency drives, can cause that the voltage of public electrode is influenced, thereby it is green attached to make the picture of product produce Greenish() problem.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of array base palte and preparation method thereof and display device, avoids the overlap capacitance between data line and the public electrode wire, thereby can under high-frequency drives, greatly reduce the Greenish phenomenon.

Embodiments of the invention provide a kind of array base palte, comprise: many grid lines, many data lines, per two grid lines adjacent one another are and per two pixel regions that data line adjacent one another are limits, wherein said pixel region is provided with public electrode, pixel electrode and thin film transistor (TFT); Also comprise with described data line and be in the same layer public electrode wire, wherein said public electrode wire and described data line are non-intersect, be provided with passivation layer at described public electrode wire, wherein said public electrode wire is connected with described public electrode by the via hole that is formed on the described passivation layer, and described public electrode and described data line are not overlapping.

Wherein, described grid line is vertical overlapping with described data line, and described pixel region is rectangle, and described data line consists of the minor face of described pixel region, and described grid line consists of the long limit of described pixel region.

Wherein, described grid line overlapping position vertical with described data line has thin film transistor (TFT), and described data line is connected with described pixel electrode by described thin film transistor (TFT).

Wherein, described pixel electrode is narrow slit structure.

Wherein, the narrow slit structure of described pixel electrode has crossover sites, and the projection of described public electrode wire on the layer of described pixel electrode place drops on the described crossover sites.

Wherein, described public electrode has the slit that structure that the slit with described pixel electrode is complementary and the projection of described public electrode on described pixel electrode can cover described pixel electrode.

Wherein, described public electrode can also cover near the subregion the slit of described pixel electrode in the projection on the described pixel electrode.

Embodiments of the invention also provide a kind of method for making of array base palte, comprising:

One underlay substrate is provided;

Form pixel electrode at described underlay substrate;

Be formed with on the underlay substrate of described pixel electrode, forming grid line;

Form gate insulation layer at the underlay substrate that is formed with described grid line;

Form data line and public electrode wire at the underlay substrate that is being formed with described gate insulation layer, and described public electrode wire and described data line are non-intersect;

Via hole on the underlay substrate formation passivation layer that is formed with described data line and public electrode wire and described passivation layer;

Form public electrode at the underlay substrate that is formed with described passivation layer, described public electrode is connected with described public electrode wire by the via hole on the described passivation layer.

Embodiments of the invention also provide a kind of display device, comprise array base palte as described above.

The beneficial effect of technique scheme of the present invention is as follows:

In the such scheme, be in same layer by public electrode wire and described data line, and public electrode wire and described data line are non-intersect, avoid the generation of the overlap capacitance between data line and the public electrode wire, thereby can be under high-frequency drives, effectively avoid data line voltage on the impact of public electrode voltages signal, greatly reduce the generation of Greenish phenomenon.

Description of drawings

Fig. 1 is the floor map of array base palte in the prior art;

Fig. 2 is the floor map of array base palte of the present invention;

Fig. 3-Fig. 7 is the manufacturing process schematic diagram of array base palte of the present invention;

Fig. 8 is the change in voltage schematic diagram of the public electrode of array base palte of the present invention.

Embodiment

For making the technical problem to be solved in the present invention, technical scheme and advantage clearer, be described in detail below in conjunction with the accompanying drawings and the specific embodiments.

As shown in Figure 2, embodiments of the invention provide a kind of array base palte, comprise: the underlay substrate (not shown), some grid lines 1, some data lines 2, per two grid lines adjacent one another are 1 and per two pixel regions that data line adjacent one another are 2 limits, wherein said pixel region is provided with public electrode 7, pixel electrode 4 and thin film transistor (TFT) 5; Also comprise the public electrode wire 3 that is in same layer with described data line 2, wherein said public electrode wire 3 and described data line 2 are non-intersect, be provided with passivation layer at described public electrode wire 3, wherein said public electrode wire 3 is connected with described public electrode 7 by the via hole that is formed on the described passivation layer, and described public electrode 7 is not overlapping with described data line 2.

This embodiment of the present invention is by being arranged to public electrode 7 and public electrode wire 3 and data line 2 non-intersect folded structures, avoid the generation of the overlap capacitance between data line 2 and public electrode wire 3 and the public electrode 7, thereby can be under high-frequency drives, effectively avoid data line voltage on the impact of public electrode voltages signal, greatly reduce the incidence of Greenish phenomenon.

In the above-described embodiments, the grid line 1 on the described underlay substrate is vertical overlapping with data line 2, and limits pixel region; The plane of this pixel region is rectangle, and data line 2 consists of the minor face of described pixel region, and grid line 1 consists of the long limit of described pixel region.

Be provided with pixel electrode 4 in the described pixel region, this pixel electrode 4 is to utilize the ground floor ITO that deposits at underlay substrate to make, and this pixel electrode 4 is made into narrow slit structure.

In addition, described grid line 1 has thin film transistor (TFT) (TFT) 5 with described data line 2 vertical overlapping positions, and described data line 2 is connected with described pixel electrode 4 by described thin film transistor (TFT) 5.

Be positioned at the passivation layer above the described data line 2 and be positioned at public electrode 7 above the described passivation layer also being provided with on the described array base palte, described public electrode 7 is connected with described public electrode wire 3 by the via hole 6 on the described passivation layer.

In the above-described embodiments, described public electrode 7 has the slit that structure that the slit with described pixel electrode 4 is complementary and the projection of described public electrode 7 on described pixel electrode 4 place layers can cover described pixel electrode 4, perhaps further can cover near the subregion the slit.When said structure can guarantee to form fringe field, consequent memory capacitance reduced greatly, was conducive to the high-frequency drive product and reached the charge rate requirement.But described public electrode 7 also can be other for example bar shaped of shape.

When a certain row are opened on the display panel, voltage signal is converted into ceiling voltage by 0V on data line 2, charge by 5 pairs of pixel electrodes 4 of TFT, because as shown in Figure 8, the voltage of public electrode wire 3 can produce the process that falls after rise gradually again after the saltus step, and △ Vcom is public electrode wire 3(or public electrode) voltage variety, this value is higher, on the more difficult recovery of impact of the voltage of public electrode wire 3, thereby will produce the Greenish phenomenon.

Corresponding single dot structure, data line 2 can be presented as the impact of the voltage signal of public electrode wire 3:

$\mathrm{\ΔVcom}=a\×\frac{\mathrm{Cdc}+\mathrm{Clateral}}{\mathrm{\ΣC}\_\mathrm{dot}}\×\mathrm{\ΔVdata}$

Wherein, a is constant coefficient, and Cdc is the overlap capacitance between data line and public electrode wire, and Clateral is the side direction electric capacity between the public electrode 7 on data line 2 and right side, and Δ Vdata is the voltage variety of data line, and C_dot is the total capacitance of a sub-pix.

Hence one can see that; When Cdc and Clateral reduction, just can reduce the variation of the voltage signal of public electrode; In the above embodiments of the present invention, owing to public electrode wire 3 and data line 2 same layer making and non-intersect with data line 2, therefore, having avoided the existence of the two overlap capacitance Cdc;

In addition, because public electrode 7 is prepared into the structure consistent with the slit of described pixel electrode 4, compare with traditional before dot structure, because data line 2 designs in the minor face position, therefore the side direction capacitance of data line and public electrode 7 reduces greatly, has therefore effectively avoided the generation of Greenish phenomenon; And effectively reduced the storage capacitance value with pixel electrode, so that under the high-frequency drive condition, product can reach the charge rate requirement; And other design with public electrode 7 of similar functions also can realize.

Such as Fig. 3-shown in Figure 7, embodiments of the invention also provide a kind of method for making of array base palte, comprising: a underlay substrate (not shown this underlay substrate) is provided; Form pixel electrode 4(as shown in Figure 3 at underlay substrate, concrete, when underlay substrate deposition ground floor tin indium oxide ITO, through behind the exposure imaging, obtain pixel electrode as shown in Figure 3); On the underlay substrate that is formed with pixel electrode 4, form grid line 1(as shown in Figure 4); Form the gate insulation layer (not shown) at the underlay substrate that is formed with grid line 1; Form data line 2 and public electrode wire 3 at the underlay substrate that is formed with gate insulation layer, and public electrode wire 3 and described data line 2 are non-intersect (as shown in Figure 5, can also be simultaneously at grid line overlapping position forming film transistor 5 vertical with described data line in this step, data line is connected with pixel electrode 4 by thin film transistor (TFT) 5); Via hole 6(on the underlay substrate formation passivation layer that is formed with data line 2 and public electrode wire 3 and described passivation layer as shown in Figure 6); Form public electrode 7 at the underlay substrate that is formed with passivation layer, described public electrode 7 is connected (as shown in Figure 7) by the via hole 6 on the passivation layer with public electrode wire 3.

The array base palte that the method embodiment forms is array base palte as shown in Figure 2 above, equally by public electrode 7 and public electrode wire 3 are arranged to and data line 2 non-intersect folded structures, avoid the generation of the overlap capacitance between data line 2 and public electrode wire 3 and the public electrode 7, thereby can be under high-frequency drives, effectively avoid data line voltage on the impact of public electrode voltages signal, greatly reduce the incidence of Greenish phenomenon.

The present invention also provides a kind of display device that comprises above-mentioned array base palte shown in Figure 2.This display device can be: any product or parts with Presentation Function such as LCD TV, liquid crystal display, mobile phone, panel computer.

The above is preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from principle of the present invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (9)

1. array base palte, comprise that many grid lines, many data lines, per two grid lines adjacent one another are and per two data lines adjacent one another are limit pixel region, wherein said pixel region is provided with public electrode, pixel electrode and thin film transistor (TFT), it is characterized in that

Also comprise with described data line and be in the same layer public electrode wire, wherein said public electrode wire and described data line are non-intersect, be provided with passivation layer at described public electrode wire, wherein said public electrode wire is connected with described public electrode by the via hole that is formed on the described passivation layer, and described public electrode and described data line are not overlapping.

2. array base palte according to claim 1 is characterized in that, described grid line is vertical overlapping with described data line, and described pixel region is rectangle, and described data line consists of the minor face of described pixel region, and described grid line consists of the long limit of described pixel region.

3. array base palte according to claim 2 is characterized in that, described grid line overlapping position vertical with described data line has thin film transistor (TFT), and described data line is connected with described pixel electrode by described thin film transistor (TFT).

4. array base palte according to claim 2 is characterized in that, described pixel electrode is narrow slit structure.

5. array base palte according to claim 4 is characterized in that, the narrow slit structure of described pixel electrode has crossover sites, and the projection of described public electrode wire on the layer of described pixel electrode place drops on the described crossover sites.

6. array base palte according to claim 4 is characterized in that, described public electrode has the slit that structure that the slit with described pixel electrode is complementary and the projection of described public electrode on described pixel electrode can cover described pixel electrode.

7. array base palte according to claim 6 is characterized in that, described public electrode can also cover near the subregion the slit of described pixel electrode in the projection on the described pixel electrode.

8. the method for making of an array base palte is characterized in that, comprising:

One underlay substrate is provided;

Form pixel electrode at described underlay substrate;

Be formed with on the underlay substrate of described pixel electrode, forming grid line;

Form gate insulation layer at the underlay substrate that is formed with described grid line;

Form data line and public electrode wire at the underlay substrate that is being formed with described gate insulation layer, and described public electrode wire and described data line are non-intersect;

Via hole on the underlay substrate formation passivation layer that is formed with described data line and public electrode wire and described passivation layer;

Form public electrode at the underlay substrate that is formed with described passivation layer, described public electrode is connected with described public electrode wire by the via hole on the described passivation layer.

9. a display device is characterized in that, comprises each described array base palte among the claim 1-7.

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