CN202712184U - Array substrate and display apparatus - Google Patents
Array substrate and display apparatus Download PDFInfo
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- CN202712184U CN202712184U CN 201220364218 CN201220364218U CN202712184U CN 202712184 U CN202712184 U CN 202712184U CN 201220364218 CN201220364218 CN 201220364218 CN 201220364218 U CN201220364218 U CN 201220364218U CN 202712184 U CN202712184 U CN 202712184U
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- conductive barrier
- layer
- array base
- passivation layer
- base palte
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Abstract
The utility model discloses an array substrate and a display apparatus. The array substrate comprises a data line layer which includes a plurality of data lines, a conductive barrier layer which includes a plurality of conductive barrier portions and is positioned above the data line layer, a passivation layer which is positioned above the conductive barrier layer, and a transparent conductive layer which is positioned above the passivation layer. Above each data line, the passivation layer s provided with a via hole; the conductive barrier portions are positioned below the via hole and are in contact with corresponding data lines; and the transparent conductive layer is connected with corresponding conductive barrier portions through the via hole. With the adoption of the array substrate, when the via hole is formed by etching the passivation layer, the conductive barrier portions can effectively protect metal of the data lines from etching, and thus a product qualified rate is substantially improved.
Description
Technical field
The utility model relates to tft liquid crystal Display Technique field, particularly relates to a kind of array base palte and a kind of display unit.
Background technology
In panel display apparatus, Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, be called for short TFT-LCD) have that volume is little, low in energy consumption, manufacturing cost is relatively low and the characteristics such as radiationless, occupied leading position in current flat panel display market.
At present, the display mode of TFT-LCD mainly contains TN(Twisted Nematic, twisted-nematic) pattern, VA(Vertical Alignment, vertical orientated) pattern, IPS(In-Plane-Switching, the in-plane conversion) pattern and AD-SDS(ADvanced Super Dimension Switch, a senior super dimension switch technology is called for short ADS) pattern etc.
Wherein, the electric field that the electric field that produces by gap electrode edge in the same plane based on the display of ADS pattern and gap electrode layer and plate electrode interlayer produce forms multi-dimensional electric field, make in the liquid crystal cell between gap electrode, all aligned liquid-crystal molecules can both produce rotation directly over the electrode, thereby improved the liquid crystal operating efficiency and increased light transmission efficiency.A senior super dimension switch technology can improve the picture quality of TFT-LCD product, has high-resolution, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, without advantages such as water of compaction ripples (push Mura).
As shown in Figure 1, take the TFT-LCD array base palte of existing ADS pattern as example, its structure comprises: glass substrate 10, be formed at grid line layer (comprising grid 11) on the glass substrate 10 successively, gate insulator 12, active layer 13, data line layer (comprising source electrode 14, drain electrode 15), the first passivation layer 16, pixel electrode 17(is plate electrode), the second passivation layer 18 and public electrode 19(are gap electrode), wherein, the via hole 21 that passes on the first passivation layer 16 of pixel electrode 17 15 is connected with drain electrode.
In the prior art, the via hole that forms on the first passivation layer generally includes following steps: apply photoresist at the first passivation layer; Substrate behind the coating photoresist is exposed, develops, removed the photoresist (cross hole site photoresist in addition and form etching protection mask) of hole site; Carry out etching to crossing the hole site, form via hole; Photoresist residual on the substrate is peeled off.
The defective that prior art exists is, because the thinner thickness (usually between 1 ~ 3 micron) of the first passivation layer, thickness among the figure only is for convenient mapping, schematic thickness, when etching was carried out in the mistake hole site, production technology is difficult control, very easily etches away the part or all of metal of via hole below, cause overetch, finally cause product defects.
The utility model content
The purpose of this utility model provides a kind of array base palte and a kind of display unit, in order to solve the difficult control of the via etch technique that exists in the prior art, easily causes overetch, causes the technical problem of product defects.
The utility model array base palte, comprise: the data line layer that comprises many data wires, be positioned on the described data line layer, comprise the electrically conductive barrier of a plurality of conductive barrier section, be positioned at the passivation layer on the described electrically conductive barrier, and be positioned at transparency conducting layer on the described passivation layer, wherein, above each bar data wire:
Be provided with via hole on the described passivation layer;
Described conductive barrier section is positioned at the via hole below, and with corresponding data wire contact;
Described transparency conducting layer connects with corresponding conductive barrier section by via hole.
Preferably, described passivation layer material is non-photosensitive type resin.
Preferably, described conductive barrier section is identical with the transparency conducting layer material.
Better, described conductive barrier section material is tin indium oxide.
Preferably, above each bar data wire, described data wire corresponding to described conductive barrier section's covering.
Better, described data wire comprises source electrode and drain electrode, described drain electrode corresponding to described conductive barrier section's covering.
The utility model display unit comprises the described array base palte of aforementioned arbitrary technical scheme.
In the utility model array base palte because described conductive barrier section is positioned at the via hole below, and with corresponding data wire contact; therefore; when passivation layer being carried out etching formation via hole, conductive barrier section effectively protected data line layer metal is not etched away, and has greatly improved the qualification rate of product.
Description of drawings
Fig. 1 is the TFT-LCD array base-plate structure schematic diagram of existing ADS pattern;
Fig. 2 is the utility model array base palte the first example structure schematic diagram;
Fig. 3 is the utility model array base palte the second example structure schematic diagram;
Fig. 4 is for making the method flow schematic diagram of the utility model array base palte.
Reference numeral:
10-glass substrate 11-grid
12-gate insulator 13-active layer
14-source electrode 15-drain electrode
16-the first passivation layer 17-pixel electrode
18-the second passivation layer 19-public electrode
20-transparency carrier 30-conductive barrier section
21-via hole 22-data wire
23-passivation layer 24-transparency conducting layer
25-the second transparency conducting layer
Embodiment
In order to solve the difficult control of the via etch technique that exists in the prior art, easily cause overetch, cause the technical problem of product defects, the utility model embodiment provides a kind of array base palte and a kind of display unit.
As shown in Figure 2, the utility model array base palte, comprise: the data line layer that comprises many data wires 22, be positioned on the described data line layer, comprise the electrically conductive barrier of a plurality of conductive barrier section 30, be positioned at the passivation layer 23 on the described electrically conductive barrier, and be positioned at transparency conducting layer 24 on the described passivation layer 23, wherein, above each bar data wire 22:
Be provided with via hole 21 on the described passivation layer 23;
Described conductive barrier section 30 is positioned at via hole 21 belows, and with corresponding data wire 22 contacts;
Described transparency conducting layer 24 by via hole 21(namely part be deposited into via hole 21) with corresponding conductive barrier section 30 connections.
In the utility model embodiment, described data line layer refers to the layer structure that many data wires consist of, and in each pixel cell of array base palte, described data wire 22 comprises source electrode 14 and drain electrode 15, i.e. data wire 22 and source electrode 14 and drain electrode 15 is structure as a whole.The material of data line layer can be the monofilm of aluminium neodymium alloy (AlNd), aluminium (Al), copper (Cu), molybdenum (Mo), molybdenum and tungsten alloy (MoW) or chromium (Cr), the composite membrane that also can consist of for these metal material combination in any.
Described array base palte comprises transparency carrier 20, on transparency carrier 20, can further comprise: grid line layer, gate insulator 12, active layer 13 etc.Described array base palte can be top gate type, also can be bottom gate type, bottom gate type array base palte as shown in Figure 2, its structure is specially: grid line layer (grid line of grid line layer comprises grid 11 in each pixel cell) is formed on the transparency carrier 20, gate insulator 12 is formed on the grid line layer, active layer 13 is formed on the gate insulator 12, data line layer is formed on the active layer 13, electrically conductive barrier is formed on the data line layer (concrete, conductive barrier section 30 is formed on the drain electrode 15), passivation layer 23 covers whole substrate and be formed with via hole 21 above conductive barrier section 30, transparency conducting layer 24 parts are deposited into via hole 21 and are connected with conductive barrier section 30, and then can conduct electricity and be connected with drain electrode 15.
Via hole described in the utility model is not limited to position shown in Figure 2, in the signal guidance district of substrate periphery, equally need to be on passivation layer the etching via hole, at this moment, be positioned at this regional conductive barrier section effectively protected data line metal be not etched away.
Array base palte described in the utility model can be TN pattern, VA pattern, IPS pattern or ADS pattern etc.Please continue with reference to shown in Figure 2, the array base palte of ADS pattern also further comprises: the passivation layer 23 described in the utility model the second passivation layer 18(this moment that is formed on the transparency conducting layer 24 is the first passivation layer), and the transparency conducting layer 24 described in the utility model the second transparency conducting layer 25(this moment that is formed at the slit-shaped on the second passivation layer 18 is the first transparency conducting layer); Wherein, the first transparency conducting layer can be pixel electrode, and then the second transparency conducting layer is public electrode; Can also be, the first transparency conducting layer be public electrode, and then the second transparency conducting layer is pixel electrode.
In the utility model array base palte because described conductive barrier section is positioned at the via hole below, and with corresponding data wire contact; therefore; when passivation layer being carried out etching formation via hole, conductive barrier section effectively protected data line layer metal is not etched away, and has greatly improved the qualification rate of product.
Preferably, described passivation layer 23 materials are non-photosensitive type resin.With photosensitive type resin-phase ratio, non-photosensitive type resin has following advantage: the dielectric constant of non-photosensitive type resin material is about 3.0, is lower than the dielectric constant (being about 4.0) of photosensitive type resin material; The transmitance of non-photosensitive type resin material is near 100%, far above the transmitance (being about 93%) of photosensitive type resin material; The curing temperature of non-photosensitive type resin material is higher, be about 400 degree, and the gas effusion is almost nil, and the curing temperature of photosensitive type resin material can only in the subsequent production technical process, produce gas to overflow easily, affects product quality about 230 degree.
Described conductive barrier section 30 preferred with transparency conducting layer 24 employing identical material; as be specifically as follows tin indium oxide; tin indium oxide has good transmitance and electric conductivity; and; in the array base palte course of processing; when dry etching was carried out in the mistake hole site of passivation layer, tin indium oxide was difficult for reacting with etching gas, and effectively protected data line metal is not etched away.
Preferably above each bar data wire 22, described conductive barrier section 30 covers corresponding data wire 22.Embodiment as shown in Figure 2, the described data wire 22 of described conductive barrier section's 30 coverings, the pattern that is the pattern of conductive barrier section 30 and data wire 22 is fully overlapping, the array base palte of this structure is adding man-hour, after depositing successively data line layer metal and electrically conductive barrier metal, only need can form data line layer 22 and electrically conductive barrier 30 through a mask composition technique, therefore, this also is preferred embodiment of the present utility model; As shown in Figure 3, the other embodiment of the utility model can also be, 30 in described conductive barrier section is arranged on the data wire 22 position corresponding with via hole 21, in addition, conductive barrier section also can cover corresponding whole drain electrode, and the array base palte of these structures then needs to form data line layer 22 and electrically conductive barrier 30 through twice mask composition technique adding man-hour.
The utility model embodiment also provides a kind of display unit, it comprises above-mentioned any one array base palte, described display unit can for: liquid crystal panel, Electronic Paper, oled panel, LCD TV, liquid crystal display, DPF, mobile phone, panel computer etc. have product or the parts of any Presentation Function.
Embodiment as shown in Figure 4 makes the method for the utility model array base palte, comprising:
Preferably, described passivation layer material is non-photosensitive type resin; Described conductive barrier section is identical with the transparency conducting layer material.
Preferably, described conductive barrier section material is tin indium oxide.
As preferred version, described formation comprises data line layer and the electrically conductive barrier of many data wires, comprising:
Successively at substrate deposition data line layer metal and electrically conductive barrier metal, form many data wires and cover a plurality of conductive barrier section of each bar data wire by mask composition technique.
Wherein, described by the via hole of mask composition technique above passivation layer formation is positioned at conductive barrier section, comprising:
Passivation layer is carried out dry etching, form the via hole that is positioned at conductive barrier section top.
Wherein, the gas that described dry etching adopts comprises at least a gas in sulphur hexafluoride, tetrafluoride charcoal, oxygen and the helium, and this class gas can faster etch away the passivation layer of hole site.
The array base palte of embodiment shown in Fig. 2, its main fabrication processing is as follows:
At transparency carrier deposition grid metal, form grid line layer by the mask composition technique first time (mask composition technique generally includes cleaning, film forming, coating, exposure, development, does quarter or the operations such as wet etching, photoresist lift off);
Deposit gate insulator at the substrate of finishing above step;
Finishing the active layer film of substrate deposition of above step, by mask composition technique formation second time active layer;
Deposit successively data line layer metal (material is molybdenum) and electrically conductive barrier metal (material is tin indium oxide) on the substrate of above step finishing, form data line layer and electrically conductive barrier by mask composition technique for the third time;
Finish deposit passivation layer on the substrate of above step, forming the via hole that is positioned at conductive barrier section top by the 4th mask composition technique; In this step, the hole site of crossing of passivation layer is carried out gas that dry etching adopts and comprised at least a gas in sulphur hexafluoride, tetrafluoride charcoal, oxygen and the helium;
Finish deposit transparent conductive layer metal on the substrate of above step, forming transparency conducting layer by the 5th mask composition technique, this transparency conducting layer is deposited into via hole and is connected with conductive barrier section;
Finish substrate deposition second passivation layer of above step;
Finish deposit transparent conductive layer metal on the substrate of above step, by the second transparency conducting layer of the 6th mask composition technique formation slit-shaped.
As seen, in the 4th mask composition technique, to the crossing the hole site and carry out dry etching of passivation layer the time; the conductive barrier section that was positioned at hole site below effectively protected data line metal is not etched away; greatly improve the qualification rate of product, in addition, also greatly improved the production technology controllability.
Obviously, those skilled in the art can carry out various changes and modification to the utility model and not break away from spirit and scope of the present utility model.Like this, if of the present utility model these are revised and modification belongs within the scope of the utility model claim and equivalent technologies thereof, then the utility model also is intended to comprise these changes and modification interior.
Claims (7)
1. array base palte, it is characterized in that, comprise: the data line layer that comprises many data wires, be positioned on the described data line layer, comprise the electrically conductive barrier of a plurality of conductive barrier section, be positioned at the passivation layer on the described electrically conductive barrier, and be positioned at transparency conducting layer on the described passivation layer, wherein, above each bar data wire:
Be provided with via hole on the described passivation layer;
Described conductive barrier section is positioned at the via hole below, and with corresponding data wire contact;
Described transparency conducting layer connects with corresponding conductive barrier section by via hole.
2. array base palte as claimed in claim 1 is characterized in that, described passivation layer material is non-photosensitive type resin.
3. array base palte as claimed in claim 1 is characterized in that, described conductive barrier section is identical with the transparency conducting layer material.
4. array base palte as claimed in claim 3 is characterized in that, described conductive barrier section material is tin indium oxide.
5. array base palte as claimed in claim 1 is characterized in that, above each bar data wire, and described data wire corresponding to described conductive barrier section's covering.
6. array base palte as claimed in claim 1 is characterized in that, described data wire comprises source electrode and drain electrode, described drain electrode corresponding to described conductive barrier section's covering.
7. a display unit is characterized in that, comprises such as each described array base palte in the claim 1 ~ 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220364218 CN202712184U (en) | 2012-07-25 | 2012-07-25 | Array substrate and display apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201220364218 CN202712184U (en) | 2012-07-25 | 2012-07-25 | Array substrate and display apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202712184U true CN202712184U (en) | 2013-01-30 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201220364218 Expired - Lifetime CN202712184U (en) | 2012-07-25 | 2012-07-25 | Array substrate and display apparatus |
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| Country | Link |
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| CN (1) | CN202712184U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102799038A (en) * | 2012-07-25 | 2012-11-28 | 北京京东方光电科技有限公司 | Array substrate, display device and method for producing array substrate |
-
2012
- 2012-07-25 CN CN 201220364218 patent/CN202712184U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102799038A (en) * | 2012-07-25 | 2012-11-28 | 北京京东方光电科技有限公司 | Array substrate, display device and method for producing array substrate |
| CN102799038B (en) * | 2012-07-25 | 2015-04-01 | 北京京东方光电科技有限公司 | Array substrate, display device and method for producing array substrate |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: JINGDONGFANG SCIENCE AND TECHNOLOGY GROUP CO., LTD Free format text: FORMER OWNER: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY CO., LTD. Effective date: 20150708 Owner name: BEIJING BOE PHOTOELECTRICITY SCIENCE + TECHNOLOGY Effective date: 20150708 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20150708 Address after: 100015 Jiuxianqiao Road, Beijing, No. 10, No. Patentee after: BOE TECHNOLOGY GROUP Co.,Ltd. Patentee after: BEIJING BOE OPTOELECTRONICS TECHNOLOGY Co.,Ltd. Address before: 100176 Beijing city in Western Daxing District economic and Technological Development Zone, Road No. 8 Patentee before: BEIJING BOE OPTOELECTRONICS TECHNOLOGY Co.,Ltd. |
|
| CX01 | Expiry of patent term |
Granted publication date: 20130130 |
|
| CX01 | Expiry of patent term |