CN102800668A - Thin-film field effect transistor array substrate and manufacturing method thereof - Google Patents

Thin-film field effect transistor array substrate and manufacturing method thereof Download PDF

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Publication number
CN102800668A
CN102800668A CN2012102832855A CN201210283285A CN102800668A CN 102800668 A CN102800668 A CN 102800668A CN 2012102832855 A CN2012102832855 A CN 2012102832855A CN 201210283285 A CN201210283285 A CN 201210283285A CN 102800668 A CN102800668 A CN 102800668A
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China
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test
grid line
electrode
protective layer
drain electrode
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CN2012102832855A
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Chinese (zh)
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刘旭
朴承翊
石天雷
杨玉清
辛燕霞
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to CN2012102832855A priority Critical patent/CN102800668A/en
Publication of CN102800668A publication Critical patent/CN102800668A/en

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Abstract

The embodiment of the invention provides a thin-film field effect transistor array substrate and a manufacturing method thereof, relates to the technical field of liquid crystal display, and aims to solve the problem that TFT (Thin Film Transistor) characteristics of each pixel on the substrate are hard to detect. The thin-film field effect transistor array substrate comprises an effective pixel region, which includes grid lines, data lines, a thin-film field effect transistor, a pixel electrode and a public electrode; the thin-film field effect transistor array substrate further comprises testing grid lines, which are positioned on the external sides of the grid lines at the edge of the effective pixel region and positioned in the same layer as the grid lines; the testing grid lines are crossed with the data lines in the effective pixel region so as to form a plurality of testing regions; in each testing region, a testing grid, a testing semiconductor active layer, a testing source and a testing drain are formed, wherein the testing grid is electrically connected with the testing grid and the testing source is electrically connected with the data line in the effective pixel region; and in each testing region, a testing contact region electrically connected with the testing drain is also formed. The thin-film field effect transistor array substrate and the manufacturing method thereof, provided by the invention, are used for detecting the TFT array substrates.

Description

A kind of TFT array base palte and manufacturing approach thereof

Technical field

The present invention relates to technical field of liquid crystal display, relate in particular to a kind of TFT array base palte and manufacturing approach thereof.

Background technology

LCD (Liquid Crystal Display is called for short LCD) has been the main product of field of display.Its operation principle mainly is to utilize electric field to control the ordered state of liquid crystal molecule, thereby and then the light that produces of control backlight can manifest required display image through liquid crystal.At present; The mainstream technology of electric field controls liquid crystal molecule comprises TN (Twisted Nematic; Twisted-nematic) type, IPS (In-Plane Switching, plane conversion) type and AD-SDS (ADvanced Super Dimension Switch; Being called for short ADS, a senior ultra dimension switch technology) the vertical electric field of utilization, transverse electric field or multi-dimensional electric field such as type drive the technology of liquid crystal rotation.

Wherein, The electric field that electric field that the ADS drive pattern is mainly produced through gap electrode edge in the same plane and gap electrode layer and plate electrode interlayer produce forms multi-dimensional electric field; Make in the liquid crystal cell between gap electrode, all aligned liquid-crystal molecules can both produce rotation directly over the electrode, thereby improved the liquid crystal operating efficiency and increased light transmission efficiency.A senior ultra dimension switch technology can improve the picture quality of TFT-LCD product, has high-resolution, high permeability, low-power consumption, wide visual angle, high aperture, low aberration, no water of compaction ripple advantages such as (push Mura).

TFT (Thin Film Transistor to IPS type and ADS type LCD; TFT) array base palte; A kind of situation is: the pixel on the substrate (Pixel) electrode is embedded under the protective layer, is positioned at nexine, on this protective layer, forms common electrode layer more afterwards.Because pixel electrode is embedded in nexine, thereby is difficult to the TFT characteristic of each pixel on the substrate is detected, the yields that has limited tft array substrate promotes.

Summary of the invention

The present invention provides a kind of TFT array base palte and manufacturing approach thereof, is difficult to the problem that the TFT characteristic to each pixel on the substrate detects with solution.

For achieving the above object, embodiments of the invention adopt following technical scheme:

On the one hand, a kind of TFT array base palte is provided, comprises the effective pixel area that constitutes by grid line, data wire, TFT, pixel electrode and public electrode;

Also comprise:

In the outside of the grid line at said effective pixel area edge, also be provided with and said grid line with the test grid line of layer, each interior bar data wire of said test grid line and said effective pixel area intersects to form a plurality of test zones;

In each said test zone, the test source electrode that be formed with the test grid that is electrically connected with said test grid line, measuring semiconductor active layer, is electrically connected, and test drain electrode with data wire in the said effective pixel area;

In each said test zone, also be formed with the test contact zone that is electrically connected with said test drain electrode.

Further, in said effective pixel area, the drain electrode of said pixel electrode and said TFT connects; On said pixel electrode, be coated with first protective layer; Said public electrode is formed on said first protective layer.

Further, the said test contact zone in the said test zone is formed on said first protective layer, with said public electrode layer together.

Further, the structure of said test zone comprises: substrate; Be formed on test grid line, test grid on the said substrate; Be formed on the gate insulation layer on said test grid line, the test grid; Be formed on the measuring semiconductor active layer on the said gate insulation layer; Be formed on data wire, test source electrode, test drain electrode on the said substrate; Be formed on first protective layer of the said effective pixel area interior pixel of the covering electrode on the said substrate; Contain first via hole that exposes said test drain electrode on said first protective layer; Be formed on the test contact zone that said first via hole is electrically connected with said test drain electrode that passes through on said first protective layer.

Further, on said public electrode, also be coated with second protective layer; Said test contact zone in the said test zone is formed on said second protective layer.

Further, the structure of said test zone comprises: substrate; Be formed on test grid line, test grid on the said substrate; Be formed on the gate insulation layer on said test grid line, the test grid; Be formed on the measuring semiconductor active layer on the said gate insulation layer; Be formed on data wire, test source electrode, test drain electrode on the said substrate; Be formed on first protective layer of the said effective pixel area interior pixel of the covering electrode on the said substrate; Be formed on second protective layer of public electrode in the said effective pixel area of covering on the said substrate; Contain on said second protective layer and penetrate second via hole that said first protective layer exposes said test drain electrode; Be formed on the test contact zone that said second via hole is electrically connected with said test drain electrode that passes through on said second protective layer.

Further, said test grid line is one, is arranged on the outside of the grid line of said effective pixel area one lateral edges.

Further, said test grid line is two, is separately positioned on the outside of the grid line of said effective pixel area both sides of the edge.

On the other hand, a kind of manufacturing approach of TFT array base palte is provided, comprises:

On substrate, form grid line, grid through the composition PROCESS FOR TREATMENT;

On said grid line, said grid, form gate insulation layer;

On said gate insulation layer, form semiconductor active layer through the composition PROCESS FOR TREATMENT;

On said substrate, form data wire, source electrode and drain electrode through composition technology; Said data wire and said grid line intersect and constitute pixel region, and in removing the pixel region that outermost grid line constitutes, form the pixel electrode that is electrically connected with said drain electrode through composition technology;

On said substrate, form protective layer;

On said protective layer, in the pixel region that removes said outermost grid line formation, form public electrode through composition technology;

In the pixel region that said outermost grid line constitutes, form the test contact zone that is electrically connected with said drain electrode through the composition PROCESS FOR TREATMENT.

Can find out that from such scheme the grid line arranged outside at the effective pixel area edge has the test grid line, the data wire in this test grid line and the effective pixel area constitutes test zone.In test zone owing to be formed with TFT; And the test contact zone that is electrically connected with the test drain electrode; Therefore can be through testing the contact zone transmitted test signal to this; Realization is to the detection of the TFT of associated data line and the pixel that this data wire connected, thereby can test out the TFT characteristic of each pixel easily.

Description of drawings

In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art; To do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below; Obviously, the accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills; Under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.

The plan structure sketch map of the tft array substrate that Fig. 1 provides for the embodiment of the invention;

The board structure sketch map of the tft array substrate test zone that Fig. 2 (a) provides for the embodiment of the invention; The board structure sketch map of the tft array substrate effective pixel area that Fig. 2 (b) provides for the embodiment of the invention;

The board structure sketch map of the tft array substrate test zone that Fig. 3 (a) provides for the embodiment of the invention; The board structure sketch map of the tft array substrate effective pixel area that Fig. 3 (b) provides for the embodiment of the invention;

The board structure sketch map of the tft array substrate test zone that Fig. 4 (a) provides for the embodiment of the invention; The board structure sketch map of the tft array substrate effective pixel area that Fig. 4 (b) provides for the embodiment of the invention;

The board structure sketch map of the tft array substrate test zone that Fig. 5 (a) provides for the embodiment of the invention; The board structure sketch map of the tft array substrate effective pixel area that Fig. 5 (b) provides for the embodiment of the invention;

The board structure sketch map of the tft array substrate test zone that Fig. 6 (a) provides for the embodiment of the invention; The board structure sketch map of the tft array substrate effective pixel area that Fig. 6 (b) provides for the embodiment of the invention;

The board structure sketch map of the tft array substrate test zone that Fig. 7 (a) provides for the embodiment of the invention; The board structure sketch map of the tft array substrate effective pixel area that Fig. 7 (b) provides for the embodiment of the invention;

The board structure sketch map of the tft array substrate test zone that Fig. 8 (a) provides for the embodiment of the invention; The board structure sketch map of the tft array substrate effective pixel area that Fig. 8 (b) provides for the embodiment of the invention.

Embodiment

To combine the accompanying drawing in the embodiment of the invention below, the technical scheme in the embodiment of the invention is carried out clear, intactly description, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills are not making the every other embodiment that is obtained under the creative work prerequisite, all belong to the scope of the present invention's protection.

The TFT array base palte that the embodiment of the invention provides is that example describes with substrate schematic top plan view shown in Figure 1.

In Fig. 1, horizontal grid line 12,13,14 and longitudinally data wire 21,22,23,24 horizontal vertical intersections confirmed pixel region.In the present embodiment, grid line 12,13,14 and the definite pixel region of data wire 21,22,23,24 horizontal vertical intersections are called effective pixel area.Need to prove, be to be example with three grid lines and four data wires in the present embodiment, and the not restriction of actual grid line, data number of lines can be any many in the zone of reasonableness.

In the present embodiment, be embedded in nexine with pixel electrode, public electrode is arranged on the pixel electrode top and describes for example.

In each pixel region in effective pixel area, be formed with the pixel electrode 4 that is electrically connected with drain electrode 3; On pixel electrode 4, be formed with protective layer (not expression among Fig. 1); On protective layer, be formed with common electrode layer (not expression among Fig. 1).

Need to prove; For making horizontal electric field or the multi-dimensional electric field of generation between pixel electrode and the public electrode; Therefore the public electrode that is positioned at the top in the present embodiment must be made the for example pectinate texture that contains slit; The pixel electrode that is positioned at lower floor both can be plate, also can be the pectinate texture that contains slit as shown in Figure 1.

Further, in the outside (being the top of grid line 12 among Fig. 1) of the grid line 12 at effective pixel area edge, also be provided with effective pixel area in grid line with the test grid line 11 of layer; This test grid line 11 intersects to form a plurality of test zones with each interior bar data wire 21,22,23,24 of effective pixel area.

Same, in the outside (being the below of grid line 14 among Fig. 1) of the grid line 14 at effective pixel area edge, also be provided with effective pixel area in grid line with the test grid line 15 of layer; This test grid line 15 intersects to form a plurality of test zones with each interior bar data wire 21,22,23,24 of effective pixel area.

In the present embodiment, the test grid line is exemplified as two, but also can be one, promptly can only have the test grid line 11 among Fig. 1 or test any in the grid line 15.

In each test zone, all be formed with test grid 6, measuring semiconductor active layer 7, the test source electrode 8 that is electrically connected with the interior data wire of effective pixel area and test drain electrode 3.Wherein, this test grid 6, measuring semiconductor active layer 7, test source electrode 8 and test drain electrode 3 constitute TFT.

In this test zone, be not formed with pixel electrode and public electrode.

In addition, in each test zone, also be formed with the test contact zone 5 that is electrically connected with test drain electrode 3.

Like this; When tft array substrate shown in Figure 1 is detected; When for example data wire 21 being detected, can load test voltage, behind test grid line 11 and/or 15 loading unlatchings of test grid line or shutoff voltage to data wire 21; Utilize testing equipment on the test contact zone, to load accordingly, detect test signal, just can detect the short circuit of data wire 21 and open circuit.For example; Can load test voltage to data wire 21; After test grid line 15 loads unlatching or shutoff voltage; Utilize testing equipment to load test signal to the test contact zone of the data wire 21 and the test zone of test grid line 15 definition, if data wire 21 short circuits are perhaps opened circuit, then data wire 21 will can not detect normal signal with the test contact zone of the test zone of test grid line 15 definition.In addition; Also can load test signal to data wire 21; Behind 11 loading unlatchings of test grid line or shutoff voltage, utilize the test contact zone of the testing equipment test grid line 11 and the test zone of data wire 21 definition, to reach the purpose of this test zone of detection TFT characteristic; Thereby can draw the TFT characteristic of the effective pixel region under the same process condition, realize monitoring process stability and inhomogeneity purpose.In actual test process, be to need two test grid lines or one is tested the grid line action, can look the needs of checkout equipment and decide.

In the present embodiment, be with pixel electrode down, public electrode is in the last explanation of carrying out for example, present embodiment is not limited to this, public electrode is descending, pixel electrode also can be provided with above-mentioned test zone at last tft array substrate, and tests the contact zone.

In addition, in the present embodiment, matcoveredn at interval between pixel electrode and the public electrode, the test contact zone can with public electrode with layer, be arranged on this protective layer, the test contact zone can certainly be arranged on the upper strata of public electrode.

In addition; Being provided with when sealing frame glue on tft array substrate shown in Figure 1; Can be arranged at the side of test grid line 11,15, promptly isolate envelope frame glue and effective pixel area, so more can guarantee product quality through test grid line 11,15 away from effective pixel area.

The manufacturing approach of the TFT array base palte that the embodiment of the invention once provides is described through accompanying drawing 2~Fig. 7 below.Wherein, (a) figure among Fig. 2~Fig. 7 is the sectional view of test zone, and (b) figure is the sectional view of effective pixel area.

Need to prove, be still in the present embodiment with earlier below to form public electrode up after forming pixel electrode be the explanation that example is carried out.

Step 201: as Fig. 2 (a) (b) shown in, forming grid line, grid 32 (in the present embodiment, the grid in the test zone is called the test grid) on the substrate 31 through the composition PROCESS FOR TREATMENT.In this step, the test zone shown in Fig. 1 (a) is identical with the manufacture craft of the effective pixel area shown in Fig. 1 (b).

Concrete; Can use magnetically controlled sputter method, preparation one layer thickness is at metallic film to on glass substrate.Metal material can adopt metals such as molybdenum, aluminium, alumel, molybdenum and tungsten alloy, chromium or copper usually, also can use the combining structure of above-mentioned different materials film.Then, with mask through exposure, development, etching, the composition PROCESS FOR TREATMENT such as peel off, on certain zone of substrate 31, form the figure of many horizontal grid lines and the grid that links to each other with grid line 32.

Step 202: as Fig. 3 (a) (b) shown in, on grid line, grid 32, form gate insulation layer 33.In this step, the test zone shown in Fig. 3 (a) is identical with the manufacture craft of the effective pixel area shown in Fig. 3 (b).

Concrete; Can utilize chemical vapor deposition method successive sedimentation thickness on substrate to be the gate insulation layer 33 of to ; The material of gate insulation layer 33 is silicon nitride normally, also can use silica and silicon oxynitride etc.

Step 203: as Fig. 4 (a) (b) shown in, forming semiconductor active layer 34 (in the present embodiment, the semiconductor active layer in the test zone is called the measuring semiconductor active layer) through the composition PROCESS FOR TREATMENT on the gate insulation layer 33.In this step, the test zone shown in Fig. 4 (a) is identical with the manufacture craft of the effective pixel area shown in Fig. 4 (b).

Concrete; Can utilize chemical vapor deposition method deposit thickness on gate insulation layer 33 also can be depositing metal oxide semiconductive thin film on gate insulation layer 33 for the amorphous silicon membrane and the n+ amorphous silicon membrane of to .Mask with active layer makes public to amorphous silicon membrane, afterwards this amorphous silicon membrane is carried out dry etching, above grid 32, forms semiconductor active layer 34.

If the depositing metal oxide semiconductive thin film is as active layer on gate insulation layer 33; Then metal oxide semiconductor films is carried out a composition technology and can form active layer; Promptly after photoresist applies, with common mask to substrate make public, development, etching formation semiconductor active layer 34 get final product.If what form on the gate insulation layer 33 is amorphous silicon membrane and n+ amorphous silicon membrane, then need carry out etching by the n+ amorphous silicon membrane above raceway groove, to form raceway groove.

Step 204: shown in Fig. 5 (b); Form pixel electrode 40, the drain electrode 36 that forms data wire (not shown), source electrode 35 afterwards and be electrically connected in the pixel transmission region in effective pixel area (also promptly removing the pixel region that outermost grid line constitutes) with pixel electrode 40.Shown in Fig. 5 (a); In test zone (yet being the pixel region that outermost grid line constitutes), do not form pixel electrode; On measuring semiconductor active layer 34, directly form data wire (not shown), source electrode 35 and drain 36 (in the present embodiment; Source electrode in the test zone is called the test source electrode, and drain electrode is called the test drain electrode).

Concrete, can utilize chemical vapor deposition method on whole base plate, to deposit the layer of conductive film layer, obtain the pixel electrode figure in the effective pixel area through composition technology afterwards, and get rid of the conductive membrane layer of test zone.Conductive film commonly used can be ITO (Indium Tin Oxides; Indium tin oxide) or IZO (Indium Zinc Oxide; Indium-zinc oxide), thickness is between to .

Afterwards, can on substrate, deposit a layer thickness and arrive metallic film at .Form the figure of data wire, source electrode, drain electrode in the regulation zone through the composition PROCESS FOR TREATMENT.

Need to prove, in this step, be to form pixel electrode 40 earlier in the effective pixel area, carries the drain electrode 36 that forms source electrode 35 and be electrically connected with pixel electrode 40 afterwards.But can form source electrode 35, drain electrode 36 earlier yet, form the pixel electrode 40 that is electrically connected with drain electrode 36 afterwards again, present embodiment does not limit.

Step 205: as Fig. 6 (a) (b) shown in, in data wire, source electrode 35, drain electrode 36, form protective layer 37.Especially, in the test zone shown in Fig. 6 (a), also on the protective layer 37 above the drain electrode 36, form and expose the via hole 38 of this drain electrode 36.

Concrete; Can on whole base plate, apply the protective layer that a layer thickness arrives at , its material is silicon nitride or transparent organic resin material normally.In the test zone shown in Fig. 6 (a),, utilize composition technology on the protective layer 37 above the drain electrode 36, to form and expose the via hole 38 of said drain electrode 36 through mask.

Step 206: shown in Fig. 7 (b), on the protective layer 37 of effective pixel area (also promptly removing the pixel region that outermost grid line constitutes), form public electrode 41.Shown in Fig. 7 (a), on the protective layer 37 of test zone (also being the pixel region that outermost grid line constitutes), form the test contact zone 39 that is electrically connected with test drain electrode 36 through via hole 38.Wherein, this test contact zone 39 can be made with material with layer with public electrode 41.

Concrete; Can be similar with the method for making pixel electrode; Utilize chemical vapor deposition method on whole base plate, to deposit the layer of conductive film layer, utilize composition technology to obtain the figure of the public electrode of effective pixel area and the figure of the test contact zone of test zone afterwards.Conductive film commonly used can be ITO or IZO, and thickness is between to .

Signal through Fig. 7 (b) also can be found out; Produce transverse electric field or multi-dimensional electric field between public electrode 41 that occupy the upper strata and the pixel electrode 40 that occupy lower floor for making; The public electrode 41 that occupy the upper strata must be the structure that has the for example pectination of slit; And the pixel electrode that occupy lower floor can certainly be a plate-like structure in the present embodiment for having the pectinate texture of slit.

Need to prove; The concrete structure of effective pixel area and manufacture method just illustrate in the present embodiment; Present embodiment is not limited to this; Other for example top gate structure, composition form source/drain electrode and semiconductor active layer etc. all can, just do not form pixel electrode, public electrode and only form and test the test contact zone that drains and be electrically connected at test zone.

Further; In another embodiment, basic structure is identical with a last embodiment with manufacture method, just shown in Fig. 8 (b); In effective pixel area; On public electrode 41, cover second protective layer 42 again, be separated with first protective layer 37 between promptly between pixel electrode 40 and the public electrode 41, be coated with second protective layer 42 on the public electrode 41.Shown in Fig. 8 (a); At test zone; In test drain electrode 36, be coated with first protective layer 37 and second protective layer 42; And on second protective layer 42, penetrate the via hole 382 that first protective layer 37 exposes test drain electrode 36 through the formation of composition technology, and on second protective layer 42, forming test contact zone 39, this is tested contact zone 39 and is electrically connected through via hole 382 and test drain electrode 36.

Can find out that from the foregoing description the grid line arranged outside at the effective pixel area edge has the test grid line, the data wire in this test grid line and the effective pixel area constitutes test zone.In test zone owing to be formed with TFT; And the test contact zone that is electrically connected with the test drain electrode; Therefore can be through testing the contact zone transmitted test signal to this; Realization is to the detection of the TFT of associated data line and the pixel that this data wire connected, thereby can test out the TFT characteristic of each pixel easily.

The above; Be merely embodiment of the present invention, but protection scope of the present invention is not limited thereto, any technical staff who is familiar with the present technique field is in the technical scope that the present invention discloses; Can expect easily changing or replacement, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of said claim.

Claims (12)

1. a TFT array base palte comprises the effective pixel area that is made up of grid line, data wire, TFT, pixel electrode and public electrode;
It is characterized in that, also comprise:
In the outside of the grid line at said effective pixel area edge, also be provided with and said grid line with the test grid line of layer, each interior bar data wire of said test grid line and said effective pixel area intersects to form a plurality of test zones;
In each said test zone, the test source electrode that be formed with the test grid that is electrically connected with said test grid line, measuring semiconductor active layer, is electrically connected, and test drain electrode with data wire in the said effective pixel area;
In each said test zone, also be formed with the test contact zone that is electrically connected with said test drain electrode.
2. TFT array base palte according to claim 1 is characterized in that, in said effective pixel area, the drain electrode of said pixel electrode and said TFT connects; On said pixel electrode, be coated with first protective layer; Said public electrode is formed on said first protective layer.
3. TFT array base palte according to claim 2 is characterized in that, the said test contact zone in the said test zone is formed on said first protective layer, with said public electrode layer together.
4. TFT array base palte according to claim 3 is characterized in that, the structure of said test zone comprises:
Substrate;
Be formed on test grid line, test grid on the said substrate;
Be formed on the gate insulation layer on said test grid line, the test grid;
Be formed on the measuring semiconductor active layer on the said gate insulation layer;
Be formed on data wire, test source electrode, test drain electrode on the said substrate;
Be formed on first protective layer of the said effective pixel area interior pixel of the covering electrode on the said substrate; Contain first via hole that exposes said test drain electrode on said first protective layer;
Be formed on the test contact zone that said first via hole is electrically connected with said test drain electrode that passes through on said first protective layer.
5. TFT array base palte according to claim 2 is characterized in that,
On said public electrode, also be coated with second protective layer;
Said test contact zone in the said test zone is formed on said second protective layer.
6. TFT array base palte according to claim 5 is characterized in that, the structure of said test zone comprises:
Substrate;
Be formed on test grid line, test grid on the said substrate;
Be formed on the gate insulation layer on said test grid line, the test grid;
Be formed on the measuring semiconductor active layer on the said gate insulation layer;
Be formed on data wire, test source electrode, test drain electrode on the said substrate;
Be formed on first protective layer of the said effective pixel area interior pixel of the covering electrode on the said substrate;
Be formed on second protective layer of public electrode in the said effective pixel area of covering on the said substrate; Contain on said second protective layer and penetrate second via hole that said first protective layer exposes said test drain electrode;
Be formed on the test contact zone that said second via hole is electrically connected with said test drain electrode that passes through on said second protective layer.
7. according to the arbitrary described TFT array base palte of claim 1 to 6, it is characterized in that said test grid line is one, be arranged on the outside of the grid line of said effective pixel area one lateral edges.
8. according to the arbitrary described TFT array base palte of claim 1 to 6, it is characterized in that said test grid line is two, be separately positioned on the outside of the grid line of said effective pixel area both sides of the edge.
9. the manufacturing approach of a TFT array base palte is characterized in that, comprising:
On substrate, form grid line, grid through the composition PROCESS FOR TREATMENT;
On said grid line, said grid, form gate insulation layer;
On said gate insulation layer, form semiconductor active layer through the composition PROCESS FOR TREATMENT;
On said substrate, form data wire, source electrode and drain electrode through composition technology; Said data wire and said grid line intersect and constitute pixel region, and in removing the pixel region that outermost grid line constitutes, form the pixel electrode that is electrically connected with said drain electrode through composition technology;
On said substrate, form protective layer;
On said protective layer, in the pixel region that removes said outermost grid line formation, form public electrode through composition technology;
In the pixel region that said outermost grid line constitutes, form the test contact zone that is electrically connected with said drain electrode through the composition PROCESS FOR TREATMENT.
10. method according to claim 9 is characterized in that, on said protective layer, in the pixel region that removes said outermost grid line formation, forms public electrode through composition technology; In the pixel region that said outermost grid line constitutes, forming the test contact zone that is electrically connected with said drain electrode through the composition PROCESS FOR TREATMENT comprises:
On said protective layer, form conductive membrane layer;
Through the composition PROCESS FOR TREATMENT, in the pixel region that removes said outermost grid line formation, form public electrode; In the pixel region that said outermost grid line constitutes, form the test contact zone that is electrically connected with said drain electrode.
11. method according to claim 9 is characterized in that, on said protective layer, in the pixel region that removes said outermost grid line formation, after composition technology formation public electrode, also comprises:
On said public electrode, form second protective layer, said second protective layer contains the via hole that exposes said drain electrode;
In the pixel region that said outermost grid line constitutes, forming the test contact zone that is electrically connected with said drain electrode through the composition PROCESS FOR TREATMENT comprises: on said second protective layer, in the pixel region that said outermost grid line constitutes, form the test contact zone that is electrically connected with said drain electrode through the composition PROCESS FOR TREATMENT.
12. method according to claim 9 is characterized in that, said outermost grid line is positioned at the outermost grid line of an end in each bar grid line, perhaps for laying respectively at outermost two grid lines in two ends.
CN2012102832855A 2012-08-09 2012-08-09 Thin-film field effect transistor array substrate and manufacturing method thereof CN102800668A (en)

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