CN102854677A - Array substrate, production method of array substrate and display device - Google Patents
Array substrate, production method of array substrate and display device Download PDFInfo
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- CN102854677A CN102854677A CN2012103327355A CN201210332735A CN102854677A CN 102854677 A CN102854677 A CN 102854677A CN 2012103327355 A CN2012103327355 A CN 2012103327355A CN 201210332735 A CN201210332735 A CN 201210332735A CN 102854677 A CN102854677 A CN 102854677A
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Abstract
The invention provides an array substrate, a production method of the array substrate and a display device and belongs to the field of liquid crystal display. A gate insulating layer of the array substrate is made of black insulating material. The gate insulating layer is provided with an opening for exposing a pixel region. By the array substrate, quality of display frames is improved.
Description
Technical field
The present invention relates to field of liquid crystal display, particularly the manufacture method of a kind of array base palte, array base palte and display device.
Background technology
Liquid crystal display comprises the pixel cell with matrix form design, and the driving circuit that drives these pixel cells, realizes the deflection of liquid crystal molecule reaching display effect by the variation of liquid crystal cell internal electric field.
Available liquid crystal display device great majority adopt traditional black matrix manufacturing technology, namely in order to avoid the light leak problem, make black matrix at color membrane substrates, and respectively red color resistance R, green look resistance G and blue look resistance B are connected with black matrix with the form of overlapping (Over Lap).This structure can inevitably be brought the poor problem of angle section, has had a strong impact on like this quality of display frame.
Summary of the invention
Technical matters to be solved by this invention provides manufacture method and the display device of a kind of array base palte, array base palte, to improve the quality of display frame.
For solving the problems of the technologies described above, it is as follows to the invention provides technical scheme:
A kind of array base palte, the gate insulation layer of described array base palte adopts the black insulating material, and described gate insulation layer has the opening that exposes pixel region.
Described array base palte comprises:
Substrate;
Be formed on gate electrode and grid line on the substrate;
Be formed on the described gate insulation layer on the substrate that is formed with described gate electrode and grid line;
Be formed on the semiconductor layer on the described gate insulation layer;
Be formed on data line, source electrode and drain electrode on the described semiconductor layer;
Be formed on the passivation layer on the substrate that is formed with described data line, source electrode and drain electrode, be formed with via hole on the described passivation layer;
Be formed on the pixel electrode on the passivation layer, described pixel electrode is connected with described drain electrode by described via hole.
Above-mentioned array base palte wherein, also comprises:
Be formed on the ohmic contact layer between described source electrode, drain electrode and the semiconductor layer.
Above-mentioned array base palte, wherein: described black insulating material is organic material.
A kind of manufacture method of array base palte, described manufacture method adopt the black insulating material to form the gate insulation layer of described array base palte, and form the opening that exposes pixel region in described gate insulation layer.
Described manufacture method comprises:
Form gate electrode and grid line at substrate;
Form described gate insulation layer at the substrate that is formed with described gate electrode and grid line;
Form semiconductor layer, data line, source electrode and drain electrode at described gate insulation layer;
Form passivation layer at the substrate that is formed with described semiconductor layer, data line, source electrode and drain electrode, and form via hole at described passivation layer;
Form pixel electrode at described passivation layer, described pixel electrode is connected with described drain electrode by described via hole.
Above-mentioned manufacture method also comprises:
At described source electrode.Form ohmic contact layer between drain electrode and the semiconductor layer.
Above-mentioned manufacture method, wherein: described black insulating material is organic material.
A kind of display device comprises above-mentioned array base palte.
According to technique scheme of the present invention, utilize the black insulating material to form the gate insulation layer of array base palte, and form the opening that exposes pixel region at described gate insulation layer, like this, gate insulation layer has just played the effect of black matrix simultaneously, can avoid the poor problem of angle section that color membrane substrates occurs in the existing display device manufacture process, thereby improve the quality of display frame.In addition, owing to avoided the angle section poor, then can omit again the coating of color membrane substrates flatness layer, thereby can reduce the manufacturing cost of display device.
Description of drawings
Fig. 1 is the schematic cross-section of the array base palte of the embodiment of the invention;
Fig. 2 is the floor map of gate insulation layer in the array base palte of the embodiment of the invention;
Fig. 3～Fig. 6 is the manufacture process synoptic diagram of the array base palte of the embodiment of the invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, describe the present invention below in conjunction with the accompanying drawings and the specific embodiments.
For fear of having the poor problem of angle section that color membrane substrates occurs in the display device manufacture process now, the embodiment of the invention provides a kind of display device, described display device comprise array base palte, color membrane substrates and be folded in described array base palte and described color membrane substrates between liquid crystal layer.Wherein, do not comprise black matrix in the described color membrane substrates; The gate insulation layer of described array base palte adopts the black insulating material, and described gate insulation layer has the opening that exposes pixel region, and like this, gate insulation layer has just played the effect of black matrix simultaneously.Particularly, described display device can be liquid crystal panel, LCD TV, mobile phone, liquid crystal display etc.
Fig. 1 is the schematic cross-section of the array base palte of the embodiment of the invention.With reference to Fig. 1, described array base palte can comprise:
Substrate 1;
Be formed on gate electrode 2 and grid line (not shown) on the substrate 1;
Be formed on the described gate insulation layer 3 on the substrate 1 that is formed with described gate electrode 2 and grid line, gate insulation layer 3 adopts the black insulating material, and described gate insulation layer 3 has the opening that exposes pixel region;
Be formed on the semiconductor layer 4 on the described gate insulation layer 3;
Be formed on data line (not shown), source electrode 6 and drain electrode 7 on the described semiconductor layer 4;
Be formed on the passivation layer 8 on the substrate 1 that is formed with described data line, source electrode 6 and drain electrode 7, be formed with via hole 9 on the described passivation layer;
Be formed on the pixel electrode 10 on the passivation layer 8, described pixel electrode 10 is connected with described drain electrode 8 by described via hole 9.
Alternatively, described array base palte also comprises the ohmic contact layer 5 that is formed between described source electrode 6, drain electrode 7 and the semiconductor layer 4.
Fig. 2 is the floor map of gate insulation layer in the array base palte of the embodiment of the invention.Can find out that in conjunction with Fig. 1 and Fig. 2 gate insulation layer 3 has covered grid line, data line and thin film transistor (TFT) in the direction perpendicular to array base palte, and expose pixel region, thereby play the effect of black matrix.This kind mode can strengthen the shading intensity between each sub-pix, thereby avoids the generation of color cross-talk.
Alternatively, described black insulating material is organic material.By adopting organic material, can be array base palte and bring the advantages such as low threshold voltage, low electric leakage, high mobility.
The embodiment of the invention also provides the manufacture method of above-mentioned array base palte, can comprise the steps:
Step S1 provides a substrate, forms grid line and gate electrode at substrate;
As shown in Figure 3, at first, can adopt sputter, thermal evaporation or other film build method, on the transparency carrier 1 of glass substrate 1 or other types, form the grid metal level, the grid metal level can adopt chromium (Cr), molybdenum (Mo), aluminium (Al), copper (Cu), tungsten (W), neodymium (Nd) and alloy thereof, and the grid metal level can be one or more layers; Then, form photoresist at the grid metal level; Secondly, the employing portrayal has the mask plate of figure that photoresist is exposed and develops, and forms the photoresist mask; Again, adopt the photoresist mask that the grid metal level is carried out etching, form grid line and gate electrode 2; At last, peel off remaining photoresist.
Step S2 forms gate insulation layer at the substrate of completing steps S1;
Such as Fig. 2 and shown in Figure 4, at first, can strengthen the methods such as chemical vapor deposition (PECVD) by using plasma, deposit gate insulating film at described substrate 1, wherein, gate insulating film adopts the black insulating material, and alternatively, described black insulating material is organic material; Then, form photoresist at the grid metal film; Secondly, the employing portrayal has the mask plate of figure that photoresist is exposed and develops, and forms the photoresist mask; Again, adopt the photoresist mask gate insulating film to be carried out etching, the figure of shape gate insulation layer 3; At last, peel off remaining photoresist.
Step S3 forms semiconductor layer, ohmic contact layer, data line, source electrode and drain electrode at the substrate of completing steps S2;
As shown in Figure 5, at first, metal film is leaked in deposited semiconductor film, Ohmic contact film, source successively on described substrate 1; Then, leak metal film in the source and form photoresist layer; Secondly, adopt portrayal to have the gray tone of figure or intermediate tone mask plate that photoresist layer is exposed and develops, formation comprises the not photoresist mask of reserve area of the complete reserve area of photoresist, photoresist part reserve area and photoresist; Again, source leakage metal film, Ohmic contact film and the semiconductor film of reserve area do not carry out etching, the figure of formation data line and semiconductor layer 4 to photoresist to adopt the photoresist mask; Again, by the photoresist of cineration technics removal photoresist part reserve area, the photoresist attenuation of the complete reserve area of photoresist forms new photoresist mask; Again, metal film and Ohmic contact film are leaked in the source of adopting new photoresist mask etching to expose, and form the figure of source electrode 6 and drain electrode 7, and finish the raceway groove of thin film transistor (TFT); At last, peel off remaining photoresist.
Step S4 forms passivation layer at the substrate of completing steps S3, and passivation layer is carried out composition;
As shown in Figure 6, at first, can adopt the methods such as PECVD, forming thickness at described substrate 1 is passivation layer 8, and passivation layer 8 can adopt the materials such as SiNx or SiOx; Then, form photoresist at passivation layer 8; Secondly, the employing portrayal has the mask plate of figure that photoresist is exposed and develops, and forms the photoresist mask; Again, adopt the photoresist mask that passivation layer is carried out etching, to expose drain electrode 7, form via hole 9; At last, peel off remaining photoresist.
Step S5 forms pixel electrode at the substrate of completing steps S4.
As shown in Figure 1, at first, can adopt magnetron sputtering, thermal evaporation or other film build method, form transparency conducting layer at described substrate 1, transparency conducting layer can adopt the materials such as tin indium oxide (ITO), indium zinc oxide (IZO) or aluminum zinc oxide; Then, form photoresist at transparency conducting layer; Secondly, the employing portrayal has the mask plate of figure that photoresist is exposed and develops, and forms the photoresist mask; Again, adopt the photoresist mask that transparency conducting layer is carried out etching, form pixel electrode 10, wherein, described pixel electrode 10 connects in described drain electrode 7 by via hole 9; At last, peel off remaining photoresist
Should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from the spiritual scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (9)
1. array base palte is characterized in that: the gate insulation layer of described array base palte adopts the black insulating material, and described gate insulation layer has the opening that exposes pixel region.
2. array base palte as claimed in claim 1 is characterized in that, described array base palte comprises:
Substrate;
Be formed on gate electrode and grid line on the substrate;
Be formed on the described gate insulation layer on the substrate that is formed with described gate electrode and grid line;
Be formed on the semiconductor layer on the described gate insulation layer;
Be formed on data line, source electrode and drain electrode on the described semiconductor layer;
Be formed on the passivation layer on the substrate that is formed with described data line, source electrode and drain electrode, be formed with via hole on the described passivation layer;
Be formed on the pixel electrode on the passivation layer, described pixel electrode is connected with described drain electrode by described via hole.
3. array base palte as claimed in claim 2 is characterized in that, also comprises:
Be formed on the ohmic contact layer between described source electrode, drain electrode and the semiconductor layer.
4. array base palte as claimed in claim 1 is characterized in that:
Described black insulating material is organic material.
5. the manufacture method of an array base palte is characterized in that: described manufacture method adopts the black insulating material to form the gate insulation layer of described array base palte, and forms the opening that exposes pixel region in described gate insulation layer.
6. manufacture method as claimed in claim 5 is characterized in that, described manufacture method comprises:
Form gate electrode and grid line at substrate;
Form described gate insulation layer at the substrate that is formed with described gate electrode and grid line;
Form semiconductor layer, data line, source electrode and drain electrode at described gate insulation layer;
Form passivation layer at the substrate that is formed with described semiconductor layer, data line, source electrode and drain electrode, and form via hole at described passivation layer;
Form pixel electrode at described passivation layer, described pixel electrode is connected with described drain electrode by described via hole.
7. manufacture method as claimed in claim 6 is characterized in that, also comprises:
At described source electrode.Form ohmic contact layer between drain electrode and the semiconductor layer.
8. manufacture method as claimed in claim 5 is characterized in that:
Described black insulating material is organic material.
9. a display device is characterized in that: comprise such as each described array base palte among the claim 1-4.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2012103327355A CN102854677A (en) | 2012-09-10 | 2012-09-10 | Array substrate, production method of array substrate and display device |
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| CN2012103327355A CN102854677A (en) | 2012-09-10 | 2012-09-10 | Array substrate, production method of array substrate and display device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103199095A (en) * | 2013-04-01 | 2013-07-10 | 京东方科技集团股份有限公司 | Displayer, thin film transistor array substrate and manufacturing process thereof |
| WO2014166181A1 (en) * | 2013-04-12 | 2014-10-16 | 京东方科技集团股份有限公司 | Thin-film transistor and manufacturing method thereof, array base plate and display apparatus |
| CN109192736A (en) * | 2018-09-04 | 2019-01-11 | 京东方科技集团股份有限公司 | Thin-film transistor array base-plate and preparation method thereof, display device |
| CN109709695A (en) * | 2019-01-10 | 2019-05-03 | 京东方科技集团股份有限公司 | Display base plate and its manufacturing method, display device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6556265B1 (en) * | 1998-03-19 | 2003-04-29 | Seiko Epson Corporation | LCD having auxiliary capacitance lines and light shielding films electrically connected via contact holes |
| CN201867561U (en) * | 2010-11-09 | 2011-06-15 | 北京京东方光电科技有限公司 | Array substrate and liquid crystal display |
| CN102540591A (en) * | 2012-02-08 | 2012-07-04 | 信利半导体有限公司 | Passive matrix type liquid crystal display |
-
2012
- 2012-09-10 CN CN2012103327355A patent/CN102854677A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6556265B1 (en) * | 1998-03-19 | 2003-04-29 | Seiko Epson Corporation | LCD having auxiliary capacitance lines and light shielding films electrically connected via contact holes |
| CN201867561U (en) * | 2010-11-09 | 2011-06-15 | 北京京东方光电科技有限公司 | Array substrate and liquid crystal display |
| CN102540591A (en) * | 2012-02-08 | 2012-07-04 | 信利半导体有限公司 | Passive matrix type liquid crystal display |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103199095A (en) * | 2013-04-01 | 2013-07-10 | 京东方科技集团股份有限公司 | Displayer, thin film transistor array substrate and manufacturing process thereof |
| WO2014166181A1 (en) * | 2013-04-12 | 2014-10-16 | 京东方科技集团股份有限公司 | Thin-film transistor and manufacturing method thereof, array base plate and display apparatus |
| CN109192736A (en) * | 2018-09-04 | 2019-01-11 | 京东方科技集团股份有限公司 | Thin-film transistor array base-plate and preparation method thereof, display device |
| CN109709695A (en) * | 2019-01-10 | 2019-05-03 | 京东方科技集团股份有限公司 | Display base plate and its manufacturing method, display device |
| CN109709695B (en) * | 2019-01-10 | 2021-12-24 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method thereof and display device |
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Application publication date: 20130102 |