CN109541862A - Active switch and preparation method thereof, array substrate and display device - Google Patents
Active switch and preparation method thereof, array substrate and display device Download PDFInfo
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- CN109541862A CN109541862A CN201811465751.5A CN201811465751A CN109541862A CN 109541862 A CN109541862 A CN 109541862A CN 201811465751 A CN201811465751 A CN 201811465751A CN 109541862 A CN109541862 A CN 109541862A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
Abstract
This application involves a kind of active switch and preparation method thereof, array substrate and display devices.The active switch includes substrate；Grid is formed on the substrate；Gate insulating layer is formed on the substrate and covers the grid；Oxide semiconductor layer is formed in the top that the gate insulating layer corresponds to the grid；Source electrode, drain electrode are formed in the two sides of the oxide semiconductor layer along upper；First protective layer is formed in the source electrode, in drain electrode；Flatness layer is formed on first protective layer；Public electrode is formed in the top that the flatness layer corresponds to the grid；Electrode stabilized zone is formed on the public electrode；Wherein, the projection of the electrode stabilized zone on the substrate has overlapping with the projection of the grid on the substrate.The application can reduce the loss of aperture opening ratio by the way that the electrode stabilized zone corresponded to above grid is arranged on public electrode under the premise of guaranteeing that the current potential of public electrode is stablized.
Description
Technical field
This application involves field of display technology, more particularly to a kind of active switch and preparation method thereof, array substrate and
Display device.
Background technique
LCD (Liquid Crystal Display, liquid crystal display) panel is as most widely used display at present
One of, it can be provided for various electronic equipments such as mobile phone, personal digital assistant (PDA), digital camera and computer etc. high
Resolution color screen.Wherein FFS (Fringe Field Switching, fringe field switching technique) liquid crystal display device and
The features such as its wide viewing angle, high aperture, is liked by users.
The FFS liquid crystal display device generallyd use at present, usually may include upper substrate, lower substrate and upper and lower base plate it
Between liquid crystal layer.Pixel electrode and public electrode are wherein typically provided on lower substrate, pixel electrode and public electrode can be distinguished
For it is planar or have narrow slit structure；In order to increase penetrance, it is other that general public electrode and pixel electrode are produced on different layers.
Current design, generally can be using the pixel of one layer of metal string connection same grid line, together in order to stablize the current potential on public electrode
When make this layer of metal input COM signal, then directly contact public electrode or by borehole by way of be connected to it is public
Electrode, it is stable come the current potential for guaranteeing public electrode with this.But whether which kind of above-mentioned way of contact, can all lose aperture opening ratio.
Summary of the invention
Based on this, it is necessary to for directly contact or borehole by way of with public electrode basis caused by aperture opening ratio damage
The problem of mistake, provides a kind of active switch and preparation method thereof, array substrate and display device.
A kind of active switch, the active switch include:
Substrate；
Grid is formed on the substrate；
Gate insulating layer is formed on the substrate and covers the grid；
Oxide semiconductor layer is formed in the top that the gate insulating layer corresponds to the grid；
Source electrode, drain electrode are formed in the two sides of the oxide semiconductor layer along upper；
First protective layer is formed in the source electrode, in drain electrode；
Flatness layer is formed on first protective layer；
Public electrode is formed in the top that the flatness layer corresponds to the grid；
Electrode stabilized zone is formed on the public electrode；Wherein, the projection of the electrode stabilized zone on the substrate
Have with the projection of the grid on the substrate overlapping.
The active switch in one of the embodiments, further include:
Second protective layer is formed on the electrode stabilized zone.
The active switch in one of the embodiments, further include:
Pixel electrode is formed on second protective layer；Wherein, the pixel electrode passes through through second protection
Layer, the via hole of flatness layer and the first protective layer and the drain electrode connect.
The material of the oxide semiconductor layer is indium gallium zinc in one of the embodiments,.
In one of the embodiments, the oxide semiconductor layer with a thickness of 200 angstroms -1000 angstroms.
In one of the embodiments, the electrode stabilized zone with a thickness of 1000 angstroms -6000 angstroms.
The electrode stabilized zone includes at least one of molybdenum, titanium, aluminium and copper in one of the embodiments,.
A kind of production method of active switch, for manufacturing the aforementioned active switch, which comprises
One substrate is provided, and deposits the first metal layer on the substrate, the first metal layer is carried out at patterning
Reason forms grid；
Gate insulating layer is formed on the grid；
On the gate insulating layer deposited semiconductor layer and to the semiconductor layer perform etching with formed correspond to institute
State the oxide semiconductor layer above grid；
Depositing second metal layer on the oxide semiconductor layer performs etching to be formed and be covered the second metal layer
It is placed on source electrode, the drain electrode on oxide semiconductor layer two sides edge；
The first protective layer, flatness layer are sequentially formed in the source electrode, drain electrode；
Third metal layer is deposited on the flat laye, and the third metal layer is performed etching to be formed corresponding to described
Public electrode above grid；
The 4th metal layer is deposited on the public electrode, the 4th metal layer is performed etching to form electrode and stablize
Layer；Wherein, the projection of the electrode stabilized zone on the substrate has overlapping with the projection of the grid on the substrate.
A kind of array substrate, including display area, peripheral region and switching tube region, before the switching tube region is provided with
State the active switch.
A kind of display device, including the aforementioned array substrate.
Above-mentioned active switch by forming public electrode on flatness layer, and makes electrode stabilized zone directly and common electrical
On the one hand pole contact can guarantee that the current potential of public electrode is stablized, on the other hand, due to projection of the electrode stabilized zone on substrate
Have with projection of the grid on substrate overlapping, in other words, when light is emitted by backlight, grid can shelter from one
Point light, due to electrode stabilized zone and grid have in vertical direction it is overlapping, so light and electrode that grid blocks are stablized
The light that layer blocks just has coincidence, then, (projection and grid of the electrode stabilized zone on substrate are on substrate for setting in this way
Projection has overlapping) it can allow the transmission of influence light that electrode stabilized zone will not be excessive, to reduce the loss of aperture opening ratio.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of the active switch in an embodiment；
Fig. 2 is the production method flow diagram of the active switch in an embodiment；
Fig. 3 is the partial structure diagram formed according to step S10 in Fig. 2；
Fig. 4 is the partial structure diagram formed according to step S20 in Fig. 2；
Fig. 5 is the partial structure diagram formed according to step S30 in Fig. 2；
Fig. 6 is the partial structure diagram formed according to step S40 in Fig. 2；
Fig. 7, Fig. 8 are the partial structure diagram formed according to step S50 in Fig. 2；
Fig. 9 is the partial structure diagram formed according to step S60 in Fig. 2；
Figure 10 is the partial structure diagram formed according to step S70 in Fig. 2；
Figure 11 is the structural schematic diagram of the array substrate in an embodiment.
Specific embodiment
The application in order to facilitate understanding is described more fully the application below with reference to relevant drawings.In attached drawing
Give the optional embodiment of the application.But the application can realize in many different forms, however it is not limited to this
Embodiment described in text.On the contrary, the purpose of providing these embodiments is that making to disclosure of this application understanding
It is more thorough and comprehensive.
It should be noted that it can directly on the other element when element is referred to as " being fixed on " another element
Or there may also be elements placed in the middle.When an element is considered as " connection " another element, it, which can be, is directly connected to
To another element or it may be simultaneously present centering elements.Term as used herein " vertical ", " horizontal ", " left side ",
" right side " and similar statement for illustrative purposes only, are not meant to be the only embodiment.
Unless otherwise defined, all technical and scientific terms used herein and the technical field for belonging to the application
The normally understood meaning of technical staff is identical.The term used in the description of the present application is intended merely to description tool herein
The purpose of the embodiment of body, it is not intended that in limitation the application.
Fig. 1 is please referred to, is the structural schematic diagram of the active switch in an embodiment；The active switch may include: substrate
10, grid 20, gate insulating layer 30, oxide semiconductor layer 40, source electrode 510, drain electrode 520, the first protective layer 60, flatness layer
70, public electrode 80 and electrode stabilized zone 90.Wherein, grid 20 is formed on substrate 10；Gate insulating layer 30 is formed in substrate
On 10 and cover grid 20；Oxide semiconductor layer 40 is formed in the top that gate insulating layer 30 corresponds to grid；Source electrode 510,
Drain electrode 520 is formed in the two sides of oxide semiconductor layer 40 along upper；First protective layer 60 is formed in source electrode 510, drain electrode 520
On；Flatness layer 70 is formed on the first protective layer 60；Public electrode 80 is formed in the top that flatness layer 70 corresponds to grid 20；Electricity
Extremely stable layer 90 is formed on public electrode 80；Wherein, the projection of electrode stabilized zone 90 on the substrate 10 and grid 20 are in substrate
Projection on 10 has overlapping.
Above-described embodiment by forming public electrode on flatness layer, and makes electrode stabilized zone directly and public electrode
Contact, on the one hand can guarantee public electrode current potential stablize, on the other hand, due to projection of the electrode stabilized zone on substrate with
Projection of the grid on substrate has overlapping, and in other words, when light is emitted by backlight, grid can shelter from a part
Light, due to electrode stabilized zone and grid have in vertical direction it is overlapping, so light and electrode stabilized zone that grid blocks
The light blocked just has coincidence, then, setting (projection and grid throwing on substrate of the electrode stabilized zone on substrate in this way
Shadow has overlapping) it can allow the transmission of influence light that electrode stabilized zone will not be excessive, to reduce the loss of aperture opening ratio.
Aperture opening ratio refers to the light after the wiring part for removing each sub-pixel, tTransistor portion (generalling use black matrix" to hide)
Line passes through the ratio between the area of part and the area of each sub-pixel entirety.Aperture opening ratio is higher, the efficiency that light passes through
It is higher.When light is emitted via backlight, not all light can pass through panel, for example drive to LCD source electrode
The signal lead and thin film transistor (TFT) itself of dynamic chip and grid drive chip, there are also the storage capacitors of stored voltage
Deng.These places also due to not controlled by voltage by the light in these places, and can not be shown just other than incomplete light transmission
True grayscale, so all need to be covered using black matrix", in order to avoid interfere other transmission regions.And effective transmission region with
The ratio of entire area is just referred to as aperture opening ratio.
Substrate 10 can be glass substrate or plastic base, wherein glass substrate can be the ultra-thin glass of alkali-free borosilicate
Glass, no alkali borosilicate glass physical characteristic with higher, preferable corrosion resistance, higher thermal stability and lower
Density and higher elasticity modulus.
Grid 20 is formed on substrate 10, wherein the formation process of grid 20 may include rf magnetron sputtering, heat steaming
Hair, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.It is appreciated that the formation process of grid 20 can be with
It is selected and is adjusted according to practical situations and properties of product, be not further limited herein.The material of grid 20
It can be the heap stack combination of one or more of molybdenum, titanium, aluminium and copper；Select molybdenum, titanium, aluminium and copper can as 20 material of grid
To guarantee good electric conductivity.It is appreciated that the material of grid 20 can according to practical situations and properties of product into
Row selection and adjustment, are not further limited herein.
Gate insulating layer 30 is formed on substrate 10, and the formation process of gate insulating layer 30 may include that radio frequency magnetron splashes
It penetrates, thermal evaporation, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.It is appreciated that gate insulating layer 30
Formation process can be selected and be adjusted according to practical situations and properties of product, do not limit further herein
It is fixed.The material of gate insulating layer 30 can be one of silica, silicon nitride or combination, i.e. gate insulating layer 30
It can be silica, be also possible to silicon nitride, can also be the mixture of silica and silicon nitride.It is appreciated that gate insulator
The material of layer 30 can be selected and be adjusted according to practical situations and properties of product, not limited further herein
It is fixed.The thickness of gate insulating layer 30 can be 1000 angstroms -4000 angstroms, and optionally, the thickness of gate insulating layer 30 can be 1000
Angstroms -2500 angstroms, further, the thickness of gate insulating layer 30 can be 2500 angstroms -4000 angstroms.It is appreciated that gate insulating layer
30 thickness can be selected and be adjusted according to practical situations and properties of product, be not further limited herein.
Oxide semiconductor layer 40 is formed in the top of the corresponding grid 20 of gate insulating layer 30, in other words, oxide half
Conductor layer 40 is made only in the top opposite with grid 20.The formation process of oxide semiconductor layer 40 may include radio frequency magnetron
Sputtering, thermal evaporation, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.It is appreciated that oxide is partly led
The formation process of body layer 40 can be selected and be adjusted according to practical situations and properties of product, not made herein further
Restriction.Further, the material of oxide semiconductor layer 40 is indium gallium zinc oxide (Indium Gallium Zinc
Oxide, IGZO), use metal oxide to have the advantages that following both sides as the active layer material of thin film transistor (TFT): (1)
Forbidden band is wide (> 3.0eV), thus can bring extraordinary light durability, so, metal different from amorphous silicon film transistor
Oxide thin film transistor can be fabricated to all-transparent device, to dramatically increase the aperture opening ratio of display panel, and then reduce aobvious
The power consumption of showing device；(2) high mobility (about 10cm2/V·s).To sum up, metal oxide thin-film transistor can be simultaneously
Have the technical advantage of amorphous silicon film transistor and polycrystalline SiTFT, and there is feasibility in scale of mass production.
The thickness of oxide semiconductor layer 40 can be 200 angstroms -1000 angstroms, and optionally, the thickness of oxide semiconductor layer 40 can be
200 angstroms -600 angstroms, further, the thickness of oxide semiconductor layer 40 can be 600 angstroms -1000 angstroms.It is appreciated that oxide
The thickness of semiconductor layer 40 can be selected and be adjusted according to practical situations and properties of product, not made herein further
Restriction.
Source electrode 510 is formed in the two sides of oxide semiconductor layer 40 along upper with drain electrode 520.Source electrode 510 and drain electrode 520
Formation process may include rf magnetron sputtering, thermal evaporation, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition
Technique.It is appreciated that source electrode 510 and the formation process of drain electrode 520 can be carried out according to practical situations and properties of product
Selection and adjustment, are not further limited herein.Source electrode 510 and the material of drain electrode 520 can be in molybdenum, titanium, aluminium and copper
One or more kinds of heap stack combinations；Selection molybdenum, titanium, aluminium and copper can guarantee as source electrode 510 with 520 materials of drain electrode good
Electric conductivity.It is appreciated that source electrode 510 and the material of drain electrode 520 can be carried out according to practical situations and properties of product
Selection and adjustment, are not further limited herein.
First protective layer 60 be formed in source electrode 510, drain electrode 520 on, the formation process of the first protective layer 60 may include penetrating
Frequency magnetron sputtering, thermal evaporation, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.It is appreciated that first
The formation process of protective layer 60 can be selected and be adjusted according to practical situations and properties of product, not made herein into one
The restriction of step.The material of first protective layer 60 can be one of silica, silicon nitride or combination, i.e., first protects
Sheath 60 can be silica, be also possible to silicon nitride, can also be the mixture of silica and silicon nitride.It is appreciated that the
The material of one protective layer 60 can be selected and be adjusted according to practical situations and properties of product, not made herein further
Restriction.
Flatness layer 70 is formed on the first protective layer 60.The formation process of flatness layer 70 may include rf magnetron sputtering,
Thermal evaporation, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.It is appreciated that the formation work of flatness layer 70
Skill can be selected and be adjusted according to practical situations and properties of product, be not further limited herein.Flatness layer
70 thickness can be 2000 nanometers -3000 nanometers；Optionally, the thickness of flatness layer 70 can be 2000 nanometers -2500 nanometers；
Optionally, the thickness of flatness layer 70 can be 2500 nanometers -3000 nanometers.It is appreciated that the thickness of flatness layer 70 can basis
Practical situations and properties of product are selected and are adjusted, and are not further limited herein.
Public electrode 80 is formed in the top that flatness layer 70 corresponds to grid 20.The formation process of public electrode 80 can wrap
Include rf magnetron sputtering, thermal evaporation, vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique.It is appreciated that
The formation process of public electrode 80 can be selected and be adjusted according to practical situations and properties of product, do not make herein into
The restriction of one step.Public electrode 80 can be transparent metal oxide, and transparent metal oxide can be indium tin oxide, indium zinc
One of oxide, aluminium tin-oxide, aluminium zinc oxide, indium germanium zinc oxide are a variety of.
Electrode stabilized zone 90 is formed on public electrode 80；Wherein, the projection on the substrate 10 of electrode stabilized zone 90 and grid
The projection of pole 20 on the substrate 10 has overlapping.In other words, when light is emitted by backlight, grid 20 is due to use
Lighttight metal, so the light of a part can be sheltered from, due to electrode stabilized zone 90 and grid 20 perpendicular to
Have on the direction of substrate it is overlapping, so the light that light and electrode stabilized zone 90 that grid 20 blocks block just has coincidence, that
, (projection and grid projection on substrate of the electrode stabilized zone on substrate has overlapping) is arranged in this way can allow electrode steady
Given layer 90 will not be excessive influence light transmission, to reduce the loss of aperture opening ratio.The material of electrode stabilized zone 90 can be
The heap stack combination of one or more of molybdenum, titanium, aluminium and copper；Select molybdenum, titanium, aluminium and copper that can guarantee as 20 material of grid
Good electric conductivity.It is appreciated that the material of electrode stabilized zone 90 can according to practical situations and properties of product into
Row selection and adjustment, are not further limited herein.The thickness range of electrode stabilized zone 90 can be 1000 angstroms -6000 angstroms,
Optionally, the thickness of electrode stabilized zone 90 can be 1000 angstroms -3500 angstroms, and further, the thickness of electrode stabilized zone 90 can be with
It is 3500 angstroms -6000 angstroms.It is appreciated that the thickness of electrode stabilized zone 90 can according to practical situations and properties of product into
Row selection and adjustment, are not further limited herein.Due to accompanying flatness layer 70 between grid 20 and electrode stabilized zone 90, and
And flatness layer 70 with a thickness of 2000 nanometers -3000 nanometers, that is to say that the distance between grid and electrode stabilized zone are far, so
Load on grid line does not have too much influence.Further, since electrode stabilized zone 90 is directly contacted with public electrode 80,
So metal routing (COM signal) originally parallel with grid 20 can be saved, increase aperture opening ratio.
Referring to Fig. 2, for the production method flow diagram of the active switch in an embodiment；Before this method is for manufacturing
State the active switch；This method may include step S10-S70.
Step S10 provides a substrate, and deposits the first metal layer on the substrate, carries out to the first metal layer
Patterned process forms grid.
Specifically, it please assist refering to Fig. 3, substrate 10 can be glass substrate or plastic base, wherein glass substrate can be with
For no alkali borosilicate ultra-thin glass, no alkali borosilicate glass physical characteristic with higher, preferable corrosion resistance, compared with
High thermal stability and lower density and higher elasticity modulus.Forming the first metal layer on the substrate 10, (Fig. 3 is not marked
Show), the formation process of the first metal layer may include rf magnetron sputtering, thermal evaporation, vacuum electronic beam evaporation and plasma
Enhance chemical vapor deposition process.It is appreciated that the formation process of the first metal layer can be according to practical situations and production
Moral character can be carried out selection and adjustment, not be further limited herein.Patterned process is carried out to the first metal layer and forms grid
20.Specifically, it can be coated with one layer of photoresist layer (Fig. 3 is not indicated) in the top of the first metal layer, then uses one of light shield technique
Patterned process is carried out to photoresist layer, the photoresist (Fig. 3 is not indicated) for obtaining having predetermined pattern can be used on this basis
Wet-etching technology performs etching the first metal layer to form grid 20.
Step S20 forms gate insulating layer on the grid.
Specifically, referring to Fig. 4, forming gate insulating layer 30 on grid 20.The gate insulating layer 30 of formation is by grid
20 cover, the formation process of gate insulating layer 30 may include rf magnetron sputtering, thermal evaporation, vacuum electronic beam evaporation and
Plasma reinforced chemical vapour deposition technique.It is appreciated that the formation process of gate insulating layer 30 can be according to practical application feelings
Condition and properties of product are selected and are adjusted, and are not further limited herein.
Step S30, on the gate insulating layer deposited semiconductor layer and to the semiconductor layer perform etching with formed
Corresponding to the oxide semiconductor layer above the grid.
Specifically, it please assist refering to Fig. 5, semiconductor layer (Fig. 5 is not indicated) be formed on gate insulating layer 30, to semiconductor
Layer is performed etching to form the oxide semiconductor layer 40 for corresponding to 20 top of grid.Can by rf magnetron sputtering, thermal evaporation,
Vacuum electronic beam evaporation and plasma reinforced chemical vapour deposition technique form semiconductor layer on gate insulating layer 30, then
It is coated with one layer of photoresist layer (Fig. 5 is not indicated) in the top of semiconductor layer, figure is then carried out to photoresist layer using one of light shield technique
Caseization processing, obtains the photoresist (Fig. 5 is not indicated) with predetermined pattern, on this basis, using dry etch process to the
One metal layer is performed etching to form oxide semiconductor layer 40.The material of oxide semiconductor layer 40 can aoxidize for indium gallium zinc
Object.
Step S40, depositing second metal layer, performs etching the second metal layer on the oxide semiconductor layer
To form the source electrode for being covered in oxide semiconductor layer two sides edge, drain electrode.
Specifically, it please assist refering to Fig. 6, deposition forms second metal layer (Fig. 6 is not marked on oxide semiconductor layer 40
Show), the formation process to second metal layer may include rf magnetron sputtering, thermal evaporation, vacuum electronic beam evaporation and wait from
Son enhancing chemical vapor deposition process.It is appreciated that the formation process of second metal layer can according to practical situations and
Properties of product are selected and are adjusted, and are not further limited herein.Second metal layer is performed etching to be formed and be covered in
The source electrode 510 on 40 two sides edge of oxide semiconductor layer, drain electrode 520.Specifically, one layer can be coated in the top of second metal layer
Photoresist layer (Fig. 6 is not indicated) then carries out patterned process to photoresist layer using one of light shield technique, obtains with predetermined pattern
Photoresist (Fig. 6 is not indicated) use wet-etching technology to perform etching to form source electrode second metal layer on this basis
510, drain electrode 520, wherein source electrode 510 realizes with the side of oxide semiconductor layer 40 and be electrically connected that drain electrode 520 and oxide are partly
Realize electrical connection in the other side of conductor layer 40.
Step S50 sequentially forms the first protective layer, flatness layer in the source electrode, drain electrode.
Specifically, it please assist refering to Fig. 7, Fig. 8.It can be sequentially depositing to form the first protective layer in source electrode 510, drain electrode 520
60 and flatness layer 70, depositing operation may include rf magnetron sputtering, thermal evaporation, vacuum electronic beam evaporation and plasma enhancing
Chemical vapor deposition process.It is appreciated that the formation process of the first protective layer 60 and flatness layer 70 can be according to practical application feelings
Condition and properties of product are selected and are adjusted, and are not further limited herein.
Step S60 deposits third metal layer on the flat laye, performs etching the third metal layer with formation pair
Public electrode above grid described in Ying Yu.
Specifically, it please assist refering to Fig. 9, deposition forms third metal layer (Fig. 9 is not indicated) on flatness layer 70, to third
The formation process of metal layer may include rf magnetron sputtering, thermal evaporation, vacuum electronic beam evaporation and plasma-reinforced chemical
Gas-phase deposition.It is appreciated that the formation process of third metal layer can according to practical situations and properties of product into
Row selection and adjustment, are not further limited herein.Third metal layer is performed etching to be formed and correspond to 20 top of grid
Public electrode 80.Specifically, it can be coated with one layer of photoresist layer (Fig. 9 is not indicated) in the top of third metal layer, then uses one
Road light shield technique carries out patterned process to photoresist layer, obtains the photoresist (Fig. 9 is not indicated) with predetermined pattern, basic herein
On, use wet-etching technology to perform etching third metal layer to form the public electrode 80 for corresponding to 20 top of grid.
Step S70 deposits the 4th metal layer on the public electrode, performs etching the 4th metal layer to be formed
Electrode stabilized zone；Wherein, the projection and the projection of the grid on the substrate of the electrode stabilized zone on the substrate
Have overlapping.
Specifically, refering to fig. 10 please be assist, deposition forms the 4th metal layer (Figure 10 is not indicated) on public electrode 80, right
The formation process of 4th metal layer may include rf magnetron sputtering, thermal evaporation, vacuum electronic beam evaporation and plasma enhancing
Chemical vapor deposition process.It is appreciated that the formation process of the 4th metal layer can be according to practical situations and product
It can be carried out selection and adjustment, be not further limited herein.4th metal layer is performed etching to form electrode stabilized zone 90,
Wherein, the projection of electrode stabilized zone 90 on the substrate 10 has overlapping with the projection of grid 20 on the substrate 10.It specifically, can be
The top of four metal layers is coated with one layer of photoresist layer (Figure 10 is not indicated), then carries out pattern to photoresist layer using one of light shield technique
Change processing, obtains the photoresist (Figure 10 is not indicated) with predetermined pattern, on this basis, using wet-etching technology to the 4th
Metal layer is performed etching to form electrode stabilized zone 90.The projection of electrode stabilized zone 90 on the substrate 10 and grid 20 are in substrate 10
On projection have it is overlapping.In other words, when light is emitted by backlight, grid 20 is due to using lighttight gold
Category is made, so the light of a part can be sheltered from, in a direction perpendicular to a substrate due to electrode stabilized zone 90 and grid 20
Have it is overlapping, so the light that light and electrode stabilized zone 90 that grid 20 blocks block just has coincidence, then, be arranged in this way
(projection and grid projection on substrate of the electrode stabilized zone on substrate has overlapping) can allow electrode stabilized zone 90 will not
The transmission of excessive influence light, to reduce the loss of aperture opening ratio.
The production method of above-mentioned active switch, since the active switch manufactured on flatness layer by forming common electrical
Pole, and make electrode stabilized zone directly and common electrode contact, it on the one hand can guarantee that the current potential of public electrode is stablized, another party
Face, due to projection and grid projection on substrate of the electrode stabilized zone on substrate have it is overlapping, in other words, when light is by carrying on the back
When tabula rasa emits, grid can shelter from the light of a part, since electrode stabilized zone and grid have friendship in vertical direction
It is folded, so the light that light and electrode stabilized zone that grid blocks block just has coincidence, then, (electrode is stablized for setting in this way
Projection and grid projection on substrate of the layer on substrate has overlapping) it can allow the influence light that electrode stabilized zone will not be excessive
The transmission of line, to reduce the loss of aperture opening ratio.
Figure 11 is please referred to, is the structural schematic diagram of the array substrate in an embodiment；The array substrate may include switch
Area under control domain 1, display area 2 and peripheral region 3, wherein switching tube region 1 is provided with the aforementioned active switch.
Further, please continue to refer to Figure 11, active switch can also include the second protective layer 100 and pixel electrode
110；Wherein, the second protective layer 100 is formed on electrode stabilized zone 90；Pixel electrode 110 is formed on the second protective layer 100,
Pixel electrode 110 is connect by the via hole H1 through the second protective layer 100, flatness layer 70 and the first protective layer 60 with drain electrode 520.
Specifically, the second protective layer 100 can be one of silica, silicon nitride or combination, i.e. protection insulating layer 90
It can be silica, be also possible to silicon nitride, can also be the mixture of silica and silicon nitride.It is appreciated that the second protection
The material of layer 100 can be selected and be adjusted according to practical situations and properties of product, not limited further herein
It is fixed.The formation process of pixel electrode 100 may include rf magnetron sputtering, thermal evaporation, vacuum electronic beam evaporation and plasma
Enhance chemical vapor deposition process.It is appreciated that the formation process of pixel electrode 100 can be according to practical situations and production
Moral character can be carried out selection and adjustment, not be further limited herein.Pixel electrode 100 can be indium tin oxide, indium zinc oxygen
One of compound, aluminium tin-oxide, aluminium zinc oxide, indium germanium zinc oxide are a variety of.Pixel electrode 110 and drain electrode 520 are logical
Cross the via hole H1 electrical connection through the second protective layer 100, flatness layer 70 and the first protective layer 60." running through " can pass through photoetching or quarter
Etching technique is formed, specifically, photoetching, which refers to, makes light by exposure and imaging using the mask with a certain layer design configuration
Three-dimensional relief pattern is formed on the substrate in quick photoresist.Etching refers under photoresist masking, forms micrographics as needed
Film layer it is different, selective etch is carried out in film layer using different etching substances and method.In this way, remove photoresist with
Afterwards, three dimensional design figure has been transferred in the related film layer of substrate.
Above-mentioned array substrate, since using the aforementioned active switch, the active switch on flatness layer by forming
Public electrode, and make electrode stabilized zone directly and common electrode contact, it on the one hand can guarantee that the current potential of public electrode is stablized,
On the other hand, the projection of projection and grid on substrate due to electrode stabilized zone on substrate has overlapping, in other words, works as light
When line is emitted by backlight, grid can shelter from the light of a part, since electrode stabilized zone and grid are in vertical direction
On have it is overlapping, so the light that light and electrode stabilized zone that grid blocks block just has coincidence, then, setting (electricity in this way
Projection and grid projection on substrate of the extremely stable layer on substrate has overlapping) it can allow what electrode stabilized zone will not be excessive
The transmission for influencing light, to reduce the loss of aperture opening ratio.
A kind of display device is also provided, including the aforementioned array substrate, the array substrate is due to using aforementioned described
Active switch, which makes electrode stabilized zone directly and common electrical by forming public electrode on flatness layer
On the one hand pole contact can guarantee that the current potential of public electrode is stablized, on the other hand, due to projection of the electrode stabilized zone on substrate
Have with projection of the grid on substrate overlapping, in other words, when light is emitted by backlight, grid can shelter from one
Point light, due to electrode stabilized zone and grid have in vertical direction it is overlapping, so light and electrode that grid blocks are stablized
The light that layer blocks just has coincidence, then, (projection and grid of the electrode stabilized zone on substrate are on substrate for setting in this way
Projection has overlapping) it can allow the transmission of influence light that electrode stabilized zone will not be excessive, to reduce the loss of aperture opening ratio.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The several embodiments of the application above described embodiment only expresses, the description thereof is more specific and detailed, but simultaneously
The limitation to claim therefore cannot be interpreted as.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the concept of this application, various modifications and improvements can be made, these belong to the protection of the application
Range.Therefore, the scope of protection shall be subject to the appended claims for the application patent.
Claims (10)
1. a kind of active switch, which is characterized in that the active switch includes:
Substrate；
Grid is formed on the substrate；
Gate insulating layer is formed on the substrate and covers the grid；
Oxide semiconductor layer is formed in the top that the gate insulating layer corresponds to the grid；
Source electrode, drain electrode are formed in the two sides of the oxide semiconductor layer along upper；
First protective layer is formed in the source electrode, in drain electrode；
Flatness layer is formed on first protective layer；
Public electrode is formed in the top that the flatness layer corresponds to the grid；
Electrode stabilized zone is formed on the public electrode；Wherein, electrode stabilized zone projection on the substrate and institute
State the projection of grid on the substrate have it is overlapping.
2. active switch according to claim 1, which is characterized in that further include:
Second protective layer is formed on the electrode stabilized zone.
3. active switch according to claim 2, which is characterized in that further include:
Pixel electrode is formed on second protective layer；Wherein, the pixel electrode by through second protective layer,
The via hole of flatness layer and the first protective layer and the drain electrode connect.
4. active switch according to claim 1, which is characterized in that the material of the oxide semiconductor layer is indium oxide
Gallium zinc.
5. active switch according to claim 1, which is characterized in that the oxide semiconductor layer with a thickness of 200 angstroms-
1000 angstroms.
6. active switch according to claim 1, which is characterized in that the electrode stabilized zone with a thickness of 1000 angstroms-
6000 angstroms.
7. active switch according to claim 1, which is characterized in that the electrode stabilized zone includes in molybdenum, titanium, aluminium and copper
At least one.
8. a kind of production method of active switch, which is characterized in that for manufacturing such as the described in any item actives of claim 1-7
Switch, which comprises
One substrate is provided, and deposits the first metal layer on the substrate, patterned process shape is carried out to the first metal layer
At grid；
Gate insulating layer is formed on the grid；
On the gate insulating layer deposited semiconductor layer and to the semiconductor layer perform etching with formed correspond to the grid
Oxide semiconductor layer above pole；
Depositing second metal layer on the oxide semiconductor layer performs etching to be formed and be covered in the second metal layer
The source electrode on oxide semiconductor layer two sides edge, drain electrode；
The first protective layer, flatness layer are sequentially formed in the source electrode, drain electrode；
Third metal layer is deposited on the flat laye, and the third metal layer is performed etching to be formed and correspond to the grid
The public electrode of top；
The 4th metal layer is deposited on the public electrode, and the 4th metal layer is performed etching to form electrode stabilized zone；
Wherein, the projection of the electrode stabilized zone on the substrate has overlapping with the projection of the grid on the substrate.
9. a kind of array substrate, including display area, peripheral region and switching tube region, which is characterized in that the switch area under control
Domain is arranged just like the described in any item active switches of claim 1-7.
10. a kind of display device, which is characterized in that including array substrate as claimed in claim 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811465751.5A CN109541862A (en) | 2018-12-03 | 2018-12-03 | Active switch and preparation method thereof, array substrate and display device |
| PCT/CN2018/120136 WO2020113599A1 (en) | 2018-12-03 | 2018-12-10 | Active switch and manufacturing method thereof, and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811465751.5A CN109541862A (en) | 2018-12-03 | 2018-12-03 | Active switch and preparation method thereof, array substrate and display device |
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| CN109541862A true CN109541862A (en) | 2019-03-29 |
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| CN112612161A (en) * | 2020-12-11 | 2021-04-06 | 惠科股份有限公司 | Display panel, manufacturing method thereof and display device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103176302A (en) * | 2011-12-22 | 2013-06-26 | 乐金显示有限公司 | Liquid crystal display device and method for manufaturing the same |
| CN103353699A (en) * | 2013-06-24 | 2013-10-16 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
| CN103838044A (en) * | 2014-02-26 | 2014-06-04 | 京东方科技集团股份有限公司 | Substrate, manufacturing method of substrate and display device |
| US20160126255A1 (en) * | 2014-10-31 | 2016-05-05 | Samsung Dispaly Co., Ltd. | Display substrate and method of manufacturing the same |
| CN106292100A (en) * | 2015-05-28 | 2017-01-04 | 鸿富锦精密工业（深圳）有限公司 | Array base palte and there is the display panels of this array base palte |
| CN107678222A (en) * | 2016-08-01 | 2018-02-09 | 三星显示有限公司 | Display panel and its manufacture method |
| CN108305879A (en) * | 2018-01-31 | 2018-07-20 | 昆山龙腾光电有限公司 | Thin-film transistor array base-plate and production method and display device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9036114B2 (en) * | 2012-06-01 | 2015-05-19 | Semiconductor Energy Laboratory Co., Ltd. | Polymer/liquid crystal composite and liquid crystal display device including the same |
| CN203299499U (en) * | 2013-06-24 | 2013-11-20 | 京东方科技集团股份有限公司 | Array substrate and display device |
| KR102162888B1 (en) * | 2013-06-27 | 2020-10-08 | 엘지디스플레이 주식회사 | Liquid crystal display array substrate and method for manufacturing of the same |
| CN103345092B (en) * | 2013-07-08 | 2017-03-29 | 合肥京东方光电科技有限公司 | Array base palte and preparation method thereof, display device |
| CN109087921A (en) * | 2018-08-15 | 2018-12-25 | 京东方科技集团股份有限公司 | Array substrate and its manufacturing method, display device |
-
2018
- 2018-12-03 CN CN201811465751.5A patent/CN109541862A/en active Pending
- 2018-12-10 WO PCT/CN2018/120136 patent/WO2020113599A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103176302A (en) * | 2011-12-22 | 2013-06-26 | 乐金显示有限公司 | Liquid crystal display device and method for manufaturing the same |
| CN103353699A (en) * | 2013-06-24 | 2013-10-16 | 京东方科技集团股份有限公司 | Array substrate, preparation method thereof and display device |
| CN103838044A (en) * | 2014-02-26 | 2014-06-04 | 京东方科技集团股份有限公司 | Substrate, manufacturing method of substrate and display device |
| US20160126255A1 (en) * | 2014-10-31 | 2016-05-05 | Samsung Dispaly Co., Ltd. | Display substrate and method of manufacturing the same |
| CN106292100A (en) * | 2015-05-28 | 2017-01-04 | 鸿富锦精密工业（深圳）有限公司 | Array base palte and there is the display panels of this array base palte |
| CN107678222A (en) * | 2016-08-01 | 2018-02-09 | 三星显示有限公司 | Display panel and its manufacture method |
| CN108305879A (en) * | 2018-01-31 | 2018-07-20 | 昆山龙腾光电有限公司 | Thin-film transistor array base-plate and production method and display device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112612161A (en) * | 2020-12-11 | 2021-04-06 | 惠科股份有限公司 | Display panel, manufacturing method thereof and display device |
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|---|---|
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Application publication date: 20190329 |