CN105914237A - Thin-film transistor, manufacturing method thereof, array substrate and display device - Google Patents
Thin-film transistor, manufacturing method thereof, array substrate and display device Download PDFInfo
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- CN105914237A CN105914237A CN201610383556.2A CN201610383556A CN105914237A CN 105914237 A CN105914237 A CN 105914237A CN 201610383556 A CN201610383556 A CN 201610383556A CN 105914237 A CN105914237 A CN 105914237A
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- ohmic contact
- film transistor
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- tft
- layer
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- 239000010409 thin film Substances 0.000 title claims abstract description 80
- 239000000758 substrate Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000010410 layer Substances 0.000 claims abstract description 104
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 32
- 239000000463 material Substances 0.000 claims abstract description 18
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 17
- 239000011229 interlayer Substances 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 64
- 238000000059 patterning Methods 0.000 claims description 28
- 229910021419 crystalline silicon Inorganic materials 0.000 claims description 21
- 239000010408 film Substances 0.000 claims description 18
- 239000012212 insulator Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 8
- 238000005224 laser annealing Methods 0.000 claims description 5
- 229920005591 polysilicon Polymers 0.000 claims description 5
- 238000004544 sputter deposition Methods 0.000 claims description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical group [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 125000004429 atom Chemical group 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- -1 grid Substances 0.000 claims description 2
- 125000004437 phosphorous atom Chemical group 0.000 claims description 2
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 3
- 230000009286 beneficial effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 7
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 238000000137 annealing Methods 0.000 description 3
- 238000002360 preparation method Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910003978 SiClx Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Abstract
The invention discloses a thin-film transistor, a manufacturing method thereof, an array substrate and a display device, relates to the technical field of display and solves the technical problem that the manufacturing process of a low-temperature polycrystalline silicon thin-film transistor is complex. An active layer provided by the thin-film transistor comprises two ohmic contact parts and a channel part. One end of the channel part is overlapped on one end of one ohmic contact part, and the other end of the channel part is overlapped on one end of the other ohmic contact part. The material of the channel part is low-temperature polycrystalline silicon. The material of the ohmic contact parts is doped amorphous silicon. The thin-film transistor further comprises a first through hole and a second through hole which respectively penetrate through an interlayer insulating layer and a grid insulating layer, wherein the first through hole is corresponding to one ohmic contact part, the second through hole is corresponding to the other ohmic contact part, a source electrode is connected with one ohmic contact part through the first through hole, and a drain electrode is connected with the other ohmic contact part through a second through hole. The thin-film transistor is applied to a liquid crystal display.
Description
Technical field
The present invention relates to Display Technique field, particularly relate to a kind of thin film transistor (TFT) and preparation method thereof, array
Substrate and display device.
Background technology
Owing to the atomic rule in low temperature polycrystalline silicon arranges, carrier mobility is high, therefore, at present, generally
The material making the active layer in thin film transistor (TFT) is low temperature polycrystalline silicon, and then can be effectively improved thin film transistor (TFT)
Performance, and also be conducive to reducing the volume of thin film transistor (TFT), increase aperture opening ratio.
Exemplarily, the material of active layer is that the manufacturing process of thin film transistor (TFT) of low temperature polycrystalline silicon is as follows: first
First, underlay substrate forms one layer of non-crystalline silicon；Secondly, this amorphous silicon layer is processed, forms one layer
Low temperature polycrystalline silicon, forms the figure including active layer through patterning processes；Again, gate insulator is sequentially formed
Layer, grid and interlayer insulating film；Then on interlayer insulating film and gate insulator, etching is formed corresponding to source
Pole and the contact hole of drain electrode, make low temperature polycrystalline silicon expose；Finally, source electrode and drain electrode, source electrode and drain electrode are formed
Contacted with low temperature polycrystalline silicon by contact hole, thus form thin film transistor (TFT).Further, thin in order to reduce
Contact resistance between the source electrode of film transistor, drain electrode and active layer, the manufacturing process of thin film transistor (TFT) is also wrapped
Include: forming low-temperature polycrystalline silicon layer, and after patterning processes formation includes the figure of active layer, also needing
Doping to be used (doping) technique is doped to the two ends of active layer, and carries out after doping quickly
Heat up annealing, thus form two ohmic contact at the two ends of active layer.
Inventors herein have recognized that, although above-mentioned manufacturing process can effectively reduce thin film transistor (TFT) source electrode,
Contact resistance between drain electrode and active layer, improves the performance of thin film transistor (TFT), but can make low temperature polycrystalline silicon
The complex manufacturing technology of thin film transistor (TFT).
Summary of the invention
It is an object of the invention to provide a kind of thin film transistor (TFT) and preparation method thereof, array base palte and display dress
Put, for simplifying the processing technology of thin film transistor (TFT).
For reaching above-mentioned purpose, the present invention provides a kind of thin film transistor (TFT), adopts the following technical scheme that
This thin film transistor (TFT) includes underlay substrate, and be cascadingly set on described underlay substrate active
Layer, gate insulator, grid, interlayer insulating film, the source electrode arranged with layer and drain electrode, described active layer bag
Including two ohmic contact and a groove, one end of described groove rides over a described Ohmic contact
On the one end in portion, the other end of described groove rides on one end of another described ohmic contact, described
The material of groove is low temperature polycrystalline silicon, and the material of described ohmic contact is the non-crystalline silicon of doping；Described thin
Film transistor also includes all running through described interlayer insulating film and the first via of described gate insulator and the second mistake
Hole, wherein, described first via is corresponding with a described ohmic contact, described second via and another
Described ohmic contact is corresponding, and described source electrode is connected by described first via and a described ohmic contact,
Described drain electrode is connected with ohmic contact another described by described second via.
The invention provides a kind of as above thin film transistor (TFT), active due in above-mentioned thin film transistor (TFT)
Layer has structures described above, therefore, in the manufacturing process of above-mentioned thin film transistor (TFT), only need to be initially formed
The amorphous silicon layer of one layer of doping, forms two ohmic contact through patterning processes, then forms low temperature polycrystalline silicon
Layer, forms groove through patterning processes, can complete the making of active layer in thin film transistor (TFT), and show
Have in technology, need to be initially formed low-temperature polycrystalline silicon layer, and form the figure including active layer through patterning processes
Afterwards, use doping technique, the two ends of active layer are doped, and the most quickly rise
Temperature annealing, just can complete the making of active layer in thin film transistor (TFT).As can be seen here, have in the present invention
The processing technology of the thin film transistor (TFT) of structure is the simplest.
Further, present invention also offers a kind of array base palte, this array base palte includes above-mentioned film crystal
Pipe.
The thin film transistor (TFT) included due to this array base palte has said structure, therefore, and above-mentioned array base palte
Beneficial effect is identical with the beneficial effect of above-mentioned thin film transistor (TFT), so place no longer repeats.
Further, present invention also offers a kind of display device, this display device includes above-mentioned array base palte.
Owing to this display device includes above-described array base palte, and this array base palte includes above-described
Thin film transistor (TFT), therefore, the beneficial effect phase of the beneficial effect of above-mentioned display device and above-mentioned thin film transistor (TFT)
With, so place no longer repeats.
Additionally, present invention also offers the manufacture method of a kind of thin film transistor (TFT), adopt the following technical scheme that
The manufacture method of this thin film transistor (TFT) includes:
One underlay substrate is provided；
Described underlay substrate is formed the amorphous silicon layer of doping, is formed with two of active layer through patterning processes
The figure of ohmic contact；
Form low-temperature polycrystalline silicon layer, be formed with the figure of the groove of active layer, wherein, institute through patterning processes
The one end stating groove rides on one end of a described ohmic contact, and the other end of described groove rides over
On one end of another described ohmic contact；
On the underlay substrate of the figure of the figure and described groove that define said two ohmic contact,
Form gate insulator；
On described gate insulator, form gate metal layer, form the figure including grid through patterning processes
Shape；
Form interlayer insulating film, formed through patterning processes and all run through described interlayer insulating film and described grid is exhausted
First via of edge layer and the second via, wherein, described first via is corresponding with a described ohmic contact,
Described second via is corresponding with ohmic contact another described；
Form source-drain electrode metal level, form the figure including source electrode and drain electrode, wherein, institute through patterning processes
Stating source electrode to be connected by described first via and a described ohmic contact, described drain electrode is by described second
Via is connected with ohmic contact another described.
The invention provides the manufacture method of a kind of thin film transistor (TFT) as above, use above-mentioned thin film brilliant
When the manufacture method of body pipe makes thin film transistor (TFT), only need to be initially formed the amorphous silicon layer of one layer of doping, through structure
Figure technique forms two ohmic contact, then forms low-temperature polycrystalline silicon layer, forms groove through patterning processes
The making of active layer in thin film transistor (TFT) can be completed, and in prior art, need to be initially formed low-temperature polysilicon
Silicon layer, and after patterning processes formation includes the figure of active layer, use doping technique, to active
The two ends of layer are doped, and carry out RTA after doping, just can complete in thin film transistor (TFT)
The making of active layer.As can be seen here, when using the manufacture method of thin film transistor (TFT) in the present invention, make
Technique is the simplest.
Accompanying drawing explanation
In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to enforcement
In example description, the required accompanying drawing used is briefly described, it should be apparent that, the accompanying drawing in describing below is only
It is only some embodiments of the present invention, for those of ordinary skill in the art, is not paying creative labor
On the premise of Dong, it is also possible to obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the schematic diagram of the thin film transistor (TFT) in the embodiment of the present invention；
Fig. 2 is the schematic diagram of the structure formed after step S2 terminates in the embodiment of the present invention；
Fig. 3 is the schematic diagram of the structure formed after step S3 terminates in the embodiment of the present invention；
Fig. 4 is the schematic diagram of the structure formed after step S4 terminates in the embodiment of the present invention；
Fig. 5 is the schematic diagram of the structure formed after step S5 terminates in the embodiment of the present invention；
Fig. 6 is the schematic diagram of the structure formed after step S6 terminates in the embodiment of the present invention；
Fig. 7 is the schematic diagram of the thin film transistor (TFT) formed after step S7 terminates in the embodiment of the present invention.
Description of reference numerals:
1 underlay substrate, 2 active layers, 21 ohmic contact, 22 grooves, 3 gate insulators,
4 grids, 5 interlayer insulating films, 6 source electrodes, 7 drain electrodes, 8 first vias,
9 second vias, 10 cushions.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clearly
Chu, it is fully described by, it is clear that described embodiment is a part of embodiment of the present invention rather than all
Embodiment.Based on the embodiment in the present invention, those of ordinary skill in the art are not making creative labor
The every other embodiment obtained under dynamic premise, broadly falls into the scope of protection of the invention.
Embodiment one
The embodiment of the present invention provides a kind of thin film transistor (TFT), as it is shown in figure 1, this thin film transistor (TFT) includes substrate
Substrate 1, and be cascadingly set on underlay substrate 1 active layer 2, gate insulator 3, grid 4,
Interlayer insulating film 5, the source electrode 6 arranged with layer and drain electrode 7, wherein, active layer 2 includes two Ohmic contact
Portion 21 and a groove 22, one end of groove 22 rides on one end of an ohmic contact 21,
The other end of groove 22 rides on one end of another ohmic contact 21, and the material of groove 22 is low
Temperature polysilicon, the material of ohmic contact 21 is the non-crystalline silicon of doping；Thin film transistor (TFT) also includes all running through layer
Between insulating barrier 5 and the first via 8 and the second via 9 of gate insulator 3, wherein, the first via 8 and
Individual ohmic contact 21 is corresponding, and the second via 9 is corresponding with another ohmic contact 21, and source electrode 6 passes through
First via 8 is connected with an ohmic contact 21, and drain electrode 7 is connect with another ohm by the second via 9
Contact portion 21 connects.
In the technical scheme of the embodiment of the present invention, owing to this thin film transistor (TFT) has said structure, therefore,
In the manufacturing process of above-mentioned thin film transistor (TFT), only need to be initially formed the amorphous silicon layer of one layer of doping, through composition
Technique forms two ohmic contact 21, then forms low-temperature polycrystalline silicon layer, forms groove through patterning processes
22, the making of active layer 2 in thin film transistor (TFT) can be completed, and in prior art, need to be initially formed low
Temperature polysilicon layer, and after patterning processes formation includes the figure of active layer, use doping technique,
The two ends of active layer are doped, and carry out RTA after doping, just can complete thin film brilliant
The making of the active layer in body pipe.As can be seen here, there is the thin film transistor (TFT) of structure in the embodiment of the present invention
Processing technology the simplest.
Additionally, in the manufacturing process of thin film transistor (TFT) in embodiments of the present invention, it is not necessary in prior art
Equally low temperature polycrystalline silicon is doped, and then without using doping equipment, therefore, there is the present invention real
The cost of manufacture of the thin film transistor (TFT) executing structure in example is relatively low.
Exemplarily, the material of above-mentioned ohmic contact 21 can be non-crystalline silicon or the p-type doping of n-type doping
Non-crystalline silicon.When the non-crystalline silicon that material is n-type doping of ohmic contact 21, in ohmic contact 21
Impurity can be phosphorus atoms and/or arsenic atom；When the non-crystalline silicon that the material of ohmic contact 21 is p-type doping
Time, the impurity in ohmic contact 21 can be boron atom and/or sow atom.It should be noted that for Europe
The material of nurse contact site 21 is non-crystalline silicon or the non-crystalline silicon of n-type doping of p-type doping, and wherein impurity
Concrete kind and doping, those skilled in the art can select according to actual needs, not enter
Row limits.
Preferably, as it is shown in figure 1, above-mentioned thin film transistor (TFT) can also include being arranged at underlay substrate 1 and having
Cushion 10 between active layer 2.Underlay substrate 1 can be completely cut off by cushion 10 with active layer 2, it is to avoid lining
Impurity in substrate 1 enters active layer 2, affects the performance of active layer 2, and in the making of active layer 2
During, cushion 10 also can reduce the thermal diffusion between non-crystalline silicon and underlay substrate 2, reduces quasi-molecule and swashs
The temperature impact on underlay substrate 2 in photo-annealing technical process.Wherein, the material of cushion 10 can be nitrogen
SiClx and/or silicon oxide.
It addition, additionally provide a kind of array base palte in the embodiment of the present invention, this array base palte includes above-mentioned thin film
Transistor.Wherein, other structures that array base palte includes are same as the prior art, and those skilled in the art can
To be configured based on prior art, the most no longer repeat.Owing to this array base palte includes having above-mentioned
The thin film transistor (TFT) of structure, therefore, the beneficial effect of above-mentioned array base palte is useful with above-mentioned thin film transistor (TFT)
Effect is identical, so place no longer repeats.
Additionally, additionally provide a kind of display device in the embodiment of the present invention, this display device includes above-mentioned array
Substrate.Similarly, other structures that display device includes are the most same as the prior art, those skilled in the art
Can be configured based on prior art, the most no longer repeat.Alternatively, above-mentioned display device is permissible
For: liquid crystal panel, Electronic Paper, LCD TV, liquid crystal display, DPF, mobile phone, panel computer
Etc. any product with display function or parts.Owing to this display device includes above array base palte, and should
Array base palte includes above-described thin film transistor (TFT), and therefore, the beneficial effect of above-mentioned display device is with above-mentioned
The beneficial effect of thin film transistor (TFT) is identical, the most no longer repeats.
Embodiment two
The embodiment of the present invention provides the manufacture method of a kind of thin film transistor (TFT), the manufacture method of this thin film transistor (TFT)
In order to make the thin film transistor (TFT) described in the embodiment of the present invention one, specifically, the making of this thin film transistor (TFT)
Method includes:
Step S1, provide a underlay substrate.
Step S2, on underlay substrate, form the amorphous silicon layer of doping, be formed with active layer through patterning processes
The figure of two ohmic contact.Step S2 forms structure as shown in Figure 2 after terminating.Exemplarily, originally
Inventive embodiments can be formed on underlay substrate the amorphous silicon layer of doping by methods such as sputterings.Need
Bright, if no special instructions, the patterning processes in the embodiment of the present invention all include coat photoresist, mask,
Exposure, development and the step of stripping photoresist.
Step S3, formation low-temperature polycrystalline silicon layer, be formed with the figure of the groove of active layer through patterning processes,
Wherein, one end of groove rides on one end of an ohmic contact, and the other end of groove rides over another
On one end of individual ohmic contact.Step S3 forms structure as shown in Figure 3 after terminating.
Exemplarily, the step forming low-temperature polycrystalline silicon layer specifically includes:
Step S31, on the underlay substrate of figure defining two ohmic contact, form one layer of non-crystalline silicon
Layer.
Step S32, amorphous silicon layer is processed, make non-crystalline silicon be converted into low temperature polycrystalline silicon.Wherein, to non-
Crystal silicon layer processes, and the method making non-crystalline silicon be converted into low temperature polycrystalline silicon has a variety of, the most one by one
Enumerate.Inventors herein have recognized that, the crystalline substance of low temperature polycrystalline silicon prepared by use quasi-molecule laser annealing technique
Grain is big, spatial selectivity is good, intracrystalline imperfection is few, electrology characteristic is good, and quasi-molecule laser annealing technique is to lining
The temperature impact of substrate is less, therefore, in the embodiment of the present invention, quasi-molecule laser annealing work is preferably used
Amorphous silicon layer is processed by skill, makes non-crystalline silicon be converted into low temperature polycrystalline silicon.
Step S4, on the underlay substrate of the figure of the figure and groove that define two ohmic contact,
Form gate insulator.Step S4 forms structure as shown in Figure 4 after terminating.Exemplarily, the present invention is real
Execute methods such as can using plasma enhanced chemical vapor deposition in example and form gate insulator.
Step S5, on gate insulator, formed gate metal layer, through patterning processes formed include grid
Figure.Step S5 forms structure as shown in Figure 5 after terminating.Exemplarily, can in the embodiment of the present invention
To use the methods such as sputtering or evaporation to form gate metal layer.
Step S6, form interlayer insulating film, formed through patterning processes and all run through interlayer insulating film and grid is exhausted
First via of edge layer and the second via, wherein, the first via is corresponding with an ohmic contact, the second mistake
Hole is corresponding with another ohmic contact.Step S6 forms structure as shown in Figure 6 after terminating.Exemplarily,
The embodiment of the present invention can use the methods such as plasma enhanced chemical vapor deposition form interlayer insulating film.
Step S7, formation source-drain electrode metal level, form the figure including source electrode and drain electrode through patterning processes,
Wherein, source electrode is connected with ohmic contact by the first via, drain electrode by the second via and another
Ohmic contact connects, so that have good Ohmic contact between source electrode, drain electrode and active layer, makes
Thin film transistor (TFT) has good performance.Step S7 forms thin film transistor (TFT) as shown in Figure 7 after terminating.Show
Example ground, can use the methods such as sputtering or evaporation to form source-drain electrode metal level in the embodiment of the present invention.
Additionally, in the embodiment of the present invention, preferably form buffering between underlay substrate and the amorphous silicon layer of doping
Layer.Underlay substrate can be completely cut off by cushion with active layer, it is to avoid the impurity in underlay substrate enters active layer,
Affect the performance of active layer, additionally can reduce the thermal diffusion between non-crystalline silicon and underlay substrate, reduce standard point
The temperature impact on underlay substrate during sub-laser annealing technique.
In embodiments of the present invention, when using the manufacture method of above-mentioned thin film transistor (TFT) to make thin film transistor (TFT),
Only need to be initially formed the amorphous silicon layer of one layer of doping, form two ohmic contact through patterning processes, then formed
Low-temperature polycrystalline silicon layer, forms groove through patterning processes and can complete the system of the active layer in thin film transistor (TFT)
Make, and in prior art, need to be initially formed low-temperature polycrystalline silicon layer, and include active through patterning processes formation
After the figure of layer, use doping technique, the two ends of active layer are doped, and enter after doping
Row RTA, just can complete the making of active layer in thin film transistor (TFT).As can be seen here, this is used
During the manufacture method of the thin film transistor (TFT) in invention, processing technology is the simplest.
The above, the only detailed description of the invention of the present invention, but protection scope of the present invention is not limited to
This, any those familiar with the art, in the technical scope that the invention discloses, can readily occur in
Change or replacement, all should contain within protection scope of the present invention.Therefore, protection scope of the present invention should
It is as the criterion with described scope of the claims.
Claims (10)
1. a thin film transistor (TFT), including underlay substrate, and is cascadingly set on described underlay substrate
Active layer, gate insulator, grid, interlayer insulating film, with layer arrange source electrode and drain electrode, its feature
Being, described active layer includes two ohmic contact and a groove, and one end of described groove is taken
On one end of a described ohmic contact, the other end of described groove rides over another described ohm and connects
On one end of contact portion, the material of described groove is low temperature polycrystalline silicon, and the material of described ohmic contact is for mixing
Miscellaneous non-crystalline silicon；Described thin film transistor (TFT) also includes all running through described interlayer insulating film and described gate insulator
The first via and the second via, wherein, described first via is corresponding with a described ohmic contact, institute
Stating the second via corresponding with ohmic contact another described, described source electrode is by described first via and one
Described ohmic contact connects, and described drain electrode is by described second via with another described ohmic contact even
Connect.
Thin film transistor (TFT) the most according to claim 1, it is characterised in that the material of described ohmic contact
Matter is non-crystalline silicon or the non-crystalline silicon of p-type doping of n-type doping.
Thin film transistor (TFT) the most according to claim 2, it is characterised in that
When the non-crystalline silicon that material is n-type doping of described ohmic contact, miscellaneous in described ohmic contact
Matter is phosphorus atoms and/or arsenic atom；
When the non-crystalline silicon that the material of described ohmic contact is p-type doping, miscellaneous in described ohmic contact
Matter is boron atom and/or sows atom.
Thin film transistor (TFT) the most according to claim 1, it is characterised in that described thin film transistor (TFT) also wraps
Include the cushion being arranged between described underlay substrate and described active layer.
5. an array base palte, it is characterised in that include that the thin film as described in any one of Claims 1 to 4 is brilliant
Body pipe.
6. a display device, it is characterised in that include array base palte as claimed in claim 5.
7. the manufacture method of a thin film transistor (TFT), it is characterised in that including:
One underlay substrate is provided；
Described underlay substrate is formed the amorphous silicon layer of doping, is formed with two of active layer through patterning processes
The figure of ohmic contact；
Form low-temperature polycrystalline silicon layer, be formed with the figure of the groove of active layer, wherein, institute through patterning processes
The one end stating groove rides on one end of a described ohmic contact, and the other end of described groove rides over
On one end of another described ohmic contact；
On the underlay substrate of the figure of the figure and described groove that define said two ohmic contact,
Form gate insulator；
On described gate insulator, form gate metal layer, form the figure including grid through patterning processes
Shape；
Form interlayer insulating film, formed through patterning processes and all run through described interlayer insulating film and described grid is exhausted
First via of edge layer and the second via, wherein, described first via is corresponding with a described ohmic contact,
Described second via is corresponding with ohmic contact another described；
Form source-drain electrode metal level, form the figure including source electrode and drain electrode, wherein, institute through patterning processes
Stating source electrode to be connected by described first via and a described ohmic contact, described drain electrode is by described second
Via is connected with ohmic contact another described.
The manufacture method of thin film transistor (TFT) the most according to claim 7, it is characterised in that by sputtering
Mode on described underlay substrate, form the amorphous silicon layer of doping.
The manufacture method of thin film transistor (TFT) the most according to claim 7, it is characterised in that form low temperature
The step of polysilicon layer specifically includes:
On the underlay substrate of figure defining two described ohmic contact, form one layer of amorphous silicon layer；
Use quasi-molecule laser annealing technique that described amorphous silicon layer is processed, make non-crystalline silicon be converted into low temperature
Polysilicon.
The manufacture method of thin film transistor (TFT) the most according to claim 7, it is characterised in that described thin
The manufacture method of film transistor also includes: formed between the amorphous silicon layer of described underlay substrate and described doping
Cushion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610383556.2A CN105914237A (en) | 2016-06-01 | 2016-06-01 | Thin-film transistor, manufacturing method thereof, array substrate and display device |
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| CN109727999A (en) * | 2019-01-02 | 2019-05-07 | 合肥京东方显示技术有限公司 | Preparation method, array substrate and the display device of array substrate |
| CN109920845A (en) * | 2019-03-20 | 2019-06-21 | 京东方科技集团股份有限公司 | Array substrate and its manufacturing method, display panel, display device |
| CN110416286A (en) * | 2019-07-30 | 2019-11-05 | 京东方科技集团股份有限公司 | A kind of display panel, its production method and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109727999A (en) * | 2019-01-02 | 2019-05-07 | 合肥京东方显示技术有限公司 | Preparation method, array substrate and the display device of array substrate |
| CN109727999B (en) * | 2019-01-02 | 2020-07-03 | 合肥京东方显示技术有限公司 | Preparation method of array substrate, array substrate and display device |
| CN109920845A (en) * | 2019-03-20 | 2019-06-21 | 京东方科技集团股份有限公司 | Array substrate and its manufacturing method, display panel, display device |
| CN110416286A (en) * | 2019-07-30 | 2019-11-05 | 京东方科技集团股份有限公司 | A kind of display panel, its production method and display device |
| CN110416286B (en) * | 2019-07-30 | 2023-07-18 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
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