JP2021184465A - Semiconductor device - Google Patents

Abstract

To provide a transistor using an oxide semiconductor film which reduces contact resistance between an oxide semiconductor film and a metal film and has excellent on-state characteristics.SOLUTION: A semiconductor device has a pair of electrodes on an insulating surface, an oxide semiconductor film provided in contact with the pair of electrodes, a gate insulation film on the oxide semiconductor film and a gate electrode which overlaps the oxide semiconductor film via the gate insulation film, in which the pair of electrode contains a halogen element in a region contacting the oxide semiconductor film. In addition, a plasma treatment in a fluorine-containing atmosphere can be used as a method of impregnating the region of the pair of electrodes, which contacts the oxide semiconductor film with the halogen element.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

In the present specification, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics, and the electro-optical device, the semiconductor circuit, and the electronic device are all semiconductor devices.

Silicon-based semiconductor materials are widely known as materials for semiconductor thin films applicable to transistors, but oxide semiconductors are attracting attention as other materials.

Transistors using amorphous silicon, for which manufacturing technology has been established, are often used for the display device, but transistors using amorphous silicon have low field-effect mobility, and the display device has higher definition. And there are problems such as low power consumption.

Further, the transistor using amorphous silicon has a problem that the electrical characteristics are significantly deteriorated (low reliability) due to temperature changes and repeated operations.

In addition, semiconductor devices (semiconductor storage devices, etc.) that use transistors using single crystal silicon with high field-effect mobility have increased power consumption due to high integration and circuit complexity according to the scaling law. It is a problem.

Transistors using oxide semiconductors are known to have higher field-effect mobilities than transistors using amorphous silicon. Further, since it is easy to form a film on mother glass having a large area by a sputtering method or the like, application to a display device is being actively studied.

On the other hand, it has been pointed out that when an oxide semiconductor and an aluminum alloy wiring are directly connected, a high-resistance aluminum oxide is generated and the contact resistance increases (see Patent Document 1).

Further, even when a metal that is relatively difficult to oxidize or a metal having conductivity is used as the oxide, a high-resistance metal oxide is formed at the interface with the oxide semiconductor by heat treatment in a later step.
Contact resistance may increase not a little.

As described above, the high contact resistance between the metal and the oxide semiconductor causes a problem that the on-characteristics of the transistor are deteriorated.

Further, in order to reduce the contact resistance, a technique of providing a low resistance buffer layer between the oxide semiconductor and the metal is disclosed. Further, an oxide semiconductor containing nitrogen as a buffer layer is disclosed (see Patent Document 2).

Japanese Unexamined Patent Publication No. 2011-49542 Japanese Unexamined Patent Publication No. 2011-9724

As described above, in a transistor using an oxide semiconductor film, the on-characteristics of the transistor deteriorate due to the contact resistance between the metal film and the oxide semiconductor film, so that the performance of the semiconductor device using the transistor is sufficiently brought out. It may not be possible.

That is, due to a factor that hinders the movement of the carrier, the on-characteristics of the transistor may be lowered to about 30% to 70%, and in some cases, 10% or less with respect to the on-characteristics of the transistor that should be originally obtained.

As described above, in a transistor using an oxide semiconductor film, it is desired to reduce the contact resistance between the oxide semiconductor film and the metal film, which is a factor of lowering the on-characteristics.

One of the problems in one aspect of the present invention is to reduce the contact resistance between the oxide semiconductor film and the metal film.

Further, in one aspect of the present invention, it is an object of the present invention to provide a transistor using an oxide semiconductor film having excellent on-characteristics.

One aspect of the present invention is a pair of electrodes on an insulating surface, an oxide semiconductor film provided in contact with the pair of electrodes, a gate insulating film on the oxide semiconductor film, and an oxide semiconductor via the gate insulating film. It is a semiconductor device having a gate electrode superimposing on a film, and having a pair of electrodes containing a halogen element in a region in contact with the oxide semiconductor film.

One aspect of the present invention includes a gate electrode on an insulating surface, a gate insulating film on the gate electrode, a pair of electrodes on the gate insulating film, and an oxide semiconductor film provided in contact with the pair of electrodes. The semiconductor device is characterized in that the region in contact with the oxide semiconductor film contains a halogen element in the pair of electrodes.

In one aspect of the present invention, a pair of electrodes are formed on an insulating surface, the pair of electrodes are halogenated, and then an oxide semiconductor film in contact with the pair of electrodes is formed on the oxide semiconductor film. This is a method for manufacturing a semiconductor device, characterized in that a gate insulating film is formed on the surface of the semiconductor device, and a gate electrode is formed so as to be superimposed on the oxide semiconductor film via the gate insulating film.

In one aspect of the present invention, a gate electrode is formed on an insulating surface, a gate insulating film is formed on the gate electrode, a pair of electrodes are formed on the gate insulating film, and the pair of electrodes are halogenated. This is a method for manufacturing a semiconductor device, which comprises forming an oxide semiconductor film in contact with a pair of electrodes.

One aspect of the present invention is a method for manufacturing a semiconductor device, wherein the halogenation treatment is a plasma treatment in an atmosphere containing fluorine. As the atmosphere containing fluorine, for example, nitrogen trifluoride gas or the like can be used. Plasma processing is ICP (Inductive)
A very Coupled Plasma (inductively coupled plasma) device or the like can be used. Further, it is preferable to use a high-density plasma device because the damage caused by plasma to the object to be processed is reduced.

Further, the halogenation treatment does not have to be a plasma treatment, and can be performed by exposing the object to be treated to an atmosphere containing a halogen element. At that time, when the object to be treated is heated,
It is preferable because the halogenation treatment is promoted. Further, it may be immersed in a liquid containing a halogen element.

The semiconductor device according to one aspect of the present invention has a so-called bottom contact type transistor structure in which the upper surface of a pair of electrodes functioning as a source electrode and a drain electrode is in contact with an oxide semiconductor film. By using such a structure, when the pair of electrodes is processed by dry etching or the like, there is no influence such as etching of the oxide semiconductor film, so that the film thickness of the oxide semiconductor film can be easily controlled. Also, since there is no damage due to processing,
The reliability of the transistor is improved. The above effects are the same in both the top gate type and bottom gate type structures.

During the formation of the oxide semiconductor film on the metal film, or by heat treatment in the state where the metal film and the oxide semiconductor film are in contact with each other, the metal film is oxidized by oxygen from the oxide semiconductor film, thereby forming the metal film and oxidation. A metal oxide film is formed at the interface of the physical semiconductor film. Therefore, the contact resistance between the metal film and the oxide semiconductor film increases.

Therefore, by forming a bond with a halogen element (termination with a halogen element) on the surface of the metal film before forming the oxide semiconductor film, the reaction between the metal film and the oxide semiconductor film is suppressed, and the metal oxide film is formed. It is possible to suppress the formation of. Thereby, an increase in contact resistance in the metal film and the oxide semiconductor film can be suppressed. At the same time, it is possible to prevent the diffusion of oxygen from the oxide semiconductor to the metal film. Therefore, the formation of oxygen deficiency in the oxide semiconductor film can be suppressed.

According to one aspect of the present invention, the contact resistance between the oxide semiconductor film and the metal film can be reduced.

Further, according to one aspect of the present invention, it is possible to provide a transistor using an oxide semiconductor film having excellent on-characteristics.

Top view and sectional view showing an example of a transistor according to one aspect of the present invention. The cross-sectional view which shows an example of the transistor which concerns on one aspect of this invention. The cross-sectional view which shows an example of the manufacturing process of the transistor which concerns on one aspect of this invention. The cross-sectional view which shows an example of the manufacturing process of the transistor which concerns on one aspect of this invention. Top view and sectional view showing an example of a transistor according to one aspect of the present invention. The cross-sectional view which shows an example of the manufacturing process of the transistor which concerns on one aspect of this invention. A circuit diagram showing an example of a semiconductor storage device using a transistor according to one aspect of the present invention, and a diagram showing electrical characteristics. A circuit diagram showing an example of a semiconductor storage device using a transistor according to one aspect of the present invention, and a diagram showing electrical characteristics. A block diagram showing a specific example of a CPU using a transistor according to one aspect of the present invention and a circuit diagram thereof. The perspective view which shows an example of the electronic device which has the transistor which concerns on one aspect of this invention.

(Embodiment 1)
In the present embodiment, a transistor which is a semiconductor device according to one aspect of the present invention and a method for manufacturing the same will be described with reference to FIGS. 1 to 4.

FIG. 1 is a top view and a cross-sectional view of a transistor which is a semiconductor device according to one aspect of the present invention. FIG. 1 (B) shows a cross section of AB corresponding to the alternate long and short dash line AB shown in the top view of the transistor shown in FIG. 1 (A). Note that FIG. 1A shows the interlayer insulating film 112 in order to prevent complication.
And the gate insulating film 108 and the like are omitted.

The transistor shown in FIG. 1B is provided in contact with the substrate 100, the underlying insulating film 102 provided on the substrate 100, the pair of electrodes 104 provided on the underlying insulating film 102, and the pair of electrodes 104. The oxide semiconductor film 106 to be formed and the gate insulating film 108 on the oxide semiconductor film 106
And the gate electrode 110 superimposed on the oxide semiconductor film 106 via the gate insulating film 108, and
It has a gate electrode 110 and an interlayer insulating film 112 provided on the gate insulating film 108. The structure may be such that the underlying insulating film 102 is not provided.

The pair of electrodes 104 are Si, Ge, Al, Ti, Cr, Co, Ni, Cu, Y, Zr, M.
One or more of o, Ag, Ru, Ta, Sn or W, their nitrides, oxides and alloys may be selected and used in a single layer or in a laminated manner. Alternatively, oxides or oxynitrides containing at least In and Zn may be used. For example, an In-Ga-Zn-ON-based material or the like may be used. The pair of electrodes 104 function as a source electrode and a drain electrode of a transistor, and can also be used as wiring.

In the pair of electrodes 104, the region in contact with the oxide semiconductor film 106 contains a halogen element. For example, it contains fluorine or chlorine. In this way, by forming a bond with a halogen element (termination with a halogen element) on the surface of the pair of electrodes 104, the reaction between the pair of electrodes 104 and the oxide semiconductor film 106 is suppressed, and the formation of a metal oxide film is formed. It becomes possible to suppress it. Therefore, it is possible to suppress the generation of a resistance component due to the formation of the metal oxide film, and it is possible to reduce the contact resistance between the pair of electrodes 104 and the oxide semiconductor film 106. At the same time, the oxide semiconductor film 1
It is also possible to prevent the diffusion of oxygen from 06 to the pair of electrodes 104. Therefore, the formation of oxygen deficiency in the oxide semiconductor film 106 can be suppressed.

The oxide semiconductor film 106 includes a low resistance region 106b and a high resistance region 106a.

The low resistance region 106b is a region containing impurities that lower the resistance of the oxide semiconductor film. For example, the low resistance region 106b is a region containing one or more selected from hydrogen, helium, boron, nitrogen, fluorine, neon, aluminum, phosphorus, argon, arsenic, krypton, indium, tin, antimony and xenon.

By forming the low resistance region 106b, it is possible to suppress a decrease in the on-characteristics of the transistor using the oxide semiconductor film 106. In the low resistance region 106b, the sheet resistance is 30 kΩ / sq.
Hereinafter, it is preferably 10 kΩ / sq or less, more preferably 1 kΩ / sq or less, still more preferably 0.7 kΩ / sq or less.

The high resistance region 106a is a region other than the main component of the oxide semiconductor film, that is, a region in which the concentration of impurities is low. For example, the high resistance region 106a has an impurity concentration of 1 × 10 ²⁰ atoms / cm.
³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹
It is a region of ⁹ atoms / cm ^{3 or less.} However, since it is difficult to strictly separate the main component and impurities, the main component is an element contained in 1 atomic% or more in the present specification.

The high resistance region 106a is a region having a low impurity concentration and a low defect density, and is shown in FIG. 1 (B).
Since the channel region is formed in the high resistance region 106a, the transistor shown in the above is excellent in electrical characteristics and reliability. In addition, the off-current value of the transistor becomes low. For example, a transistor having an off-current value per 1 μm of channel width of 1 × 10 ^-18 A or less, preferably 1 × 10 ^-21 A or less, and more preferably 1 × 10 ^-24 A or less can be used.

The material used for the oxide semiconductor film 106 preferably contains at least indium (In) or zinc (Zn). In particular, it is preferable to contain In and Zn. Further, it is preferable to have gallium (Ga) in addition to the stabilizer for reducing the variation in the electrical characteristics of the transistor using the oxide semiconductor. Further, it is preferable to have tin (Sn), hafnium (Hf), aluminum (Al), titanium (Ti) or zirconium (Zr) as the stabilizer.

In addition, as other stabilizers, lanthanoids such as lanthanum (La) and cerium (
Ce), placeodim (Pr), neodym (Nd), samarium (Sm), europium (Eu), gadrinium (Gd), terbium (Tb), dysprosium (Dy), lutetium (Ho), elbium (Er), thulium ( It may have one or more of Tm), ytterbium (Yb), and lutetium (Lu).

For example, as oxide semiconductors, indium oxide, tin oxide, zinc oxide, In—Zn oxide, Sn—Zn oxide, Al—Zn oxide, Zn—Mg oxide, which are oxides of binary metals, are used. Oxides, Sn-Mg-based oxides, In-Mg-based oxides, In-Ga-based oxides, In-Ga-Zn-based oxides (also referred to as IGZO), which are ternary metal oxides, In- Al-Zn-based oxides, In-Sn-Zn-based oxides, Sn-Ga-Zn-based oxides, Al-Ga-Zn-based oxides, Sn-Al-Zn-based oxides, In-Hf-Zn-based oxides Things, In-La-Zn-based oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides, In-Nd-Zn-based oxides, In-Sm-Zn-based oxides, In-Eu -Zn-based oxides, In-Gd-Zn-based oxides,
In-Tb-Zn-based oxide, In-Dy-Zn-based oxide, In-Ho-Zn-based oxide, I
n-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide, In
-Lu-Zn-based oxide, In-Sn-Ga-Zn-based oxide, which is a quaternary metal oxide, I
n-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-
Zn-based oxides, In-Sn-Hf-Zn-based oxides, and In-Hf-Al-Zn-based oxides can be used.

The oxide semiconductor film 106 is in a state of single crystal, polycrystal (also referred to as polycrystal) or amorphous.

Preferably, the oxide semiconductor film 106 is CAAC-OS (C Axis Aligned).
Crystalline Oxide Semiconductor) film.

The CAAC-OS membrane is neither completely single crystal nor completely amorphous. The CAAC-OS film is an oxide semiconductor film having a crystal-amorphous mixed phase structure having a crystal portion in an amorphous phase. In many cases, the crystal portion has a size that can be accommodated in a cube having a side of less than 100 nm. again,
Transmission Electron Microscope (TEM: Transmission Electron Microscope)
In the observation image by scope), the boundary between the amorphous part and the crystalline part contained in the CAAC-OS film is not clear. In addition, grain boundaries (also referred to as grain boundaries) cannot be confirmed on the CAAC-OS film by TEM. Therefore, the CAAC-OS film suppresses the decrease in electron mobility due to the grain boundaries.

The crystal part contained in the CAAC-OS film has a c-axis aligned in a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface of the CAAC-OS film, and is triangular when viewed from the direction perpendicular to the ab plane. It has a shape or hexagonal atomic arrangement, and the metal atoms are arranged in layers or the metal atoms and oxygen atoms are arranged in layers when viewed from the direction perpendicular to the c-axis. The directions of the a-axis and the b-axis may be different between different crystal portions. In the present specification, when it is simply described as vertical, 8
The range of 5 ° or more and 95 ° or less is also included. Also, when simply describing parallel, -5
The range of ° or more and 5 ° or less is also included.

In the CAAC-OS film, the distribution of crystal portions may not be uniform. For example, CAA
In the process of forming a C-OS film, when crystals are grown from the surface side of the oxide semiconductor film, the proportion of the crystal portion may be higher in the vicinity of the surface than in the vicinity of the surface to be formed. Also, CA
By adding an impurity to the AC-OS film, the crystal portion may be amorphized in the impurity-added region.

Since the c-axis of the crystal portion included in the CAAC-OS film is aligned in a direction parallel to the normal vector of the surface to be formed or the normal vector of the surface of the CAAC-OS film, the shape of the CAAC-OS film (the surface to be formed). Depending on the cross-sectional shape of the surface or the cross-sectional shape of the surface), they may face different directions. The direction of the c-axis of the crystal portion is parallel to the normal vector of the surface to be formed or the normal vector of the surface when the CAAC-OS film is formed. The crystal part is formed by forming a film or by performing a crystallization treatment such as a heat treatment after the film formation.

A transistor using a CAAC-OS film can reduce fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light. Therefore, the transistor is highly reliable.

The substrate 100 is not significantly limited, but must have at least heat resistance sufficient to withstand the subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like may be used as the substrate 100. In addition, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, and SOI (
It is also possible to apply a Silicon On Insulator) substrate or the like, and it is preferable to use a substrate on which a semiconductor element is provided as the substrate 100.

Further, a flexible substrate may be used as the substrate 100. As a method of providing the transistor on the flexible substrate, there is also a method of forming the transistor on the non-flexible substrate, peeling off the transistor, and transposing it to the substrate 100 which is a flexible substrate. In that case,
It is advisable to provide a release layer between the non-flexible substrate and the transistor.

The underlying insulating film 102 is made of silicon oxide, silicon oxide nitride, silicon nitride, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, yttrium oxide, gallium oxide, lanthanum oxide, cesium oxide, tantalum oxide and magnesium oxide. One or more may be selected and used in a single layer or in a laminated manner.

Further, it is preferable that the underlying insulating film 102 has sufficient flatness. Specifically, a underlying film is provided so that the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably 0.1 nm or less. By setting Ra to a value equal to or lower than the above value, a crystal region is likely to be formed on the oxide semiconductor film 106. Ra is a three-dimensional extension of the center line average roughness defined in JIS B0601 so that it can be applied to a surface, and is "a value obtained by averaging the absolute values of deviations from the reference surface to the designated surface. It can be expressed as, and is defined by the formula 1.

In the formula 1, S ₀ is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y).
1) Refers to the area of (a rectangular area surrounded by four points represented by (x2, y2)), Z _0.
Refers to the average height of the measurement surface. Ra is an atomic force microscope (AFM)
It can be evaluated by Microscope).

Silicon oxynitride indicates that the composition has a higher oxygen content than nitrogen.
For example, oxygen is 50 atomic% or more and 70 atomic% or less, nitrogen is 0.5 atomic% or more and 15 atomic% or less, silicon is 25 atomic% or more and 35 atomic% or less, and hydrogen is 0 atomic% or more and 10 atomic% or less. It means what is included. Further, silicon nitride oxide means that the content of nitrogen is higher than that of oxygen in its composition, for example, oxygen is 5 atomic% or more and 30 atomic% or less, and nitrogen is 20.
Atomic% or more and 55 atomic% or less, silicon is 25 atomic% or more and 35 atomic% or less, and hydrogen is 10 atomic% or more and 25 atomic% or less. However, the above range is the Rutherford Backscattering Spec (RBS).
Rometry) and hydrogen forward scatter method (HFS: Hydrogen Forward s)
It is a case of measurement using cattering spectroscopy).
Further, the composition of the constituent elements takes a value whose total does not exceed 100 atomic%.

Further, it is preferable to use an insulating film that releases oxygen by heat treatment as the underlying insulating film 102.

"Release oxygen by heat treatment" means that the amount of oxygen released in terms of oxygen atoms is 1.0 x 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 x 10 ²⁰ atto, in TDS analysis.
It means that it is ms / cm ^{3 or more.}

Here, a method for measuring the amount of oxygen released in terms of oxygen atoms by TDS analysis will be described below.

The amount of gas released during TDS analysis is proportional to the integral value of the spectrum. Therefore, the amount of gas released can be calculated from the ratio of the integrated value of the measured spectrum to the reference value of the standard sample. The reference value of a standard sample is the ratio of the density of atoms to the integrated value of the spectrum of a sample containing a predetermined atom.

_{For example, the amount of oxygen molecules released from the insulating film (NO2} ) can be calculated by Equation 2 from the TDS analysis result of a silicon wafer containing hydrogen of a predetermined density, which is a standard sample, and the TDS analysis result of the insulating film. .. Here, it is assumed that all the spectra detected by the mass number 32 obtained by the TDS analysis are derived from oxygen molecules. _{There is another CH 3} OH with a mass number of 32, but it is not considered here because it is unlikely to exist. Further, oxygen molecules containing an oxygen atom having a mass number of 17 and an oxygen atom having a mass number of 18, which are isotopes of oxygen atoms, are not considered because their abundance ratio in nature is extremely small.

_NH2 is a value obtained by converting hydrogen molecules desorbed from the standard sample by density. _SH2 is an integral value of the spectrum when the standard sample is TDS-analyzed. Here, the reference value of the standard sample is set to N.
_H2 / S _H2 . _SO2 is an integral value of the spectrum when the insulating film is TDS-analyzed. α is a coefficient that affects the spectral intensity in TDS analysis. For details of Equation 2, refer to JP-A-6-275697. The amount of oxygen released from the insulating film is
The measurement is carried out using a temperature desorption analyzer EMD-WA1000S / W manufactured by Denshi Kagaku Co., Ltd. and a silicon wafer containing ^{1 × 10 16} atoms / cm ^{3 hydrogen atoms as a standard sample.}

Also, in TDS analysis, some of the oxygen is detected as oxygen atoms. The ratio of oxygen molecule to oxygen atom can be calculated from the ionization rate of oxygen molecule. Since the above-mentioned α contains the ionization rate of oxygen molecules, the amount of oxygen atoms released can also be estimated by evaluating the amount of oxygen molecules released.

_NO2 is the amount of oxygen molecules released. The amount released when converted to oxygen atoms is twice the amount released of oxygen molecules.

By supplying oxygen from the underlying insulating film 102 to the oxide semiconductor film 106, the interface state density between the oxide semiconductor film 106 and the underlying insulating film 102 can be reduced. As a result, it is possible to suppress the capture of carriers at the interface between the oxide semiconductor film 106 and the underlying insulating film 102 due to the operation of the transistor or the like, and it is possible to obtain a highly reliable transistor.

Further, electric charges may be generated due to oxygen deficiency of the oxide semiconductor film 106. Generally, oxygen deficiency of the oxide semiconductor film 106 partially becomes a donor and emits electrons as carriers.
As a result, the threshold voltage of the transistor shifts in the negative direction. Therefore, sufficient oxygen is supplied from the base insulating film 102 to the oxide semiconductor film 106, and preferably, the oxide semiconductor film 106 contains an excessive amount of oxygen, which causes the threshold voltage to shift in the negative direction. The oxygen deficiency density of the oxide semiconductor film 106 can be reduced.

The gate insulating film 108 may be formed by the same method and the same material as the underlying insulating film 102.

The gate electrode 110 may be formed by the same method and the same material as the pair of electrodes 104.

Further, the transistor shown in FIG. 1 shows a structure in which the gate electrode 110 and the pair of electrodes 104 do not overlap with each other and an offset region is formed on the oxide semiconductor film 106, but the transistor is not limited to this. For example, the structure may be such that the gate electrode 110 and one electrode 104 are superimposed.

The interlayer insulating film 112 is formed by the same method and the same material as the underlying insulating film 102.

The interlayer insulating film 112 preferably has a small relative permittivity and a sufficient thickness. for example,
A silicon oxide film having a relative permittivity of about 3.8 may be used, and the thickness may be 300 nm or more and 1000 nm or less. The surface of the interlayer insulating film 112 has a slightly fixed charge due to the influence of atmospheric components and the like, and the threshold voltage of the transistor may fluctuate due to the influence. Therefore, it is preferable that the interlayer insulating film 112 has a relative permittivity and a thickness within a range in which the influence of electric charges generated on the surface is sufficiently small. For the same reason, the influence of the electric charge generated on the surface may be reduced by forming the resin film on the interlayer insulating film 112.

Further, in the transistor structure shown in FIG. 1, the surfaces of the pair of electrodes and the underlying insulating film are substantially aligned and flat. Therefore, it has a planar structure in which the oxide semiconductor film is formed flat. However, the structure is not limited to such a structure, and may be a structure as shown in FIG. In the transistor structure shown in FIG. 2, a pair of electrodes 204 are formed on a flat underlying insulating film 202, and an oxide semiconductor film 206 is formed on the pair of electrodes 204. Further, in FIG. 2, similarly to the oxide semiconductor film 106 shown in FIG. 1, the oxide semiconductor film 206 has a low resistance region 20.
It shows a structure including 6b and a high resistance region 206a. However, the structure is not limited to this, and it is not necessary to form a low resistance region and a high resistance region in the oxide semiconductor film. The structure shown in FIG. 1 is chemical mechanical polishing (CMP).
A flattening process such as artificial polishing) is required, but the structure shown in FIG. 2 does not require a flattening process, which facilitates the process.

Next, the method of manufacturing the transistor shown in FIG. 1 (B) will be described with reference to FIGS. 3 and 4.

First, the underlying insulating film 102 is formed on the substrate 100. The underlying insulating film 102 is formed by a chemical vapor deposition (CVD) method, a sputtering method, a molecular beam epitaxy (MBE) method, or a pulsed laser deposition (PLD) method.
The film may be formed by a method, and it is preferable to use a sputtering method. Depending on the substrate 100, the underlying insulating film 102 may not be provided.

Next, a conductive film is formed on the underlying insulating film 102. It is preferable to use a sputtering method for forming the conductive film.

Next, the conductive film is processed to form a pair of electrodes 104 (see FIG. 3A). In addition, "processing" means that unless otherwise specified, a resist mask formed by a photolithography method is used and an etching process is performed to obtain a film having a desired shape.

Next, an insulating film is formed by covering the pair of electrodes 104. The insulating film is formed by the same material and method as the underlying insulating film.

Then, a flattening treatment such as a CMP treatment is performed to polish the insulating film until the pair of electrodes 104 are exposed. (See FIG. 3 (B).).

Next, the pair of exposed electrodes 104 are subjected to a halogenation treatment. Halogenation treatment
It can be carried out by plasma treatment in an atmosphere containing a halogen element. For example, plasma treatment may be performed using a dry etching apparatus, a plasma CVD apparatus, or the like in an atmosphere containing nitrogen trifluoride gas. Further, the halogenation treatment does not have to be a plasma treatment, and can be performed by exposing the object to be treated to an atmosphere containing a halogen element. At that time, it is preferable to heat the object to be treated because the halogenation treatment is promoted. again,
It may be immersed in a liquid containing a halogen element.

After the pair of electrodes 104 are halogenated, an oxide semiconductor film is formed. The oxide semiconductor film may be formed by a CVD method, a sputtering method, an MBE method or a PLD method, and it is preferable to use a sputtering method.

After forming the oxide semiconductor film, heat treatment may be performed. When the heat treatment is performed, the crystallinity of the oxide semiconductor film is increased. In addition, the concentration of impurities (hydrogen, water, etc.) in the oxide semiconductor film can be reduced, and the defect density can be reduced.

The heat treatment may be performed by using one type or a combination of two or more types of an oxidizing atmosphere, an inert atmosphere, a reduced pressure atmosphere and a dry air atmosphere. Preferably, the heat treatment is performed in an inert atmosphere or a reduced pressure atmosphere, and then the heat treatment is performed in an oxidizing atmosphere or a dry air atmosphere. The temperature of the heat treatment may be 150 ° C. or higher and 650 ° C. or lower, preferably 250 ° C. or higher and 500 ° C. or lower, and more preferably 300 ° C. or higher and 450 ° C. or lower. The heat treatment is a resistance heating method,
A lamp heater method, a heating gas method, or the like may be applied.

The oxidizing atmosphere means an atmosphere containing an oxidizing gas. The oxidizing gas is oxygen, ozone, nitrous oxide or the like, and preferably does not contain water, hydrogen or the like. For example, the purity of oxygen, ozone, and nitrous oxide introduced into the heat treatment apparatus is 8N (99.999999%) or more, preferably 9N (99.999999%) or more. An oxidizing gas and an inert gas may be mixed in the oxidizing atmosphere. In that case, the oxidizing gas is at least 10 ppm.
The atmosphere includes the above. By performing the heat treatment in an oxidizing atmosphere, the oxygen deficiency density of the oxide semiconductor film can be reduced.

The inert atmosphere refers to an atmosphere containing an inert gas such as nitrogen or a rare gas as a main component. Specifically, the atmosphere is such that the reactive gas such as an oxidizing gas is less than 10 ppm. By performing the heat treatment in an inert atmosphere, the concentration of impurities contained in the oxide semiconductor film can be reduced.

The decompressed atmosphere means an atmosphere in which the pressure in the processing chamber is 10 Pa or less. By performing the heat treatment in a reduced pressure atmosphere, the concentration of impurities contained in the oxide semiconductor film can be further reduced as compared with the inert atmosphere.

The dry air atmosphere refers to an atmosphere containing about 20% oxygen and about 80% nitrogen with a dew point of −40 ° C. or lower, preferably a dew point of −50 ° C. or lower. Although it is a kind of oxidizing atmosphere, it is suitable for mass production because of its relatively low cost.

Next, the oxide semiconductor film is processed to form the oxide semiconductor film 106 (see FIG. 3C).
..

Next, the gate insulating film 108 is formed. The gate insulating film 108 may be formed by a CVD method, a sputtering method, an MBE method, or a PLD method, and it is particularly preferable to use a sputtering method.

Next, a conductive film is formed. The conductive film is a CVD method, a sputtering method, an MBE method or PL.
The film may be formed by the D method, and it is particularly preferable to use the sputtering method.

Next, the conductive film is processed to form the gate electrode 110 (see FIG. 4A).

Next, using the gate electrode 110 as a mask, an impurity that lowers the resistance of the oxide semiconductor film 106 is added to form a low resistance region 106b (see FIG. 4B). note that,
The region to which impurities that lower the resistance of the oxide semiconductor film are not added is the high resistance region 106a.

As impurities that lower the resistance of oxide semiconductor films, hydrogen, helium, boron, nitrogen, fluorine,
One or more selected from neon, aluminum, phosphorus, argon, arsenic, krypton, indium, tin, antimony and xenon may be added. The method may be an ion implantation method or an ion doping method. Alternatively, plasma treatment or heat treatment may be performed in an atmosphere containing impurities that lower the resistance of the oxide semiconductor film. The ion implantation method is preferably used. After adding an impurity that lowers the resistance of the oxide semiconductor film by an ion implantation method, heat treatment may be performed in an inert atmosphere or a reduced pressure atmosphere.

Next, the interlayer insulating film 112 is formed (see FIG. 4C). The interlayer insulating film 112 is provided with a CVD insulating film 112.
The film may be formed by a method, a sputtering method, an MBE method, a PLD method or a spin coating method, and C.
It is preferable to use the VD method or the sputtering method.

Further, although not particularly shown, wiring may be provided in which the interlayer insulating film 112 and the gate insulating film 108 are processed to expose the pair of electrodes 104 and connected to the pair of electrodes 104. Further, a resin film may be provided on the interlayer insulating film 112.

By the above steps, the contact resistance between the oxide semiconductor film and the pair of electrodes can be reduced. Thereby, it is possible to provide a transistor having excellent on-characteristics.

(Embodiment 2)
In the present embodiment, a transistor having a structure different from that of the transistor shown in the first embodiment and a method for manufacturing the same will be described with reference to FIGS. 5 and 6.

FIG. 5 is a top view and a sectional view of a transistor which is a semiconductor device according to one aspect of the present invention. FIG. 5 (B) shows a cross section of AB corresponding to the alternate long and short dash line AB shown in the top view of the transistor shown in FIG. 5 (A). Note that FIG. 5A shows the interlayer insulating film 212 in order to prevent complication.
And the gate insulating film 208 and the like are omitted.

The transistors shown in FIG. 5B are the substrate 100, the underlying insulating film 202 provided on the substrate 100, the gate electrode 210 provided on the underlying insulating film 202, and the gate provided on the gate electrode 210. An insulating film 208 and a pair of electrodes 204 provided on the gate insulating film 208.
And the oxide semiconductor film 206 superimposed on the gate electrode 210 via the gate insulating film 208,
It has an oxide semiconductor film 206 and an interlayer insulating film 212 provided on a pair of electrodes.
The structure may be such that the underlying insulating film 202 is not provided.

In the pair of electrodes 204, a halogen element is contained in the vicinity of the interface between the pair of electrodes 204 and the oxide semiconductor film 206. For example, it contains fluorine or chlorine. In this way, the pair of electrodes 204
By forming a strong bond (metal-fluorine bond, etc.) on the surface of the above, it is possible to suppress the reaction between the pair of electrodes 204 and the oxide semiconductor film 206 and suppress the formation of a different layer. Therefore, it is possible to suppress the generation of resistance components due to the formation of different layers, and the pair of electrodes 204 and the oxide semiconductor film 20 can be suppressed.
The contact resistance with 6 can be reduced. At the same time, it is possible to prevent the diffusion of oxygen from the oxide semiconductor film 206 to the pair of electrodes 204. Therefore, the formation of oxygen deficiency in the oxide semiconductor film 206 can be suppressed.

The material of each layer can be the same as that of the first embodiment.

Next, the method of manufacturing the transistor shown in FIG. 5B will be described with reference to FIG.

First, the underlying insulating film 202 is formed on the substrate 100. Depending on the substrate 100, the underlying insulating film 202 may not be provided.

Next, a conductive film is formed on the underlying insulating film 202. It is preferable to use a sputtering method for forming the conductive film.

Next, the conductive film is processed to form the gate electrode 210. In addition, "processing" means that unless otherwise specified, a resist mask formed by a photolithography method is used and an etching process is performed to obtain a film having a desired shape.

Next, the gate insulating film 208 is formed. The gate insulating film 208 may be formed by a CVD method, a sputtering method, an MBE method, or a PLD method, and it is particularly preferable to use a sputtering method (see FIG. 6A).

Next, a conductive film is formed on the gate insulating film 208. The conductive film may be formed by a CVD method, a sputtering method, an MBE method or a PLD method, and it is particularly preferable to use a sputtering method.

Next, the conductive film is processed to form a pair of electrodes 204 (see FIG. 6B).

Next, the pair of electrodes 204 are subjected to a halogenation treatment. The halogenation treatment can be performed by plasma treatment in an atmosphere containing a halogen element. For example, plasma treatment may be performed using a dry etching apparatus, a plasma CVD apparatus, or the like in an atmosphere containing nitrogen trifluoride gas. Further, the halogenation treatment does not have to be a plasma treatment, and can be performed by exposing the object to be treated to an atmosphere containing a halogen element. At that time, it is preferable to heat the object to be treated because the halogenation treatment is promoted.

After the pair of electrodes 204 are halogenated, an oxide semiconductor film is formed. The oxide semiconductor film may be formed by a CVD method, a sputtering method, an MBE method or a PLD method, and it is preferable to use a sputtering method.

After forming the oxide semiconductor film, heat treatment may be performed. When the heat treatment is performed, the crystallinity of the oxide semiconductor film is increased. In addition, the concentration of impurities (hydrogen, water, etc.) in the oxide semiconductor film can be reduced, and the defect density can be reduced. The heat treatment can be performed in the same manner as in the first embodiment.

Next, the oxide semiconductor film is processed to form the oxide semiconductor film 206.

Next, the interlayer insulating film 212 is formed (see FIG. 6C). The interlayer insulating film 212 is provided with a CVD insulating film 212.
The film may be formed by a method, a sputtering method, an MBE method, a PLD method or a spin coating method, and C.
It is preferable to use the VD method or the sputtering method.

Further, although not particularly shown, the interlayer insulating film 212 may be processed to expose the pair of electrodes 204, and wiring for connecting to the pair of electrodes 204 may be provided. Further, a resin film may be provided on the interlayer insulating film 212.

By the above steps, the contact resistance between the oxide semiconductor film and the pair of electrodes can be reduced. Thereby, it is possible to provide a transistor having excellent on-characteristics.

(Embodiment 3)
In this embodiment, an example of manufacturing a semiconductor storage device using the transistor shown in the first embodiment or the second embodiment will be described.

As a typical example of a volatile semiconductor storage device, a DRAM (Dynamic Ra) that stores information by selecting a transistor constituting a storage element and accumulating an electric charge in the capacitor.
There is a SRAM (Static Random Access Memory) that holds the stored contents by using a circuit such as an ndom Access Memory) and a flip-flop.

As a typical example of the non-volatile semiconductor storage device, there is a flash memory having a node between the gate of the transistor and the channel region and storing the electric charge in the node.

The transistor shown in the first embodiment or the second embodiment can be applied to a part of the transistors included in the semiconductor storage device described above.

First, the volatile memory to which the transistor shown in the first embodiment or the second embodiment is applied will be described with reference to FIG. 7.

The memory cell has a bit line BL, a word line WL, a sense amplifier SAmp, a transistor Tr, and a capacitor C (see FIG. 7A).

The time change of the voltage held in the capacitor C is due to the off current of the transistor Tr in FIG. 7.
It is known that it gradually decreases as shown in (B). The voltage initially charged from V0 to V1 is reduced to VA, which is the limit point for reading data1, over time.
This period is defined as the retention period T_1. That is, in the case of a binary memory cell, it is necessary to refresh during the retention period T_1.

Here, when the transistor shown in the first embodiment or the second embodiment is applied to the transistor Tr, the holding period T_1 can be lengthened because the off-current is small. That is, since the refresh period can be extended, the power consumption can be reduced. For example, when a transistor using an oxide semiconductor film having an off current of 1 × 10 ^-21 A or less, preferably 1 × 10 ^-24 A or less is applied to a DRAM, it does not supply power for several days to several tens. It will be possible to retain data for a year.

As described above, according to one aspect of the present invention, it is possible to obtain a volatile memory having high reliability and low power consumption.

Further, by applying the transistor having excellent on-characteristics shown in the first embodiment or the second embodiment, the electric charge is rapidly accumulated in the capacitor C, and a semiconductor storage device capable of high-speed operation can be obtained. Can be done.

Next, the non-volatile memory to which the transistor shown in the first embodiment or the second embodiment is applied will be described with reference to FIG.

FIG. 8A is a circuit diagram of the non-volatile memory. The non-volatile memory is the transistor Tr_
1, the word line WL_1 connected to the gate of the transistor Tr_1, and the transistor Tr.
The source wiring SL_1 connected to the source of _1, the transistor Tr_2, the source wiring SL_2 connected to the source of the transistor Tr_2, the drain wiring DL_2 connected to the drain of the transistor Tr_2, the capacitor C, and one end of the capacitor C are connected. It has a capacitive wiring CL, the other end of the capacitor C, a drain of the transistor Tr_1, and a node N connected to the gate of the transistor Tr_1.

The non-volatile memory shown in this embodiment has a transistor T depending on the potential of the node N.
This utilizes the fact that the threshold voltage of r_2 fluctuates. For example, FIG. 8B is a diagram illustrating the relationship between _{the voltage V CL} of the capacitive wiring CL and the drain current I _{d _2 flowing through the transistor Tr _2.}

Here, the node N can adjust the voltage via the transistor Tr_1. For example, let the potential of SL_1 be VDD. At this time, the voltage of the node N can be set to HIGH by setting the potential of WL_1 to be equal to or higher than the potential obtained by adding VDD to the threshold voltage Vth of Tr_1. Further, by setting the potential of WL_1 to the threshold voltage Vth or less of Tr_1, the potential of the node N can be set to LOW.

Therefore, N = and _V CL _-I d _2 curve indicated by LOW, _V indicated by N = HIGH _CL
-I _d _2 can be obtained either curve. That is, when N = LOW, V _CL = 0V
Since I _d _2 is small, the data becomes 0. Furthermore, the N = _HIGH, because _I d _2 is large at _V CL = 0V, the data 1. In this way, the data can be stored.

Here, when the transistor shown in the first embodiment or the second embodiment is applied to the transistor Tr_1, the off current of the transistor can be made extremely small, so that the electric charge accumulated in the node N is the source of the transistor Tr_1 and the transistor Tr_1. Unintentional leakage between drains can be suppressed. Therefore, the data can be retained for a long period of time. Further, since the threshold voltage of the transistor Tr_1 is adjusted by using one aspect of the present invention, it is possible to reduce the voltage required for writing, and the power consumption can be reduced as compared with a flash memory or the like. Can be done.

The transistor shown in the first embodiment or the second embodiment may be applied to the transistor Tr_2. The transistor is excellent in on-characteristics. Therefore, the semiconductor storage device using the transistor can operate at high speed.

As described above, according to one aspect of the present invention, it is possible to obtain a semiconductor storage device having high long-term reliability, low power consumption, and high-speed operation.

This embodiment can be used in combination with other embodiments as appropriate.

(Embodiment 4)
CPU (Central Processing) using at least a part of the transistor shown in the first embodiment or the second embodiment or the semiconductor storage device shown in the third embodiment.
Unit) can be configured.

FIG. 9A is a block diagram showing a specific configuration of the CPU. CPU shown in FIG. 9 (A)
Is an arithmetic circuit (ALU) on the substrate 1190.
t) 1191, ALU controller 1192, instruction decoder 1193, interrupt controller 1194, timing controller 1195, register 1196
, Register controller 1197, Bus interface (Bus I / F) 1198,
Rewritable ROM 1199 and ROM interface (ROM I / F) 11
Has 89. As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided on separate chips.
Of course, the CPU shown in FIG. 9A is only an example in which the configuration is simplified, and the actual CPU has a wide variety of configurations depending on the application.

Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. Further, the interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or the mask state during the execution of the CPU program. The register controller 1197 generates the address of the register 1196, and reads or writes the register 1196 according to the state of the CPU.

Further, the timing controller 1195 includes an ALU 1191 and an ALU controller 119.
2. Generates a signal that controls the operation timing of the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal CLK2 based on the reference clock signal CLK1, and supplies the clock signal CLK2 to the various circuits.

In the CPU shown in FIG. 9A, a storage element is provided in the register 1196. As the storage element of the register 1196, the semiconductor storage device shown in the third embodiment can be used.

In the CPU shown in FIG. 9A, the register controller 1197 performs a holding operation in the register 1196 according to an instruction from the ALU 1191. That is, in the storage element of the register 1196, the data is held by the phase inversion element or the data is held by the capacitor. If the data is held by the phase inversion element, the register 11
The power supply voltage is supplied to the storage element in 96. When the data is held by the capacitor, the data is rewritten to the capacitor, and the supply of the power supply voltage to the storage element in the register 1196 can be stopped.

As shown in FIG. 9B or FIG. 9C, the power supply stop is performed by providing a switching element between the storage element group and the node to which the power supply potential VDD or the power supply potential VSS is given. Can be done. The circuits of FIGS. 9 (B) and 9 (C) will be described below.

9 (B) and 9 (C) show an example of a configuration in which the transistor shown in the first embodiment or the second embodiment is used for the switching element that controls the supply of the power supply potential to the storage element.

The storage device shown in FIG. 9B has a switching element 1141 and a storage element group 1143 having a plurality of storage elements 1142. Specifically, each storage element 1142 has
The storage element shown in the third embodiment can be used. A high-level power supply potential VDD is supplied to each of the storage elements 1142 of the storage element group 1143 via the switching element 1141. Further, each storage element 11 included in the storage element group 1143
42 is given the potential of the signal IN and the potential of the low-level power supply potential VSS.

In FIG. 9B, a transistor having a semiconductor having a large bandgap such as an oxide semiconductor as an active layer is used as the switching element 1141, and the switching of the transistor is controlled by the signal Sigma given to the gate. ..

Note that FIG. 9B shows a configuration in which the switching element 1141 has only one transistor, but the present invention is not limited to this, and the switching element 1141 may have a plurality of transistors. When the switching element 1141 has a plurality of transistors functioning as switching elements, the plurality of transistors may be connected in parallel, may be connected in series, or may be connected in series and in parallel. May be connected.

Further, FIG. 9C shows an example of a storage device in which a low-level power supply potential VSS is supplied to each storage element 1142 of the storage element group 1143 via a switching element 1141. The switching element 1141 can control the supply of the low-level power supply potential VSS to each storage element 1142 of the storage element group 1143.

A switching element is provided between the storage element group and the node to which the power supply potential VDD or the power supply potential VSS is given to temporarily stop the operation of the CPU and retain the data even when the supply of the power supply voltage is stopped. It is possible to reduce power consumption. For example, even while the user of the personal computer has stopped inputting information to an input device such as a keyboard, the operation of the CPU can be stopped, thereby reducing power consumption.

Here, the CPU has been described as an example, but DSP (Digital Signal P) has been described.
(Rocessor), custom LSI, FPGA (Field Programmable)
It can also be applied to LSIs such as eGate Array).

This embodiment can be implemented in combination with the above embodiment as appropriate.

(Embodiment 5)
In this embodiment, an example of an electronic device including one or more of a transistor, a semiconductor storage device, and a CPU shown in the first to fourth embodiments will be described.

FIG. 10A is a portable information terminal. The portable information terminal shown in FIG. 10A has a housing 93.
00, button 9301, microphone 9302, display unit 9303, speaker 9
It is equipped with a 304 and a camera 9305, and has a function as a portable telephone.

FIG. 10B is a display. The display shown in FIG. 10B has a housing 931.
0 and a display unit 9311 are provided.

FIG. 10C is a digital still camera. The digital still camera shown in FIG. 10C includes a housing 9320, a button 9321, a microphone 9322, and a display unit 9323.
And.

FIG. 10D is a portable information terminal that can be folded in half. The two-foldable portable information terminal shown in FIG. 10D includes a housing 9630, a display unit 9631a, a display unit 9631b, and a fastener 9633.
, The operation switch 9638.

The display unit 9631a and / and the display unit 9631b can be partially or wholly used as a touch panel, and data can be input by touching the displayed operation keys.

By using one aspect of the present invention, the performance of the electronic device can be enhanced.

This embodiment can be used in combination with other embodiments as appropriate.

100 Substrate 102 Base insulating film 104 Pair of electrodes 106 Oxide semiconductor film 106a High resistance region 106b Low resistance region 108 Gate insulating film 110 Gate electrode 112 Interlayer insulating film 202 Base insulating film 204 Pair of electrodes 206 Oxide semiconductor film 206a High resistance Region 206b Low resistance region 208 Gate insulating film 210 Gate electrode 212 Interlayer insulating film 1141 Switching element 1142 Storage element 1143 Storage element group 1189 ROM interface 1190 Board 1191 ALU
1192 ALU controller 1193 Instruction decoder 1194 Interrupt controller 1195 Timing controller 1196 Register 1197 Register controller 1198 Bus interface 1199 ROM
9300 Housing 9301 Button 9302 Microphone 9303 Display 9304 Speaker 9305 Camera 9310 Housing 9311 Display 9320 Housing 9321 Button 9322 Microphone 9323 Display 9630 Housing 9631a Display 9631b Display 9633 Fastener 9638 Operation switch

Claims (3)

It has a first conductive film, a second conductive film, an oxide semiconductor film, a gate insulating film, and a gate electrode.
The oxide semiconductor film is located on the first conductive film and on the second conductive film.
The oxide semiconductor film has a first region, a second region, and a third region.
The oxide semiconductor film contains at least In and Zn as main components and contains at least In and Zn.
The first region has a region that overlaps with the gate electrode via the gate insulating film.
The second region has a region that does not overlap with the gate electrode and has a region.
The third region has a region that does not overlap with the gate electrode, and has a region that does not overlap with the gate electrode.
The second region has a region in contact with the first conductive film and a region not in contact with the first conductive film.
The third region has a region in contact with the second conductive film and a region not in contact with the second conductive film.
The second region has a region having a lower sheet resistance than the first region.
The third region has a region having a lower sheet resistance than the first region.
The gate electrode does not overlap with the first conductive film, and the gate electrode does not overlap with the first conductive film.
The gate electrode does not overlap with the second conductive film, and the gate electrode does not overlap with the second conductive film.
The semiconductor device, wherein the first conductive film and the second conductive film contain a halogen element in a region of the first conductive film and the second conductive film in contact with the oxide semiconductor film. It has a first conductive film, a second conductive film, an oxide semiconductor film, a gate insulating film, and a gate electrode.
The oxide semiconductor film is located on the first conductive film and on the second conductive film.
The oxide semiconductor film has a first region, a second region, and a third region.
The oxide semiconductor film contains at least In and Zn as main components and contains at least In and Zn.
The first region has a region that overlaps with the gate electrode via the gate insulating film.
The second region has a region that does not overlap with the gate electrode and has a region.
The third region has a region that does not overlap with the gate electrode, and has a region that does not overlap with the gate electrode.
The second region has a region in contact with the first conductive film and a region not in contact with the first conductive film.
The third region has a region in contact with the second conductive film and a region not in contact with the second conductive film.
The second region has a region containing impurities and has a region containing impurities.
The third region has a region containing impurities and has a region containing impurities.
The gate electrode does not overlap with the first conductive film, and the gate electrode does not overlap with the first conductive film.
The gate electrode does not overlap with the second conductive film, and the gate electrode does not overlap with the second conductive film.
The semiconductor device, wherein the first conductive film and the second conductive film contain a halogen element in a region of the first conductive film and the second conductive film in contact with the oxide semiconductor film. In claim 1 or 2,
The second region or the third region comprises one or more selected from hydrogen, helium, boron, nitrogen, fluorine, neon, aluminum, phosphorus, argon, arsenic, krypton, indium, tin, antimony, and xenon. A semiconductor device characterized by including.

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