WO2015085605A1 - Igzo transistor structure and manufacturing method therefor - Google Patents

Igzo transistor structure and manufacturing method therefor Download PDF

Info

Publication number
WO2015085605A1
WO2015085605A1 PCT/CN2013/089623 CN2013089623W WO2015085605A1 WO 2015085605 A1 WO2015085605 A1 WO 2015085605A1 CN 2013089623 W CN2013089623 W CN 2013089623W WO 2015085605 A1 WO2015085605 A1 WO 2015085605A1
Authority
WO
WIPO (PCT)
Prior art keywords
igzo
photoresist
source
drain
layer
Prior art date
Application number
PCT/CN2013/089623
Other languages
French (fr)
Chinese (zh)
Inventor
石龙强
曾志远
Original Assignee
深圳市华星光电技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/131,683 priority Critical patent/US9117912B2/en
Publication of WO2015085605A1 publication Critical patent/WO2015085605A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to the field of image display, and more particularly to an IGZO transistor structure and a method of fabricating the same.
  • Thin film field effect transistors based on oxide semiconductors are hotspots in the field of display in the future, and have been extensively researched and developed in recent years.
  • the amorphous indium gallium zinc oxide (a-IGZO) film as an active channel layer can have a mobility of up to 80 cm 2 /Vs (amorphous silicon a-Si mobility is only 0.5 to 0.8 cm 2 /Vs), and Compatible with a-Si large-volume production process. Therefore, indium gallium zinc oxide semiconductor IGZO is a potential application for next-generation liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs).
  • LCDs liquid crystal displays
  • OLEDs organic light-emitting diodes
  • the semiconductor band When the metal is in contact with the IGZO, the semiconductor band is bent at the interface to form a barrier. The presence of a barrier results in a large interface resistance, ie Schottky Schottky contact.
  • the Schottky resistor causes the on-state current of the TFT component to be insufficient, the Subthreshold Swing (SS) is too large, and the stability of the component is degraded, thereby affecting the picture display quality. Therefore, reducing the contact resistance of metal and IGZO to form an ohmic Ohmic contact is an important factor in determining the performance of a semiconductor device.
  • One of the methods for forming good ohmic contact is to heavily dope (n+IGZO) in the semiconductor region in contact with the metal, so that the depletion region of the interface is narrowed, and electrons have more opportunities for direct tunneling (tunneling).
  • 1 is a schematic diagram of a top gate Bottom Contact structure of a standard TFT, including a substrate V, a source 1', a drain y, a gate 4', an insulating layer 5', and an IGZO pattern layer 6'.
  • 2 is a schematic view of a heavily doped top gate bottom contact structure in which an n+IGZO region 7' is formed in a region where the source/drain contacts the IGZO pattern layer 6'.
  • the protection of the IGZO channel is neglected, and the IGZO channel is easily damaged, affecting the performance of the ohmic contact.
  • the technical problem to be solved by the present invention is to provide an IGZO transistor structure and a method of fabricating the same, which avoids damage to the IGZO channel during N-type doping of IGZO by plasma treatment.
  • the present invention provides a method for fabricating an IGZO transistor, comprising: preparing a source/drain pattern layer and an IGZO pattern layer on a substrate; preparing a protective layer at the IGZO channel; and treating the source by plasma processing
  • the /drain electrode and the IGZO contact region are N-doped to form an n+IGZO region; and a gate insulating layer and a gate pattern layer are prepared.
  • the preparing the protective layer at the IGZO channel further comprises: forming a silicon oxide film by chemical vapor deposition CVD on the source/drain pattern layer and the IGZO pattern layer; performing photoresist on the silicon oxide film Coating; exposure and development under a mask; etching of the unprotected area of the photoresist; photoresist stripping to form a protective layer pattern.
  • the present invention also provides a method for fabricating an indium gallium zinc oxide semiconductor IGZO transistor, comprising: preparing a source/drain pattern layer on a substrate; performing IGZO film formation and coating photoresist on the source/drain pattern layer Exposing the photoresist with a halftone mask to form a protective photoresist at the IGZO channel; N-type doping the source/drain electrode and the IGZO contact region by plasma treatment to form an n+IGZO region; A gate insulating layer and a gate pattern layer are prepared.
  • the exposing the photoresist by using a halftone mask to form a protective photoresist at the IGZO channel further comprises: exposing the photoresist portion of the source/drain and the semiconductor contact region by using a halftone mask, and The photoresist at the IGZO channel is not exposed; and after the IGZO is patterned by wet etching, the photoresist of the source/drain and the semiconductor contact region is etched away by dry etching, and the photoresist at the IGZO channel is thinned to form Protective photoresist.
  • the present invention also provides an IGZO transistor structure, comprising: a source, a drain, and an IGZO disposed on a substrate; a protective layer overlying the IGZO channel; the source, the drain, and the IGZO The n+ IGZO region formed by the N-type doping of the contact region; a protective layer and a gate insulating layer over the n+IGZO region; and a gate disposed on the gate insulating layer.
  • the protective layer is silicon oxide.
  • the IGZO transistor structure and the manufacturing method thereof provided by the present invention can avoid damage to the IGZO channel during N-type doping of IGZO by plasma treatment, thereby contributing to improvement of ohmic contact and improvement of device characteristics.
  • Fig. 1 is a schematic view showing the top gate bottom contact structure of a standard TFT.
  • FIG. 2 is a schematic view of a heavily doped top gate bottom contact structure.
  • Fig. 3 is a flow chart showing a method of manufacturing an IGZO transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of a method for fabricating an IGZO transistor according to a second embodiment of the present invention.
  • Fig. 5 is a schematic view showing the structure of a third IGZO transistor according to an embodiment of the present invention.
  • a first embodiment of the present invention provides a method for manufacturing an indium gallium zinc oxide semiconductor IGZO transistor, including:
  • Step S21 preparing a source 2 (Source), a drain 3 (Drain) pattern layer, and an IGZO pattern layer 6 on the substrate 1;
  • Step S22 preparing a protective layer 8 at the IGZO channel
  • Step S23 performing N-type doping of the source/drain electrodes and the IGZO contact region by plasma treatment to form an n+IGZO region 7;
  • Step S24 preparing a gate insulating layer 5 (GI) and a gate 4 (gate) pattern layer.
  • a Protect Layer (PL) process is added to protect the IGZO channel.
  • the step S22 of preparing the protective layer further includes:
  • Step S221 using chemical vapor deposition on the source/drain pattern layer and the IGZO pattern layer (Chemical Vapor Deposition, CVD) depositing a silicon oxide (SiOx) film; step S222, performing photoresist coating on the SiOx film;
  • CVD Chemical Vapor Deposition, CVD
  • the SiOx film on the IGZO channel is protected by photoresist, and other areas are exposed, without photoresist protection;
  • Step S224 etching an unprotected area of the photoresist
  • Step S225 peeling off the photoresist to form a protective layer pattern.
  • a protective layer is introduced in the process to prevent damage to the IGZO channel during plasma processing, and plasma enhanced chemical vapor deposition (PECVD) is also ensured in the subsequent preparation of the GI layer.
  • PECVD plasma enhanced chemical vapor deposition
  • the film also does not damage the IGZO channel.
  • the protective layer is prepared, it will not be peeled off, and the IGZO channel can be protected from damage during subsequent processes. At the same time, since the channel is already protected, the subsequent tact time of the passivation layer will be greatly reduced.
  • a second embodiment of the present invention provides a method for manufacturing an indium gallium zinc oxide semiconductor IGZO transistor, including:
  • Step S31 preparing a source 2 (Source), a drain 3 (Drain) pattern layer on the substrate 1;
  • Step S32 performing IGZO 6 film formation and coating photoresist on the source/drain pattern layer 9;
  • Step S33 exposing the photoresist with a half-tone mask, forming a protective photoresist 90 at the IGZO channel;
  • Step S34 performing plasma processing on the source/drain and IGZO contact regions to form an n+IGZO region i or 7;
  • Step S35 preparing a gate insulating layer 5 (GI) and a gate 4 (gate) pattern layer.
  • step S33 further includes:
  • Step S331 exposing the photoresist portion of the source/drain and the semiconductor contact region by using a halftone mask, so that the photoresist at the IGZO channel is not exposed;
  • Step S332 after the IGZO is patterned by wet etching, the photoresist of the source/drain and the semiconductor contact region is etched away by dry etching, and the photoresist at the IGZO channel is thinned to form a protective photoresist.
  • step S331 the exposed portion of the photoresist is thinned, and the photoresist at the IGZO channel is not exposed, and its thickness is thicker relative to the exposed portion.
  • step S332 the IGZO groove is etched.
  • the photoresist at the track is thinned to form a protective photoresist that acts to protect the IGZO channel.
  • step S341 is further included to peel off the photoresist.
  • the photoresist at the IGZO channel is not exposed, a protective photoresist is formed during etching, and the IGZO channel is protected during plasma processing.
  • SiOx is used as a protective layer, and a protective layer process is required to perform plasma processing of IGZO, so that one more mask, that is, one more film forming, yellow light, and etching process.
  • a halftone mask is used, that is, a partial exposure is strong, a part of the exposure is weak, and the remaining is not exposed; the strong exposure portion has no photoresist protection, and is etched to form an IGZO pattern; The photoresist is very thin. Before plasma treatment, it can be ashed with 02 Plasma, and the exposed area is exposed, and then plasma treatment is performed. Therefore, the plasma treatment of IGZO pattern layer and IGZO can be completed by one process, one less.
  • the mask eliminates one film formation, yellow light, and etching process, which greatly reduces production costs and increases production capacity.
  • the IGZO in contact with the metal inside the IGZO channel can be plasma-treated to improve the ohmic contact.
  • Embodiment 3 of the present invention provides an IGZO transistor structure, including:
  • the source 2, the drain 3 and the IGZO 6 are disposed on the substrate 1;
  • n+IGZO region 7 formed by N-type doping at the source 2, the drain 3 and the IGZO 6 contact region;
  • a gate insulating layer 5 disposed over the protective layer 8 and the n+IGZO region 7; and a gate electrode 4 disposed on the gate insulating layer 5.
  • the protective layer 8 is silicon oxide.
  • the protective layer 8 since the protective layer 8 is disposed over the IGZO 6 channel in the IGZO transistor structure, damage to the IGZO 6 channel during plasma processing can be prevented, and the PECVD film formation does not damage the IGZO 6 trench. Road.
  • the protective layer 8 after the protective layer 8 is prepared, it will not be peeled off, and the IGZO 6 channel can be protected from damage during the subsequent process.
  • the subsequent passivation layer will also have a large tact time. Greatly reduced.
  • the IGZO transistor structure and the manufacturing method thereof provided by the present invention can avoid damage to the IGZO channel during N-type doping of IGZO by plasma treatment, thereby contributing to improvement of ohmic contact and improvement of device characteristics.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Manufacturing & Machinery (AREA)

Abstract

Provided are an IGZO transistor and a manufacturing method therefor. The method for manufacturing the IGZO transistor comprises: preparing a source/drain pattern layer and an IGZO pattern layer on a substrate; preparing a protective layer at the position of an IGZO channel; performing N-type doping at a region where a source/drain is in contact with an IGZO by means of plasma treatment, and forming an n+IGZO region; and preparing a gate insulation layer and a gate pattern layer. Damage to the IGZO channel in the process of performing the N-type doping on the IGZO by means of the plasma treatment can be avoided, which helps to improve ohmic contact and enhance an element feature.

Description

一种 IGZO电晶体结构及其制造方法  IGZO transistor structure and manufacturing method thereof
本申请要求于 2013 年 12 月 9 日提交中国专利局、 申请号为 201310657960.0、 发明名称为 "一种 IGZO电晶体结构及其制造方法、 显示 面板" 的中国专利申请的优先权， 上述专利的全部内容通过引用结合在本申 请中。 技术领域 This application claims priority to Chinese Patent Application No. 201310657960.0, entitled " IGZO O crystal structure and its manufacturing method, display panel", filed on December 9, 2013, the entire disclosure of The content is incorporated herein by reference. Technical field
本发明涉及图像显示领域， 尤其涉及一种 IGZO电晶体结构及其制造方 法。  The present invention relates to the field of image display, and more particularly to an IGZO transistor structure and a method of fabricating the same.
背景技术 Background technique
基于氧化物半导体的薄膜场效应晶体管 ( TFT )是未来显示领域的热点， 近年来得到了广泛的研究和发展。 其中， 作为有源沟道层的无定形铟镓锌氧 化合物 （a-IGZO ) 薄膜， 迁移率可高达 80cm2/Vs (非晶硅 a-Si 迁移率仅 0.5〜0.8cm2/Vs ), 并且可与 a-Si大尺寸量产制程兼容。 因此， 铟镓锌氧化物 半导体 IGZO在下一代液晶显示（LCD )和有机发光二极管 （OLED ) 的潜 在应用。  Thin film field effect transistors (TFTs) based on oxide semiconductors are hotspots in the field of display in the future, and have been extensively researched and developed in recent years. Among them, the amorphous indium gallium zinc oxide (a-IGZO) film as an active channel layer can have a mobility of up to 80 cm 2 /Vs (amorphous silicon a-Si mobility is only 0.5 to 0.8 cm 2 /Vs), and Compatible with a-Si large-volume production process. Therefore, indium gallium zinc oxide semiconductor IGZO is a potential application for next-generation liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs).
金属和 IGZO相接触时， 在界面处半导体能带弯曲， 形成势垒。 势垒的 存在会导致大的界面电阻，即肖特基 Schottky接触。 Schottky电阻会导致 TFT 元件开态电流不足， 亚阈值摆幅（Subthreshold Swing, SS )过大， 元件稳定 性下降， 从而影响画面显示品质。 所以， 降低金属和 IGZO的接触电阻， 形 成欧姆 Ohmic接触，是决定半导体元件性能好坏的一个重要因素。 良好的欧 姆接触形成的方法之一是在与金属接触的半导体区域进行重掺杂 ( n+IGZO ),使得界面的空乏区变窄，电子有更多的机会直穿隧（穿隧效应）。 图 1为标准 TFT的顶栅底接触 （ Top Gate Bottom Contact )结构示意图， 包 括基板 V、 源极 1'、 漏极 y、 栅极 4'、 绝缘层 5' 以及 IGZO图案层 6' 。 图 2为经过重掺杂的顶栅底接触结构示意图，其中在源 /漏极与 IGZO图案层 6' 相接触的区域形成了 n+IGZO区域 7' 。 然而， 在现有的制造方法中， 尤其是在通过等离子处理对 IGZO进行 N 型掺杂时， 忽略了对 IGZO沟道的保护， 极易损害 IGZO沟道， 影响欧姆接 触的效能。 When the metal is in contact with the IGZO, the semiconductor band is bent at the interface to form a barrier. The presence of a barrier results in a large interface resistance, ie Schottky Schottky contact. The Schottky resistor causes the on-state current of the TFT component to be insufficient, the Subthreshold Swing (SS) is too large, and the stability of the component is degraded, thereby affecting the picture display quality. Therefore, reducing the contact resistance of metal and IGZO to form an ohmic Ohmic contact is an important factor in determining the performance of a semiconductor device. One of the methods for forming good ohmic contact is to heavily dope (n+IGZO) in the semiconductor region in contact with the metal, so that the depletion region of the interface is narrowed, and electrons have more opportunities for direct tunneling (tunneling). 1 is a schematic diagram of a top gate Bottom Contact structure of a standard TFT, including a substrate V, a source 1', a drain y, a gate 4', an insulating layer 5', and an IGZO pattern layer 6'. 2 is a schematic view of a heavily doped top gate bottom contact structure in which an n+IGZO region 7' is formed in a region where the source/drain contacts the IGZO pattern layer 6'. However, in the existing manufacturing method, especially when N-type doping is performed on IGZO by plasma treatment, the protection of the IGZO channel is neglected, and the IGZO channel is easily damaged, affecting the performance of the ohmic contact.
发明内容 Summary of the invention
本发明所要解决的技术问题在于， 提供一种 IGZO电晶体结构及其制造 方法， 避免在通过等离子处理对 IGZO进行 N型掺杂过程中， 损害 IGZO沟 道。  The technical problem to be solved by the present invention is to provide an IGZO transistor structure and a method of fabricating the same, which avoids damage to the IGZO channel during N-type doping of IGZO by plasma treatment.
为了解决上述技术问题，本发明提供一种 IGZO电晶体制造方法， 包括： 在基板上制备源 /漏极图案层和 IGZO图案层； 在 IGZO沟道处制备保护层； 通过等离子处理对所述源 /漏电极与 IGZO接触区域进行 N 型掺杂， 形成 n+IGZO区域； 以及制备栅极绝缘层和栅极图案层。  In order to solve the above technical problem, the present invention provides a method for fabricating an IGZO transistor, comprising: preparing a source/drain pattern layer and an IGZO pattern layer on a substrate; preparing a protective layer at the IGZO channel; and treating the source by plasma processing The /drain electrode and the IGZO contact region are N-doped to form an n+IGZO region; and a gate insulating layer and a gate pattern layer are prepared.
其中， 所述在 IGZO沟道处制备保护层进一步包括： 在所述源 /漏极图案 层和 IGZO图案层上利用化学气相沉积 CVD沉积形成氧化硅薄膜； 在所述 氧化硅薄膜上进行光阻涂布； 在掩膜下曝光及显影； 对光阻未保护的区域进 行刻蚀； 光阻剥离形成保护层图形。  Wherein the preparing the protective layer at the IGZO channel further comprises: forming a silicon oxide film by chemical vapor deposition CVD on the source/drain pattern layer and the IGZO pattern layer; performing photoresist on the silicon oxide film Coating; exposure and development under a mask; etching of the unprotected area of the photoresist; photoresist stripping to form a protective layer pattern.
本发明还提供一种铟镓锌氧化物半导体 IGZO电晶体制造方法， 包括： 在基板上制备源 /漏极图案层； 在所述源 /漏极图案层上进行 IGZO成膜和涂 布光阻；采用半色调光罩对光阻进行曝光，在 IGZO沟道处形成保护性光阻； 通过等离子处理对所述源 /漏电极与 IGZO接触区域进行 N 型掺杂， 形成 n+IGZO区域； 以及制备栅极绝缘层和栅极图案层。  The present invention also provides a method for fabricating an indium gallium zinc oxide semiconductor IGZO transistor, comprising: preparing a source/drain pattern layer on a substrate; performing IGZO film formation and coating photoresist on the source/drain pattern layer Exposing the photoresist with a halftone mask to form a protective photoresist at the IGZO channel; N-type doping the source/drain electrode and the IGZO contact region by plasma treatment to form an n+IGZO region; A gate insulating layer and a gate pattern layer are prepared.
其中， 所述采用半色调光罩对光阻进行曝光， 在 IGZO沟道处形成保护 性光阻，进一步包括： 采用半色调光罩对源 /漏极与半导体接触区域的光阻部 分曝光， 而使 IGZO沟道处光阻不曝光； 以及用湿刻使 IGZO形成图形后， 用干刻将源 /漏极与半导体接触区域的光阻刻蚀掉， IGZO沟道处的光阻变薄， 形成保护性光阻。  Wherein, the exposing the photoresist by using a halftone mask to form a protective photoresist at the IGZO channel further comprises: exposing the photoresist portion of the source/drain and the semiconductor contact region by using a halftone mask, and The photoresist at the IGZO channel is not exposed; and after the IGZO is patterned by wet etching, the photoresist of the source/drain and the semiconductor contact region is etched away by dry etching, and the photoresist at the IGZO channel is thinned to form Protective photoresist.
其中，在形成 n+IGZO区域之后，还包括将所述保护性光阻剥离的步骤。 本发明还提供一种 IGZO电晶体结构， 包括： 设置在基板上的源极、 漏 极以及 IGZO; 覆盖在所述 IGZO沟道上方的保护层； 在所述源极、 漏极与 所述 IGZO接触区域进行 N型掺杂而形成的 n+IGZO区域； 设置在所述保 护层以及 n+IGZO区域上方的栅极绝缘层； 以及设置在所述栅极绝缘层上的 栅极。 Wherein, after forming the n+IGZO region, the step of peeling off the protective photoresist is further included. The present invention also provides an IGZO transistor structure, comprising: a source, a drain, and an IGZO disposed on a substrate; a protective layer overlying the IGZO channel; the source, the drain, and the IGZO The n+ IGZO region formed by the N-type doping of the contact region; a protective layer and a gate insulating layer over the n+IGZO region; and a gate disposed on the gate insulating layer.
其中， 所述保护层为氧化硅。  Wherein, the protective layer is silicon oxide.
本发明所提供的 IGZO电晶体结构及其制造方法， 能够避免在通过等离 子处理对 IGZO进行 N型掺杂过程中损害 IGZO沟道,有助于改善欧姆接触， 提高元件特性。  The IGZO transistor structure and the manufacturing method thereof provided by the present invention can avoid damage to the IGZO channel during N-type doping of IGZO by plasma treatment, thereby contributing to improvement of ohmic contact and improvement of device characteristics.
附图说明 DRAWINGS
为了更清楚地说明本发明实施例或现有技术中的技术方案， 下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍， 显而易见地， 下面 描述中的附图仅仅是本发明的一些实施例， 对于本领域普通技术人员来讲， 在不付出创造性劳动的前提下， 还可以根据这些附图获得其他的附图。  In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below. Obviously, the drawings in the following description are only It is a certain embodiment of the present invention, and other drawings can be obtained from those skilled in the art without any creative work.
图 1是标准 TFT的顶栅底接触结构示意图。  Fig. 1 is a schematic view showing the top gate bottom contact structure of a standard TFT.
图 2是经重掺杂的顶栅底接触结构示意图。  2 is a schematic view of a heavily doped top gate bottom contact structure.
图 3是本发明实施例一 IGZO电晶体制造方法的流程示意图。  Fig. 3 is a flow chart showing a method of manufacturing an IGZO transistor according to an embodiment of the present invention.
图 4是本发明实施例二 IGZO电晶体制造方法的流程示意图。  4 is a schematic flow chart of a method for fabricating an IGZO transistor according to a second embodiment of the present invention.
图 5是本发明实施例三 IGZO电晶体结构示意图。  Fig. 5 is a schematic view showing the structure of a third IGZO transistor according to an embodiment of the present invention.
具体实施方式 detailed description
下面参考附图对本发明的优选实施例进行描述。  DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.
请参照图 3所示， 本发明实施例一提供一种铟镓锌氧化物半导体 IGZO 电晶体制造方法， 包括：  Referring to FIG. 3, a first embodiment of the present invention provides a method for manufacturing an indium gallium zinc oxide semiconductor IGZO transistor, including:
步骤 S21 , 在基板 1上制备源极 2 ( Source ), 漏极 3 ( Drain ) 图案层， 以及 IGZO图案层 6;  Step S21, preparing a source 2 (Source), a drain 3 (Drain) pattern layer, and an IGZO pattern layer 6 on the substrate 1;
步骤 S22, 在 IGZO沟道处制备保护层 8;  Step S22, preparing a protective layer 8 at the IGZO channel;
步骤 S23 , 通过等离子处理 ( Plasma Treatment )对源 /漏电极与 IGZO接 触区域进行 N型掺杂， 形成 n+IGZO区域 7； 以及  Step S23, performing N-type doping of the source/drain electrodes and the IGZO contact region by plasma treatment to form an n+IGZO region 7;
步骤 S24, 制备栅极绝缘层 5 ( GI )和栅极 4 ( Gate ) 图案层。  Step S24, preparing a gate insulating layer 5 (GI) and a gate 4 (gate) pattern layer.
本实施例增加了保护层（Protect Layer, PL )制程， 对 IGZO沟道进行 保护。 具体的， 步骤 S22制备保护层进一步包括：  In this embodiment, a Protect Layer (PL) process is added to protect the IGZO channel. Specifically, the step S22 of preparing the protective layer further includes:
步骤 S221 , 在源 /漏极图案层和 IGZO 图案层上利用化学气相沉积 ( Chemical Vapor Deposition, CVD )沉积形成氧化硅 ( SiOx ) 薄膜； 步骤 S222, 在 SiOx薄膜上进行光阻涂布； Step S221, using chemical vapor deposition on the source/drain pattern layer and the IGZO pattern layer (Chemical Vapor Deposition, CVD) depositing a silicon oxide (SiOx) film; step S222, performing photoresist coating on the SiOx film;
步骤 S223 , 在掩膜下曝光及显影；  Step S223, exposing and developing under the mask;
曝光及显影后的结果是， IGZO沟道上面的 SiOx薄膜被光阻保护， 其他 区域则棵露， 无光阻保护；  As a result of exposure and development, the SiOx film on the IGZO channel is protected by photoresist, and other areas are exposed, without photoresist protection;
步骤 S224 , 对光阻未保护的区域进行刻蚀；  Step S224, etching an unprotected area of the photoresist;
步骤 S225, 将光阻剥离形成保护层图形。  Step S225, peeling off the photoresist to form a protective layer pattern.
本实施例在制程中引入了制备保护层， 防止在等离子处理过程中对 IGZO沟道的损害，也保证了后续制备 GI层时， 等离子体增强化学气相沉积 ( Plasma Enhanced Chemical Vapor Deposition, PECVD )成膜也不会损害到 IGZO沟道。 另外， 保护层制备完成后， 不会被剥离， 后续制程中一直可以 保护 IGZO 沟道不被损害。 同时， 由于沟道已经得到保护， 后续的钝化层 ( Passivation Layer ) 的产线节拍时间 （tact time )也将大大降低。  In this embodiment, a protective layer is introduced in the process to prevent damage to the IGZO channel during plasma processing, and plasma enhanced chemical vapor deposition (PECVD) is also ensured in the subsequent preparation of the GI layer. The film also does not damage the IGZO channel. In addition, after the protective layer is prepared, it will not be peeled off, and the IGZO channel can be protected from damage during subsequent processes. At the same time, since the channel is already protected, the subsequent tact time of the passivation layer will be greatly reduced.
再请参照图 4所示，本发明实施例二提供一种铟镓锌氧化物半导体 IGZO 电晶体制造方法， 包括：  Referring to FIG. 4, a second embodiment of the present invention provides a method for manufacturing an indium gallium zinc oxide semiconductor IGZO transistor, including:
步骤 S31 , 在基板 1上制备源极 2 ( Source ), 漏极 3 ( Drain ) 图案层； 步骤 S32, 在源 /漏极图案层上进行 IGZO 6成膜和涂布光阻 9;  Step S31, preparing a source 2 (Source), a drain 3 (Drain) pattern layer on the substrate 1; Step S32, performing IGZO 6 film formation and coating photoresist on the source/drain pattern layer 9;
步骤 S33 , 采用半色调 （half-tone )光罩对光阻进行曝光， 在 IGZO沟 道处形成保护性光阻 90;  Step S33, exposing the photoresist with a half-tone mask, forming a protective photoresist 90 at the IGZO channel;
步骤 S34, 对源 /漏极与 IGZO接触区域进行等离子处理， 形成 n+IGZO 区 i或 7; 以及  Step S34, performing plasma processing on the source/drain and IGZO contact regions to form an n+IGZO region i or 7;
步骤 S35, 制备栅极绝缘层 5 ( GI )和栅极 4 ( Gate ) 图案层。  Step S35, preparing a gate insulating layer 5 (GI) and a gate 4 (gate) pattern layer.
具体的， 步骤 S33进一步包括：  Specifically, step S33 further includes:
步骤 S331 , 采用半色调光罩对源 /漏极与半导体接触区域的光阻部分曝 光， 而使 IGZO沟道处光阻不曝光； 以及  Step S331, exposing the photoresist portion of the source/drain and the semiconductor contact region by using a halftone mask, so that the photoresist at the IGZO channel is not exposed;
步骤 S332, 用湿刻使 IGZO形成图形后， 用干刻将源 /漏极与半导体接 触区域的光阻刻蚀掉， IGZO沟道处的光阻变薄， 形成保护性光阻。  Step S332, after the IGZO is patterned by wet etching, the photoresist of the source/drain and the semiconductor contact region is etched away by dry etching, and the photoresist at the IGZO channel is thinned to form a protective photoresist.
上述步骤 S331 中， 被曝光的部分光阻减薄， 而 IGZO沟道处光阻未曝 光， 其厚度相对于被曝光部分较厚。 上述步骤 S332中， 在刻蚀时 IGZO沟 道处的光阻变薄，从而形成保护性光阻，起到对 IGZO沟道进行保护的作用。 在步骤 S34之后， 还包括步骤 S341 , 将光阻剥离。 In the above step S331, the exposed portion of the photoresist is thinned, and the photoresist at the IGZO channel is not exposed, and its thickness is thicker relative to the exposed portion. In the above step S332, the IGZO groove is etched. The photoresist at the track is thinned to form a protective photoresist that acts to protect the IGZO channel. After step S34, step S341 is further included to peel off the photoresist.
本实施例通过采用半色调光罩曝光， 使 IGZO沟道处的光阻不曝光， 在 刻蚀时得以形成保护性光阻， 在等离子处理过程中对 IGZO沟道起到保护作 用。  In this embodiment, by using a halftone mask exposure, the photoresist at the IGZO channel is not exposed, a protective photoresist is formed during etching, and the IGZO channel is protected during plasma processing.
本发明实施例一采用 SiOx做保护层， 需要增加一道保护层制程， 才能 进行 IGZO的等离子处理， 所以多一道光罩， 即多一次的成膜， 黄光， 刻蚀 制程。 本发明实施例二与之相比， 采用半色调光罩， 即部分曝光强， 部分曝 光弱， 剩下的不曝光； 强曝光部分没有光阻保护， 进行刻蚀形成 IGZO图形； 部分曝光部分由于光阻很薄，进行等离子处理前可用 02 Plasma先将其灰化， 棵露出要处理的区域，然后进行等离子处理即可，所以 IGZO图案层和 IGZO 的等离子处理用一道制程即可完成， 少一道光罩， 省去一次成膜， 黄光， 刻 蚀过程， 大大降低生产成本， 增加生产产能。  In the first embodiment of the present invention, SiOx is used as a protective layer, and a protective layer process is required to perform plasma processing of IGZO, so that one more mask, that is, one more film forming, yellow light, and etching process. Compared with the second embodiment of the present invention, a halftone mask is used, that is, a partial exposure is strong, a part of the exposure is weak, and the remaining is not exposed; the strong exposure portion has no photoresist protection, and is etched to form an IGZO pattern; The photoresist is very thin. Before plasma treatment, it can be ashed with 02 Plasma, and the exposed area is exposed, and then plasma treatment is performed. Therefore, the plasma treatment of IGZO pattern layer and IGZO can be completed by one process, one less. The mask eliminates one film formation, yellow light, and etching process, which greatly reduces production costs and increases production capacity.
另外， 按照本发明实施例二的方法， 还可将 IGZO沟道内侧与金属接触 的 IGZO进行等离子处理， 达到改善欧姆接触的目的。  In addition, according to the method of the second embodiment of the present invention, the IGZO in contact with the metal inside the IGZO channel can be plasma-treated to improve the ohmic contact.
请再参照图 5所示， 相应于本发明实施例一， 本发明实施例三提供一种 IGZO电晶体结构， 包括：  Referring to FIG. 5 again, in accordance with Embodiment 1 of the present invention, Embodiment 3 of the present invention provides an IGZO transistor structure, including:
设置在基板 1的源极 2、 漏极 3以及 IGZO 6;  The source 2, the drain 3 and the IGZO 6 are disposed on the substrate 1;
覆盖在 IGZO 6沟道上方的保护层 8;  Covering the protective layer 8 above the IGZO 6 channel;
在源极 2、 漏极 3与 IGZO 6接触区域进行 N型掺杂而形成的 n+IGZO 区域 7;  An n+IGZO region 7 formed by N-type doping at the source 2, the drain 3 and the IGZO 6 contact region;
设置在保护层 8以及 n+IGZO区域 7上方的栅极绝缘层 5; 以及 设置在栅极绝缘层 5上的栅极 4。  A gate insulating layer 5 disposed over the protective layer 8 and the n+IGZO region 7; and a gate electrode 4 disposed on the gate insulating layer 5.
其中， 保护层 8为氧化硅。  The protective layer 8 is silicon oxide.
本实施例中， 由于在 IGZO电晶体结构中的 IGZO 6沟道上方设置了保 护层 8, 可以防止在等离子处理过程中对 IGZO 6沟道的损害， PECVD成膜 也不会损害到 IGZO 6沟道。 另外， 保护层 8制备完成后， 不会被剥离， 后 续制程中一直可以保护 IGZO 6沟道不被损害。 同时， 由于沟道已经得到保 护， 后续的钝化层（ Passivation Layer ) 的产线节拍时间 （ tact time )也将大 大降低。 In this embodiment, since the protective layer 8 is disposed over the IGZO 6 channel in the IGZO transistor structure, damage to the IGZO 6 channel during plasma processing can be prevented, and the PECVD film formation does not damage the IGZO 6 trench. Road. In addition, after the protective layer 8 is prepared, it will not be peeled off, and the IGZO 6 channel can be protected from damage during the subsequent process. At the same time, since the channel is already protected, the subsequent passivation layer will also have a large tact time. Greatly reduced.
本发明所提供的 IGZO电晶体结构及其制造方法， 能够避免在通过等离 子处理对 IGZO进行 N型掺杂过程中损害 IGZO沟道,有助于改善欧姆接触， 提高元件特性。  The IGZO transistor structure and the manufacturing method thereof provided by the present invention can avoid damage to the IGZO channel during N-type doping of IGZO by plasma treatment, thereby contributing to improvement of ohmic contact and improvement of device characteristics.
以上所揭露的仅为本发明较佳实施例而已， 当然不能以此来限定本发明 之权利范围， 因此依本发明权利要求所作的等同变化， 仍属本发明所涵盖的 范围。  The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, and the equivalent changes made in the claims of the present invention are still within the scope of the present invention.

Claims

权 利 要 求 Rights request
1、 一种 IGZ0电晶体制造方法， 包括： 1. An IGZ0 transistor manufacturing method, including:
在基板上制备源 /漏极图案层和 IGZ0图案层； Prepare a source/drain pattern layer and an IGZ0 pattern layer on the substrate;
在 IGZO沟道处制备保护层； Prepare a protective layer at the IGZO channel;
通过等离子处理对所述源 /漏电极与 IGZO接触区域进行 N型掺杂， 形 成 n+IGZO区域； 以及 N-type doping is performed on the contact area between the source/drain electrode and IGZO through plasma treatment to form an n+IGZO area; and
制备栅极绝缘层和栅极图案层。 Prepare a gate insulation layer and a gate pattern layer.
2、 根据权利要求 1所述的制造方法， 其中， 所述在 IGZO沟道处制备 保护层进一步包括： 2. The manufacturing method according to claim 1, wherein preparing the protective layer at the IGZO channel further includes:
在所述源 /漏极图案层和 IGZO图案层上利用化学气相沉积 CVD沉积形 成氧化硅薄膜； Use chemical vapor deposition (CVD) to form a silicon oxide film on the source/drain pattern layer and IGZO pattern layer;
在所述氧化硅薄膜上进行光阻涂布； Perform photoresist coating on the silicon oxide film;
在掩膜下曝光及显影； Exposure and development under mask;
对光阻未保护的区域进行刻蚀； Etch the unprotected areas of the photoresist;
光阻剥离形成保护层图形。 The photoresist is peeled off to form a protective layer pattern.
3、 一种 IGZO电晶体制造方法， 包括： 3. An IGZO transistor manufacturing method, including:
在基板上制备源 /漏极图案层； Prepare a source/drain pattern layer on the substrate;
在所述源 /漏极图案层上进行 IGZO成膜和涂布光阻； Perform IGZO film formation and photoresist coating on the source/drain pattern layer;
采用半色调光罩对光阻进行曝光， 在 IGZO沟道处形成保护性光阻； 通过等离子处理对所述源 /漏电极与 IGZO接触区域进行 N型掺杂， 形 成 n+IGZO区域； 以及 Use a half-tone mask to expose the photoresist to form a protective photoresist at the IGZO channel; perform N-type doping on the contact area between the source/drain electrode and IGZO through plasma treatment to form an n+IGZO area; and
制备栅极绝缘层和栅极图案层。 Prepare a gate insulation layer and a gate pattern layer.
4、 根据权利要求 3所述的制造方法， 其中， 所述采用半色调光罩对光 阻进行曝光， 在 IGZO沟道处形成保护性光阻， 进一步包括： 4. The manufacturing method according to claim 3, wherein the photoresist is exposed using a half-tone mask to form a protective photoresist at the IGZO channel, further comprising:
采用半色调光罩对源 /漏极与半导体接触区域的光阻部分曝光， 而使 IGZO沟道处光阻不曝光； 以及 Use a half-tone mask to partially expose the photoresist in the contact area between the source/drain and the semiconductor, leaving the photoresist at the IGZO channel unexposed; and
用湿刻使 IGZO形成图形后，用干刻将源 /漏极与半导体接触区域的光阻 刻蚀掉， IGZO沟道处的光阻变薄， 形成保护性光阻。 After the IGZO is patterned by wet etching, the photoresist in the contact area between the source/drain and the semiconductor is etched away by dry etching. The photoresist at the IGZO channel is thinned to form a protective photoresist.
5、 根据权利要求 4所述的制造方法， 其中， 在形成 n+IGZO区域之后， 还包括将所述保护性光阻剥离的步骤。 5. The manufacturing method according to claim 4, wherein after forming the n+IGZO region, It also includes the step of peeling off the protective photoresist.
6、 一种 IGZO电晶体结构， 其中， 包括： 6. An IGZO transistor structure, including:
设置在基板（ 1 ) 上的源极（ 2 )、 漏极（ 3 ) 以及 IGZO ( 6 ); Source (2), drain (3) and IGZO (6) provided on the substrate (1);
覆盖在所述 IGZO (6) 沟道上方的保护层（8); a protective layer (8) covering the IGZO (6) channel;
在所述源极 ( 2 )、 漏极（ 3 )与所述 IGZO ( 6 )接触区域进行 N型掺 杂而形成的 n+IGZO区域（ Ί ); An n+IGZO region (T) formed by N-type doping in the contact region between the source (2), the drain (3) and the IGZO (6);
设置在所述保护层（ 8 )以及 n+IGZO区域（ 7 )上方的栅极绝缘层（ 5 ); 以及 A gate insulation layer (5) provided above the protective layer (8) and the n+IGZO region (7); and
设置在所述栅极绝缘层 （5 )上的栅极（4)。 A gate (4) provided on the gate insulating layer (5).
7、 根据权利要求 6所述的 IGZO电晶体结构， 其中， 所述保护层（8) 为氧化硅。 7. The IGZO transistor structure according to claim 6, wherein the protective layer (8) is silicon oxide.
PCT/CN2013/089623 2013-12-09 2013-12-17 Igzo transistor structure and manufacturing method therefor WO2015085605A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/131,683 US9117912B2 (en) 2013-12-17 2013-12-17 IGZO transistor structure and manufacturing method for the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310657960.0 2013-12-09
CN201310657960.0A CN103700705B (en) 2013-12-09 2013-12-09 A kind of IGZO electric crystals manufacture method

Publications (1)

Publication Number Publication Date
WO2015085605A1 true WO2015085605A1 (en) 2015-06-18

Family

ID=50362177

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2013/089623 WO2015085605A1 (en) 2013-12-09 2013-12-17 Igzo transistor structure and manufacturing method therefor

Country Status (2)

Country Link
CN (1) CN103700705B (en)
WO (1) WO2015085605A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104157259B (en) * 2014-09-10 2016-06-22 深圳市华星光电技术有限公司 Gate driver circuit based on IGZO processing procedure
CN104409635B (en) * 2014-12-16 2017-02-22 京东方科技集团股份有限公司 Organic thin film transistor and manufacturing method thereof, array substrate, and display unit
WO2016127372A1 (en) * 2015-02-12 2016-08-18 深圳市柔宇科技有限公司 Top-gate thin-film transistor, array substrate and manufacturing method therefor, and tft device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120211755A1 (en) * 2011-02-17 2012-08-23 Sony Corporation Thin film transistor, manufacturing method of thin film transistor and display
CN102655165A (en) * 2011-03-28 2012-09-05 京东方科技集团股份有限公司 Amorphous-oxide thin-film transistor, manufacturing method thereof, and display panel
CN103337522A (en) * 2013-06-17 2013-10-02 南京中电熊猫液晶显示科技有限公司 Metal oxide thin film transistor array substrate and manufacturing method thereof
CN103403849A (en) * 2011-02-28 2013-11-20 夏普株式会社 Semiconductor device and process of producing same, and display device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102047354B1 (en) * 2010-02-26 2019-11-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 Semiconductor device
CN103299430A (en) * 2010-12-30 2013-09-11 周星工程股份有限公司 Thin-film transistor and method for manufacturing same
JP6013685B2 (en) * 2011-07-22 2016-10-25 株式会社半導体エネルギー研究所 Semiconductor device
CN102636927B (en) * 2011-12-23 2015-07-29 京东方科技集团股份有限公司 Array base palte and manufacture method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120211755A1 (en) * 2011-02-17 2012-08-23 Sony Corporation Thin film transistor, manufacturing method of thin film transistor and display
CN103403849A (en) * 2011-02-28 2013-11-20 夏普株式会社 Semiconductor device and process of producing same, and display device
CN102655165A (en) * 2011-03-28 2012-09-05 京东方科技集团股份有限公司 Amorphous-oxide thin-film transistor, manufacturing method thereof, and display panel
CN103337522A (en) * 2013-06-17 2013-10-02 南京中电熊猫液晶显示科技有限公司 Metal oxide thin film transistor array substrate and manufacturing method thereof

Also Published As

Publication number Publication date
CN103700705A (en) 2014-04-02
CN103700705B (en) 2017-07-28

Similar Documents

Publication Publication Date Title
US10192992B2 (en) Display device
KR102080732B1 (en) Low-temperature polycrystalline silicon thin-film transistor based on dual-gate structure and manufacturing method therefor
US10615266B2 (en) Thin-film transistor, manufacturing method thereof, and array substrate
US11177293B2 (en) Array substrate and fabricating method thereof, and display device
US20190312147A1 (en) Thin film transistor, thin film transistor array panel including the same, and method of manufacturing the same
US9437627B2 (en) Thin film transistor and manufacturing method thereof
WO2015100935A1 (en) Array substrate and method for fabrication thereof, and display device
WO2018176784A1 (en) Thin film transistor, manufacturing method therefor, array substrate and display device
WO2017008345A1 (en) Thin-film transistor, manufacturing method for thin-film transistor, and display device
US10236388B2 (en) Dual gate oxide thin-film transistor and manufacturing method for the same
US20140209895A1 (en) Array substrate, fabrication method thereof and display device
US9437435B2 (en) LTPS TFT having dual gate structure and method for forming LTPS TFT
WO2019061813A1 (en) Esl-type tft substrate and manufacturing method therefor
WO2015100894A1 (en) Display device, array substrate, and method for fabricating same
WO2015021708A1 (en) Array substrate, manufacturing method therefor, display panel, and display apparatus
US11342431B2 (en) Thin film transistor and manufacturing method thereof, array substrate and display device
US20150295094A1 (en) Thin film transistor, manufacturing method thereof, array substrate and display device
WO2017008347A1 (en) Array substrate, manufacturing method for array substrate, and display device
WO2016090807A1 (en) Array substrate, manufacturing method therefor, and display device
US9252284B2 (en) Display substrate and method of manufacturing a display substrate
WO2015100859A1 (en) Array substrate and method for manufacturing same, and display device
US9117912B2 (en) IGZO transistor structure and manufacturing method for the same
CN109119427B (en) Manufacturing method of back channel etching type TFT substrate and back channel etching type TFT substrate
WO2015085605A1 (en) Igzo transistor structure and manufacturing method therefor
US8232147B2 (en) Fabricating method of a thin film transistor having a dielectric layer for inhibiting leakage current

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 14131683

Country of ref document: US

121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13899179

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 13899179

Country of ref document: EP

Kind code of ref document: A1