WO2015085605A1 - Structure de transistor igzo et son procédé de fabrication - Google Patents

Structure de transistor igzo et son procédé de fabrication Download PDF

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Publication number
WO2015085605A1
WO2015085605A1 PCT/CN2013/089623 CN2013089623W WO2015085605A1 WO 2015085605 A1 WO2015085605 A1 WO 2015085605A1 CN 2013089623 W CN2013089623 W CN 2013089623W WO 2015085605 A1 WO2015085605 A1 WO 2015085605A1
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WO
WIPO (PCT)
Prior art keywords
igzo
photoresist
source
drain
layer
Prior art date
Application number
PCT/CN2013/089623
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English (en)
Chinese (zh)
Inventor
石龙强
曾志远
Original Assignee
深圳市华星光电技术有限公司
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Application filed by 深圳市华星光电技术有限公司 filed Critical 深圳市华星光电技术有限公司
Priority to US14/131,683 priority Critical patent/US9117912B2/en
Publication of WO2015085605A1 publication Critical patent/WO2015085605A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel

Definitions

  • the present invention relates to the field of image display, and more particularly to an IGZO transistor structure and a method of fabricating the same.
  • Thin film field effect transistors based on oxide semiconductors are hotspots in the field of display in the future, and have been extensively researched and developed in recent years.
  • the amorphous indium gallium zinc oxide (a-IGZO) film as an active channel layer can have a mobility of up to 80 cm 2 /Vs (amorphous silicon a-Si mobility is only 0.5 to 0.8 cm 2 /Vs), and Compatible with a-Si large-volume production process. Therefore, indium gallium zinc oxide semiconductor IGZO is a potential application for next-generation liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs).
  • LCDs liquid crystal displays
  • OLEDs organic light-emitting diodes
  • the semiconductor band When the metal is in contact with the IGZO, the semiconductor band is bent at the interface to form a barrier. The presence of a barrier results in a large interface resistance, ie Schottky Schottky contact.
  • the Schottky resistor causes the on-state current of the TFT component to be insufficient, the Subthreshold Swing (SS) is too large, and the stability of the component is degraded, thereby affecting the picture display quality. Therefore, reducing the contact resistance of metal and IGZO to form an ohmic Ohmic contact is an important factor in determining the performance of a semiconductor device.
  • One of the methods for forming good ohmic contact is to heavily dope (n+IGZO) in the semiconductor region in contact with the metal, so that the depletion region of the interface is narrowed, and electrons have more opportunities for direct tunneling (tunneling).
  • 1 is a schematic diagram of a top gate Bottom Contact structure of a standard TFT, including a substrate V, a source 1', a drain y, a gate 4', an insulating layer 5', and an IGZO pattern layer 6'.
  • 2 is a schematic view of a heavily doped top gate bottom contact structure in which an n+IGZO region 7' is formed in a region where the source/drain contacts the IGZO pattern layer 6'.
  • the protection of the IGZO channel is neglected, and the IGZO channel is easily damaged, affecting the performance of the ohmic contact.
  • the technical problem to be solved by the present invention is to provide an IGZO transistor structure and a method of fabricating the same, which avoids damage to the IGZO channel during N-type doping of IGZO by plasma treatment.
  • the present invention provides a method for fabricating an IGZO transistor, comprising: preparing a source/drain pattern layer and an IGZO pattern layer on a substrate; preparing a protective layer at the IGZO channel; and treating the source by plasma processing
  • the /drain electrode and the IGZO contact region are N-doped to form an n+IGZO region; and a gate insulating layer and a gate pattern layer are prepared.
  • the preparing the protective layer at the IGZO channel further comprises: forming a silicon oxide film by chemical vapor deposition CVD on the source/drain pattern layer and the IGZO pattern layer; performing photoresist on the silicon oxide film Coating; exposure and development under a mask; etching of the unprotected area of the photoresist; photoresist stripping to form a protective layer pattern.
  • the present invention also provides a method for fabricating an indium gallium zinc oxide semiconductor IGZO transistor, comprising: preparing a source/drain pattern layer on a substrate; performing IGZO film formation and coating photoresist on the source/drain pattern layer Exposing the photoresist with a halftone mask to form a protective photoresist at the IGZO channel; N-type doping the source/drain electrode and the IGZO contact region by plasma treatment to form an n+IGZO region; A gate insulating layer and a gate pattern layer are prepared.
  • the exposing the photoresist by using a halftone mask to form a protective photoresist at the IGZO channel further comprises: exposing the photoresist portion of the source/drain and the semiconductor contact region by using a halftone mask, and The photoresist at the IGZO channel is not exposed; and after the IGZO is patterned by wet etching, the photoresist of the source/drain and the semiconductor contact region is etched away by dry etching, and the photoresist at the IGZO channel is thinned to form Protective photoresist.
  • the present invention also provides an IGZO transistor structure, comprising: a source, a drain, and an IGZO disposed on a substrate; a protective layer overlying the IGZO channel; the source, the drain, and the IGZO The n+ IGZO region formed by the N-type doping of the contact region; a protective layer and a gate insulating layer over the n+IGZO region; and a gate disposed on the gate insulating layer.
  • the protective layer is silicon oxide.
  • the IGZO transistor structure and the manufacturing method thereof provided by the present invention can avoid damage to the IGZO channel during N-type doping of IGZO by plasma treatment, thereby contributing to improvement of ohmic contact and improvement of device characteristics.
  • Fig. 1 is a schematic view showing the top gate bottom contact structure of a standard TFT.
  • FIG. 2 is a schematic view of a heavily doped top gate bottom contact structure.
  • Fig. 3 is a flow chart showing a method of manufacturing an IGZO transistor according to an embodiment of the present invention.
  • FIG. 4 is a schematic flow chart of a method for fabricating an IGZO transistor according to a second embodiment of the present invention.
  • Fig. 5 is a schematic view showing the structure of a third IGZO transistor according to an embodiment of the present invention.
  • a first embodiment of the present invention provides a method for manufacturing an indium gallium zinc oxide semiconductor IGZO transistor, including:
  • Step S21 preparing a source 2 (Source), a drain 3 (Drain) pattern layer, and an IGZO pattern layer 6 on the substrate 1;
  • Step S22 preparing a protective layer 8 at the IGZO channel
  • Step S23 performing N-type doping of the source/drain electrodes and the IGZO contact region by plasma treatment to form an n+IGZO region 7;
  • Step S24 preparing a gate insulating layer 5 (GI) and a gate 4 (gate) pattern layer.
  • a Protect Layer (PL) process is added to protect the IGZO channel.
  • the step S22 of preparing the protective layer further includes:
  • Step S221 using chemical vapor deposition on the source/drain pattern layer and the IGZO pattern layer (Chemical Vapor Deposition, CVD) depositing a silicon oxide (SiOx) film; step S222, performing photoresist coating on the SiOx film;
  • CVD Chemical Vapor Deposition, CVD
  • the SiOx film on the IGZO channel is protected by photoresist, and other areas are exposed, without photoresist protection;
  • Step S224 etching an unprotected area of the photoresist
  • Step S225 peeling off the photoresist to form a protective layer pattern.
  • a protective layer is introduced in the process to prevent damage to the IGZO channel during plasma processing, and plasma enhanced chemical vapor deposition (PECVD) is also ensured in the subsequent preparation of the GI layer.
  • PECVD plasma enhanced chemical vapor deposition
  • the film also does not damage the IGZO channel.
  • the protective layer is prepared, it will not be peeled off, and the IGZO channel can be protected from damage during subsequent processes. At the same time, since the channel is already protected, the subsequent tact time of the passivation layer will be greatly reduced.
  • a second embodiment of the present invention provides a method for manufacturing an indium gallium zinc oxide semiconductor IGZO transistor, including:
  • Step S31 preparing a source 2 (Source), a drain 3 (Drain) pattern layer on the substrate 1;
  • Step S32 performing IGZO 6 film formation and coating photoresist on the source/drain pattern layer 9;
  • Step S33 exposing the photoresist with a half-tone mask, forming a protective photoresist 90 at the IGZO channel;
  • Step S34 performing plasma processing on the source/drain and IGZO contact regions to form an n+IGZO region i or 7;
  • Step S35 preparing a gate insulating layer 5 (GI) and a gate 4 (gate) pattern layer.
  • step S33 further includes:
  • Step S331 exposing the photoresist portion of the source/drain and the semiconductor contact region by using a halftone mask, so that the photoresist at the IGZO channel is not exposed;
  • Step S332 after the IGZO is patterned by wet etching, the photoresist of the source/drain and the semiconductor contact region is etched away by dry etching, and the photoresist at the IGZO channel is thinned to form a protective photoresist.
  • step S331 the exposed portion of the photoresist is thinned, and the photoresist at the IGZO channel is not exposed, and its thickness is thicker relative to the exposed portion.
  • step S332 the IGZO groove is etched.
  • the photoresist at the track is thinned to form a protective photoresist that acts to protect the IGZO channel.
  • step S341 is further included to peel off the photoresist.
  • the photoresist at the IGZO channel is not exposed, a protective photoresist is formed during etching, and the IGZO channel is protected during plasma processing.
  • SiOx is used as a protective layer, and a protective layer process is required to perform plasma processing of IGZO, so that one more mask, that is, one more film forming, yellow light, and etching process.
  • a halftone mask is used, that is, a partial exposure is strong, a part of the exposure is weak, and the remaining is not exposed; the strong exposure portion has no photoresist protection, and is etched to form an IGZO pattern; The photoresist is very thin. Before plasma treatment, it can be ashed with 02 Plasma, and the exposed area is exposed, and then plasma treatment is performed. Therefore, the plasma treatment of IGZO pattern layer and IGZO can be completed by one process, one less.
  • the mask eliminates one film formation, yellow light, and etching process, which greatly reduces production costs and increases production capacity.
  • the IGZO in contact with the metal inside the IGZO channel can be plasma-treated to improve the ohmic contact.
  • Embodiment 3 of the present invention provides an IGZO transistor structure, including:
  • the source 2, the drain 3 and the IGZO 6 are disposed on the substrate 1;
  • n+IGZO region 7 formed by N-type doping at the source 2, the drain 3 and the IGZO 6 contact region;
  • a gate insulating layer 5 disposed over the protective layer 8 and the n+IGZO region 7; and a gate electrode 4 disposed on the gate insulating layer 5.
  • the protective layer 8 is silicon oxide.
  • the protective layer 8 since the protective layer 8 is disposed over the IGZO 6 channel in the IGZO transistor structure, damage to the IGZO 6 channel during plasma processing can be prevented, and the PECVD film formation does not damage the IGZO 6 trench. Road.
  • the protective layer 8 after the protective layer 8 is prepared, it will not be peeled off, and the IGZO 6 channel can be protected from damage during the subsequent process.
  • the subsequent passivation layer will also have a large tact time. Greatly reduced.
  • the IGZO transistor structure and the manufacturing method thereof provided by the present invention can avoid damage to the IGZO channel during N-type doping of IGZO by plasma treatment, thereby contributing to improvement of ohmic contact and improvement of device characteristics.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Manufacturing & Machinery (AREA)

Abstract

L'invention concerne un transistor IGZO et un procédé de fabrication associé. Le procédé permettant de fabriquer le transistor IGZO comprend les étapes suivantes : préparer une couche de motif de source/drain et une couche de motif IGZO sur un substrat ; préparer une couche protectrice à la position d'un canal IGZO ; exécuter un dopage de type N à une région où une source/un drain est en contact avec un IGZO au moyen d'un traitement plasma, et former une région n+IGZO ; et préparer une couche d'isolation de grille et une couche de motif de grille. Une détérioration du canal IGZO dans le processus d'exécution du dopage de type N sur l'IGZO au moyen du traitement plasma peut être évitée, ce qui permet d'augmenter un contact ohmique et d'améliorer une caractéristique d'élément.
PCT/CN2013/089623 2013-12-09 2013-12-17 Structure de transistor igzo et son procédé de fabrication WO2015085605A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US14/131,683 US9117912B2 (en) 2013-12-17 2013-12-17 IGZO transistor structure and manufacturing method for the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201310657960.0 2013-12-09
CN201310657960.0A CN103700705B (zh) 2013-12-09 2013-12-09 一种igzo电晶体制造方法

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Publication Number Publication Date
WO2015085605A1 true WO2015085605A1 (fr) 2015-06-18

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104157259B (zh) * 2014-09-10 2016-06-22 深圳市华星光电技术有限公司 基于igzo制程的栅极驱动电路
CN104409635B (zh) * 2014-12-16 2017-02-22 京东方科技集团股份有限公司 一种有机薄膜晶体管及其制作方法、阵列基板、显示装置
WO2016127372A1 (fr) * 2015-02-12 2016-08-18 深圳市柔宇科技有限公司 Transistor à couches minces à porte supérieure, substrat de matrice et son procédé de fabrication, et dispositif tft

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US20120211755A1 (en) * 2011-02-17 2012-08-23 Sony Corporation Thin film transistor, manufacturing method of thin film transistor and display
CN102655165A (zh) * 2011-03-28 2012-09-05 京东方科技集团股份有限公司 一种非晶氧化物薄膜晶体管及其制作方法、显示面板
CN103337522A (zh) * 2013-06-17 2013-10-02 南京中电熊猫液晶显示科技有限公司 一种金属氧化物薄膜晶体管阵列基板及其制造方法
CN103403849A (zh) * 2011-02-28 2013-11-20 夏普株式会社 半导体装置及其制造方法以及显示装置

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KR102047354B1 (ko) * 2010-02-26 2019-11-21 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
CN103299430A (zh) * 2010-12-30 2013-09-11 周星工程股份有限公司 薄膜晶体管及其制造方法
JP6013685B2 (ja) * 2011-07-22 2016-10-25 株式会社半導体エネルギー研究所 半導体装置
CN102636927B (zh) * 2011-12-23 2015-07-29 京东方科技集团股份有限公司 阵列基板及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120211755A1 (en) * 2011-02-17 2012-08-23 Sony Corporation Thin film transistor, manufacturing method of thin film transistor and display
CN103403849A (zh) * 2011-02-28 2013-11-20 夏普株式会社 半导体装置及其制造方法以及显示装置
CN102655165A (zh) * 2011-03-28 2012-09-05 京东方科技集团股份有限公司 一种非晶氧化物薄膜晶体管及其制作方法、显示面板
CN103337522A (zh) * 2013-06-17 2013-10-02 南京中电熊猫液晶显示科技有限公司 一种金属氧化物薄膜晶体管阵列基板及其制造方法

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CN103700705A (zh) 2014-04-02
CN103700705B (zh) 2017-07-28

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