JP2931568B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of semiconductor manufacturing, and more particularly to a MOS transistor which is a basic element of a semiconductor device such as a DRAM.
r) and a method for producing the same.

[0002]

2. Description of the Related Art Conventionally, generally, in order to increase the degree of integration of semiconductor devices such as DRAMs, it is necessary to reduce the size of elements such as MOS transistors. In order to reduce the size of the MOS transistor, it is necessary to increase the doping of the impurity in the channel region of the MOS transistor. However, if the doping of the impurity is increased, the parasitic capacitance of the MOS transistor is reduced.
capacitance) is increased.

[0003] When the size of the MOS transistor is reduced, the MOS transistor is deteriorated.
n), the operating voltage must be low to maintain the life of the MOS transistor. For this reason, there is a problem that as the integration degree of the MOS transistor increases, the power consumption increases due to the parasitic capacitance and the operation speed decreases. In addition, the length of the channel of the MOS transistor is short, and the electric field generated in the drain region affects the source region.
There is a problem that leakage current increases due to a lower lowering phenomenon and a punch-through phenomenon.

As a method for resolving such a problem, an SOI (Silicon On) as shown in FIG.
An Insulator structure has been proposed. Reference numeral 11 denotes a silicon wafer, 12 denotes a buried oxide film, 13 denotes a source,
14 is a drain, 15 is a channel region, 16 is a gate oxide film, and 17 is a gate electrode. In this case, the insulating film between the substrate and the substrate is mainly formed of a silicon oxide film and is called a buried oxide film. The buried oxide film 12 reduces the parasitic capacitance and increases the operation speed of the circuit. .

However, since the silicon oxide film has a thermal conductivity of only 1/100 as compared with silicon, the heat generated from the MOS transistor is difficult to transfer to the lower side. For this reason, the temperature of the semiconductor chip increases, which causes a decrease in chip performance.

In a MOS transistor, a buried oxide film 1 is used.
2, the drain electric field penetrates below and greatly increases the leakage current of the MOS transistor. Such characteristics and the like become worse as the size of the MOS transistor becomes smaller.

The most ideal form of a MOS transistor is
The doping form of the channel region under the gate oxide film is
At a certain depth (e.g., a depth of 300 [ deg .]) Directly below the gate oxide, low doping is maintained (e.g.
¹⁶ cm ⁻³ or less), to increase the mobility of electrons or holes to increase the current driving capability, and to rapidly increase the impurity concentration in the region below (for example, 5 × 10 ¹⁷ cm ⁻³ or more). , DI
By preventing BL and punch-through, the impurity concentration is reduced again at a constant depth (for example, a depth of 1000 ° ) so that the source / drain parasitic capacitance is kept small. is there.

However, it is very difficult to realize a transistor having such a structure. The reason is,
As described above, even if the arrangement of the impurities is once ideal, when the gate oxide film is grown at a high temperature, which will go through almost all the manufacturing processes of the semiconductor device, the impurities diffused to the lower side will not This is because the parasitic capacitance is increased, and the impurity diffused upward decreases the current driving capability.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve such a conventional problem.
It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which improve the thermal conductivity of the I structure.

Another object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which effectively improve the punch-through or DIBL phenomenon caused by the drain electric field.

[0011]

According to a first aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate; a first insulating film, a polysilicon film, and a second insulating film sequentially stacked on the semiconductor substrate. A second insulating film, and a semiconductor layer formed on the second insulating film to provide an active region in which a MOS transistor is formed, wherein the polysilicon film is a path for releasing heat generated from the MOS transistor. Is provided.

According to a second aspect of the present invention, in the semiconductor device of the first aspect, the first insulating film and the second insulating film are oxide films.

According to a third aspect of the present invention, in the semiconductor device of the first aspect, the first insulating film and the second insulating film are an oxide film, a nitride film, and an oxide film, respectively, which are sequentially stacked. And

According to a fourth aspect of the present invention, in the semiconductor device of the first aspect, the polysilicon film is entirely doped at a concentration of 1 × 10 ¹⁶ cm ⁻³ or less.

According to a fifth aspect of the present invention, in the semiconductor device of the first aspect, the polysilicon film is formed of the M
At least 1 × 10
It has an impurity doping region doped at a concentration of ¹⁷ cm ^-3 .

According to a sixth aspect of the present invention, there is provided a semiconductor device.
6. The semiconductor device according to claim 5, wherein the first insulating film and the second insulating film each have a thickness of 50 to 150 °.

According to a seventh aspect of the present invention, in the semiconductor device of the fifth aspect, the impurity-doped region blocks a path through which an electric field generated at the drain penetrates the semiconductor substrate.

The method of manufacturing a semiconductor device according to claim 8 is
A first step of forming a first insulating film on a first semiconductor substrate;
A second step of forming a polysilicon film on the first insulating film, and a third step of forming a second insulating film on the polysilicon film.
A step of bonding the second semiconductor substrate to the second insulating film, a fifth step of removing an upper portion of the first or second semiconductor substrate to a predetermined thickness by a chemical / mechanical polishing method, After performing the fifth step, forming a gate insulating film and a gate electrode on the first or second semiconductor substrate.
And a seventh step of forming a bonding layer by implanting impurity ions to a predetermined thickness.

According to a ninth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
9. The method of manufacturing a semiconductor device according to claim 8, further comprising an eighth step of forming a thin oxide film on the second semiconductor substrate for improving an adhesive force after performing the third step. Features.

According to a tenth aspect of the present invention, in the method for manufacturing a semiconductor device according to the eighth aspect, the first insulating film and the second insulating film are oxide films.

According to an eleventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the eighth aspect, wherein the first insulating film and the second insulating film are sequentially stacked, respectively. It is characterized by being.

According to a twelfth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the eighth to tenth aspects, in the second step, the polysilicon film is entirely formed by one. It is characterized by being doped to a concentration of × 10 ¹⁶ cm ⁻³ or less.

According to a thirteenth aspect of the present invention, in the method of manufacturing a semiconductor device according to any one of the eighth to tenth aspects, in the seventh step, when forming the bonding layer, The implanted impurity is implanted up to the polysilicon film to form an impurity doping region in the silicon film.

According to a fourteenth aspect of the present invention, in a method of manufacturing a semiconductor device according to the thirteenth aspect,
The impurity doped region is at least 1 × 10 ¹⁷ cm
^It has an impurity doping concentration of ^-3 .

[0025]

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to FIGS. Note that the same reference numerals are given to portions and portions common to the embodiments, and redundant description will be omitted.

As shown in FIG. 2, the silicon wafer 21
To form a thin oxide film 22a of about 50 to 200 Å thick on top. At this time, thermal oxidation (t) is performed to form the oxide film 22a.
Thermal oxidation can be performed, or can be formed by deposition.

As shown in FIG. 3, after the polysilicon film 28 is deposited, the surface of the polysilicon film 28 is thermally oxidized to form the oxide film 22b again. At this time, the polysilicon film 28 has very excellent thermal conductivity as compared with the silicon oxide film.
Here, the oxide film 22b is also formed of the polysilicon film 28.
Can be formed on the upper part by a vapor deposition method.

Next, FIG. 4 shows a thin oxide film (not shown) formed on another silicon wafer 25 to improve the adhesive strength, and then an oxide film 22b formed on the upper portion of the silicon wafer 21. It is a diagram illustrating a state in which they are bonded.

Next, FIG. 5 shows that the upper part of the silicon wafer 21 is subjected to chemical mechanical polishing (CMP: Chemical M).
The desired thickness (junction layer (junc) can be obtained by polishing using a mechanical polishing process.
Only the silicon wafer 21 having a thickness necessary for the formation of the silicon wafer 21 is left.

Subsequently, as shown in FIG. 6, a gate oxide film 26 and a gate electrode 27 are formed on the entire structure by a usual method.
And then ion-implanting a conductive impurity to form a source 2
3 and the drain 24 are formed.

This is to use a structure in which a polysilicon film 28 and thin oxide films 22a and 22b are formed on both sides of the polysilicon film 28 instead of the buried oxide film 12 in the conventional SOI structure shown in FIG. At this time, the polysilicon film 28 has a certain impurity doping concentration at the time of VTH ion implantation for adjusting the threshold voltage of the MOS transistor. In one embodiment of the present invention, the polysilicon film 28 has a concentration of about 1 × 10 ^16. Doping is performed to a low concentration of not more than cm ⁻³ .

The feature of the MOS transistor formed on such a structure is that the composite structure of the oxide film 22a, the polysilicon film 28, and the oxide film 22b has a parasitic structure of the source / drain region like a buried oxide film of a conventional SOI structure. The purpose is to allow heat generated during the operation of the MOS transistor to be easily conducted to the lower side while serving to lower the capacitance.

FIG. 7 shows a MOS transistor according to another embodiment of the present invention. The thickness of the silicon wafer 21 is much thinner than that shown in FIG. The impurity diffusion region is formed to a lower portion of the oxide film 22b by forming the thickness of the composite layer of the polysilicon film 28 and the oxide film 22b to be considerably thin. At this time, source / drain 2
The junctions 3 and 24 are limited to the upper portion of the oxide film 22a so that the impurity diffusion region is formed inside the polysilicon film 28. Here, the impurity doping concentration below the source / drain 23 and 24 of the polysilicon film 28 to be used is set to 5 × 10 ¹⁷ cm ⁻³ or more. Accordingly, the doped polysilicon film 28 is located in a path where the electric field generated from the drain affects the source, so that the punch-through or DIBL phenomenon can be effectively improved. Further, the silicon wafer 21 on which the subsequent active region is formed can maintain low doping. At this time, an effect of preventing the impurities contained in the polysilicon film 28 from being diffused by the oxide films 22a and 22b even after a high heat treatment in the transistor manufacturing process can be obtained. If such an oxide film is too thin to prevent the diffusion of impurities effectively, an oxide film-nitride-oxide film (ONO, oxide-nitride-oxide) may be used instead of the oxide films 22a and 22b.
Structures are available.

In the embodiment of the present invention described above, the polysilicon film 2
8 may use silicon or another material film having excellent thermal conductivity.

[0036]

As described above, according to the present invention, the heat transfer characteristics are improved as compared with the conventional SOI structure, and the effect that the drain electric field permeates the lower silicon substrate is greatly reduced. Therefore, the punch-through or DIBL phenomenon is greatly reduced. In particular, when the doping concentration of the polysilicon film is kept low as in the case of the embodiment, the polysilicon film is depleted and acts just like an insulating film, so that the parasitic capacitance can be reduced. This has the effect of reducing power consumption and improving operation speed.

As described above, the present invention is not limited to the above-described embodiments and drawings, and various substitutions and changes can be made without departing from the technical idea of the present invention. Of course.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a conventional MOS transistor having an SOI structure.

FIG. 2 is a sectional view showing a product in one step of manufacturing a MOS transistor according to one embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a product in one step of manufacturing a MOS transistor according to one embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a product in one step of manufacturing a MOS transistor according to one embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a product in one step of manufacturing a MOS transistor according to one embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a product in one step of manufacturing a MOS transistor according to one embodiment of the present invention.

FIG. 7 is a cross-sectional view of a MOS transistor according to another embodiment of the present invention.

[Explanation of symbols]

 11, 21, 25 Silicon wafer (semiconductor substrate) 12 Buried oxide film 13, 23 Source 14, 24 Drain 15 Channel region 16, 26 Gate oxide film 17, 27 Gate electrode 22a, 22b Oxide film 28 Polysilicon film

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-1-206468 (JP, A) JP-A-56-111258 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/336 H01L 29/786

Claims (14)

(57) [Claims] A semiconductor substrate; a first insulating film, a polysilicon film, and a second insulating film sequentially stacked on the semiconductor substrate; and an active element formed on the second insulating film to form a MOS transistor. A semiconductor device comprising a semiconductor layer providing a region, wherein the polysilicon film provides a path for releasing heat generated from the MOS transistor. 2. The semiconductor device according to claim 1, wherein said first insulating film and said second insulating film are oxide films. 3. The semiconductor device according to claim 1, wherein the first insulating film and the second insulating film are an oxide film, a nitride film, and an oxide film, which are sequentially stacked. 4. The polysilicon film has a total thickness of 1 × 10
The semiconductor device according to claim 1, wherein the semiconductor device is doped to a concentration of ¹⁶ cm- ³ or less. 5. The semiconductor device according to claim 1, wherein said polysilicon film has an impurity doping region doped at a concentration of at least 1 × 10 ¹⁷ cm ^-3 under a junction layer of said MOS transistor. . 6. The semiconductor device according to claim 1, wherein said first insulating film and said second insulating film each have a thickness of 50 to 150 °. 7. The semiconductor device according to claim 5, wherein the impurity-doped region blocks a path through which an electric field generated at the drain penetrates into the semiconductor substrate. 8. A first step of forming a first insulating film on a first semiconductor substrate, a second step of forming a polysilicon film on the first insulating film, and a second insulating film on the polysilicon film. A third step of forming a film, a fourth step of bonding the second semiconductor substrate to the second insulating film, and removing the upper portion of the first or second semiconductor substrate to a predetermined thickness by a chemical / mechanical polishing method. A fifth step of forming a gate insulating film and a gate electrode on the first or second semiconductor substrate after performing the fifth step, and performing impurity ion implantation to a predetermined thickness. And a seventh step of forming a bonding layer by a method. 9. The method of claim 8, further comprising, after performing the third step, forming an oxide thin film on the second semiconductor substrate to improve adhesion. Of manufacturing a semiconductor device. 10. The method according to claim 8, wherein said first insulating film and said second insulating film are oxide films. 11. The method according to claim 8, wherein the first insulating film and the second insulating film are an oxide film, a nitride film, and an oxide film, which are sequentially stacked. 12. The method according to claim 8, wherein in the second step, the polysilicon film is doped at a concentration of 1 × 10 ¹⁶ cm ⁻³ or less. Of manufacturing a semiconductor device. 13. The method according to claim 7, wherein, in the forming of the bonding layer, the ion-implanted impurity is implanted up to the polysilicon film to form an impurity-doped region in the silicon film. The method of manufacturing a semiconductor device according to claim 8. 14. The method according to claim 13, wherein the impurity doping region has an impurity doping concentration of at least 1 × 10 ¹⁷ cm ⁻³ .