CN111430446A - Thin film transistor device, driving circuit and display device - Google Patents
Thin film transistor device, driving circuit and display device Download PDFInfo
- Publication number
- CN111430446A CN111430446A CN201910020460.3A CN201910020460A CN111430446A CN 111430446 A CN111430446 A CN 111430446A CN 201910020460 A CN201910020460 A CN 201910020460A CN 111430446 A CN111430446 A CN 111430446A
- Authority
- CN
- China
- Prior art keywords
- layer
- source
- doping
- drain
- thin film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 78
- 230000004888 barrier function Effects 0.000 claims abstract description 129
- 239000000758 substrate Substances 0.000 claims abstract description 26
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- 238000005036 potential barrier Methods 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000001965 increasing effect Effects 0.000 abstract description 15
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 206010047571 Visual impairment Diseases 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 309
- 238000010586 diagram Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 10
- 239000011521 glass Substances 0.000 description 9
- 230000008569 process Effects 0.000 description 7
- 238000001259 photo etching Methods 0.000 description 5
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 230000002708 enhancing effect Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052787 antimony Inorganic materials 0.000 description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011368 organic material Substances 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 239000002096 quantum dot Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000011787 zinc oxide Substances 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 238000005984 hydrogenation reaction Methods 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thin Film Transistor (AREA)
Abstract
The application is applicable to the technical field of semiconductor devices, and provides a thin film transistor device, a driving circuit and a display device, wherein the thin film transistor device comprises a substrate, a gate layer arranged on the substrate, a barrier layer arranged on the gate layer, an active layer arranged on the surface of the barrier layer, a source barrier layer and a drain barrier layer arranged on the surface of the active layer, a source electrode layer arranged on the surface of the source barrier layer and a drain electrode layer arranged on the surface of the drain barrier layer, wherein the source barrier layer comprises at least two source doping layers with different doping concentrations, the drain barrier layer comprises at least two drain doping layers with different doping concentrations, the barrier energy barrier in the thin film transistor is increased, the stability of the thin film transistor is improved, the ghost phenomenon of a display panel is improved, the back channel interface state in the thin film transistor structure etched by a back channel is improved, the purpose of eliminating the afterimage of the display panel.
Description
Technical Field
The application relates to the technical field of semiconductor devices, in particular to a thin film diode device, a driving circuit and a display device.
Background
In the manufacturing technology of the TFT, a Back Channel Etching (BCE) process is a common process of an amorphous silicon TFT, and the TFT can be formed by only four times of photoetching, namely a first photoetching process for forming a grid electrode of the TFT, a second photoetching process for forming a semiconductor layer of the TFT, a third photoetching process for forming a source electrode and a drain electrode of the TFT, a fourth photoetching process for forming a passivation layer through hole of the TFT, and the BCE process only needs four masks and fewer process steps and is widely adopted by the existing production line of the amorphous silicon (a-Si) TFT panel.
However, the back channel interface state in the conventional back channel etched thin film transistor structure is poor, which may cause the leakage of the thin film transistor to be large, thereby causing the display panel to generate the phenomenon of image sticking.
Disclosure of Invention
An object of the present application is to provide a thin film diode device, which aims to achieve the purposes of improving the back channel interface state in the thin film transistor structure of back channel etching, reducing the electric leakage of the thin film transistor, and eliminating the afterimage of the display panel.
The present application is embodied as a thin film diode device, comprising:
a substrate;
the gate electrode layer is arranged on the substrate, the surface of the substrate comprises a first preset area and a second preset area, and the gate electrode layer is arranged in the first preset area on the surface of the substrate;
the barrier layer is arranged on the gate layer and is arranged on the surface of the gate layer and a second preset area on the surface of the substrate;
the active layer is arranged on the surface of the barrier layer, the surface of the active layer comprises a third preset area and a fourth preset area, and the third preset area is not contacted with the fourth preset area;
the source barrier layer and the drain barrier layer are arranged on the surface of the active layer, wherein the source barrier layer comprises at least two source doping layers with different doping concentrations, the drain barrier layer comprises at least two drain doping layers with different doping concentrations, the source barrier layer is positioned in a third preset area on the surface of the active layer, and the drain barrier layer is positioned in a fourth preset area on the surface of the active layer;
the source electrode layer is arranged on the surface of the source electrode barrier layer; and
and the drain layer is arranged on the surface of the drain potential barrier layer.
Optionally, the source barrier layer includes:
the first source electrode doping layer is arranged on the surface of the active layer, and the first source electrode doping layer is located in a third preset area on the surface of the active layer;
the second source electrode doping layer is arranged on the surface of the first source electrode doping layer;
the third source electrode doping layer is arranged on the surface of the second source electrode doping layer; and
the fourth source electrode doping layer is arranged on the surface of the third source electrode doping layer;
the doping concentrations of the first source doping layer, the second source doping layer, the third source doping layer and the fourth source doping layer are different from each other.
Optionally, the first source doping layer has a first source doping concentration, the second source doping layer has a second source doping concentration, the third source doping layer has a third source doping concentration, and the fourth source doping layer has a fourth source doping concentration;
the first source doping concentration is less than the second source doping concentration, the second source doping concentration is less than the third source doping concentration, and the third source doping concentration is less than the fourth source doping concentration.
Optionally, the drain barrier layer comprises:
the first drain electrode doping layer is arranged on the surface of the active layer and is positioned in a fourth preset area on the surface of the active layer;
the second drain electrode doping layer is arranged on the surface of the first drain electrode doping layer;
the third drain electrode doping layer is arranged on the surface of the second drain electrode doping layer; and
the fourth drain electrode doping layer is arranged on the surface of the third drain electrode doping layer;
the first drain doped layer, the second drain doped layer, the third drain doped layer, and the fourth drain doped layer have different doping concentrations.
Optionally, the barrier layer includes at least one of silicon nitride and silicon dioxide.
Optionally, the source doped layer is doped N-type.
Optionally, the active layer is amorphous silicon.
Optionally, the amorphous silicon is hydrogenated amorphous silicon.
It is another object of the present application to provide a driver circuit comprising a thin film transistor device as claimed in any one of the above.
It is still another object of the present application to provide a display device including:
a display panel; and
a control unit electrically connected to the display panel, the control unit including the thin film transistor device as described in any one of the above.
In an embodiment of the present application, a thin film transistor device, a driving circuit and a display apparatus are provided, the thin film transistor device includes a substrate, a gate layer disposed on the substrate, a barrier layer disposed on the gate layer, an active layer disposed on the barrier layer, and a source barrier layer and a drain barrier layer disposed on the surface of the active layer, wherein the source barrier layer includes at least two source doping layers with different doping concentrations, the drain barrier layer includes at least two drain doping layers with different doping concentrations, the source barrier layer is located in a third preset region on the surface of the active layer, the drain barrier layer is located in a fourth preset region on the surface of the active layer, the source barrier layer includes at least two source doping layers with different doping concentrations, and the drain barrier layer includes at least two drain doping layers with different doping concentrations, the method has the advantages that potential barrier energy barriers inside the thin film transistor are increased, the stability of the thin film transistor is improved, the image sticking phenomenon of the display panel is improved, the back channel interface state in the thin film transistor structure with back channel etching is improved, the electric leakage of the thin film transistor is reduced, and the image sticking phenomenon of the display panel is eliminated.
Drawings
Fig. 1 is a schematic structural diagram of a thin film transistor device provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of a thin film transistor device provided in an embodiment of the present application;
fig. 3 is a schematic energy band diagram of a thin film transistor device provided in an embodiment of the present application;
fig. 4 is a schematic structural diagram of a thin film transistor device provided in an embodiment of the present application;
fig. 5 is a schematic energy band diagram of a thin film transistor device provided in an embodiment of the present application;
fig. 6 is a schematic structural diagram of a thin film transistor device provided in an embodiment of the present application;
fig. 7 is a schematic structural diagram of a thin film transistor device according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It will be understood that when an element is referred to as being "secured to" or "disposed on" another element, it can be directly or indirectly secured to the other element. When an element is referred to as being "connected to" another element, it can be directly or indirectly connected to the other element. The terms "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positions based on the orientations or positions shown in the drawings, and are for convenience of description only and not to be construed as limiting the technical solution. The terms "first", "second" and "first" are used merely for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of "plurality" is two or more unless specifically limited otherwise.
In order to explain the technical solutions of the present application, the following detailed descriptions are made with reference to specific drawings and examples.
Referring to fig. 1, as shown in fig. 1, a thin film diode device provided in an embodiment of the present application includes:
a substrate 10;
the gate layer 20 is arranged on the substrate 10, wherein the surface of the substrate 10 includes a first preset region and a second preset region, and the gate layer 20 is arranged on the first preset region on the surface of the substrate 10;
a barrier layer 30 disposed on the gate layer 20, wherein the barrier layer 30 is disposed on the surface of the gate layer 20 and a second predetermined region of the surface of the substrate 10;
the active layer 40 is arranged on the surface of the barrier layer 30, the surface of the active layer 40 comprises a third preset region and a fourth preset region, and the third preset region and the fourth preset region are not in contact with each other;
the source barrier layer 51 and the drain barrier layer 52 are arranged on the surface of the active layer 40, wherein the source barrier layer 51 comprises at least two source doped layers with different doping concentrations, the drain barrier layer 52 comprises at least two drain doped layers with different doping concentrations, the source barrier layer 51 is positioned in a third preset region on the surface of the active layer 40, and the drain barrier layer 52 is positioned in a fourth preset region on the surface of the active layer 40;
a source layer 61 provided on the surface of the source barrier layer 51; and
and a drain layer 62 provided on a surface of the drain barrier layer 52.
In this embodiment, the source barrier layer 51 includes at least two source doping layers with different doping concentrations, and the drain barrier layer 52 includes at least two drain doping layers with different doping concentrations, so that a barrier energy barrier inside the thin film transistor device can be increased, thereby achieving a purpose of reducing a leakage current of the thin film transistor, and improving a ghost phenomenon of the display panel.
In one embodiment, the substrate 10 may be a glass substrate, and the thin film transistor device may be directly integrated on the display panel glass by forming the thin film transistor device on the glass substrate, which greatly reduces the volume of the display device.
In one embodiment, the glass substrate 10 may be a flexible glass, and by forming the thin film transistor device on the flexible glass, the application scenario of the display panel may be greatly expanded.
In one embodiment, the glass substrate 10 may be a rigid glass. The stiffness of the display panel can be increased by forming the thin film transistor devices on rigid glass.
In one embodiment, referring to fig. 2, the source barrier layer 51 includes:
a first source doping layer 511 disposed on the surface of the active layer 40, wherein the first source doping layer 511 is located in a third predetermined region on the surface of the active layer 40;
a second source doped layer 512 disposed on the surface of the first source doped layer 511;
a third source doped layer 513 disposed on the surface of the second source doped layer 512; and
a fourth source doped layer 514 disposed on the surface of the third source doped layer 513;
the doping concentrations of the first source doping layer 511, the second source doping layer 512, the third source doping layer 513, and the fourth source doping layer 514 are different from each other.
In the present embodiment, the source barrier layer 51 includes four source doping layers, the doping concentrations of the four source doping layers are different from each other, and the source doping layers with different doping concentrations are used to increase the barrier energy barrier in the thin film transistor, so that the energy barrier in the source barrier layer 51 is increased step by step, thereby enhancing the stability of the thin film transistor.
In one embodiment, the source doped layer is doped N-type. In the present embodiment, the source doping layer is formed by doping an N-type element in polysilicon, and specifically, the concentration of the N-type element doped in the multi-layer source doping layer in the source barrier layer 51 is different.
In one embodiment, the N-type element doped in the source doped layer may be at least one of phosphorus, arsenic, and antimony.
In one embodiment, the first source doped layer 511 has a first source doping concentration, the second source doped layer 512 has a second source doping concentration, the third source doped layer 513 has a third source doping concentration, and the fourth source doped layer 514 has a fourth source doping concentration;
the first source doping concentration is less than the second source doping concentration, the second source doping concentration is less than the third source doping concentration, and the third source doping concentration is less than the fourth source doping concentration.
In this embodiment, the doping concentrations of the first source doping layer 511, the second source doping layer 512, the third source doping layer 513 and the fourth source doping layer 514 are increased step by step. By increasing the doping concentration of the multiple source doping layers in the source barrier layer 51 layer by layer, electrons gradually cross the higher energy level barrier when passing through the source doping layers, thereby reducing the leakage of the thin film transistor and improving the image sticking phenomenon of the display panel.
In one embodiment, referring to fig. 2, the drain barrier layer 52 comprises:
a first drain doped layer 521 disposed on the surface of the active layer 40, wherein the first drain doped layer 521 is located in a fourth predetermined region on the surface of the active layer 40;
a second drain doping layer 522 disposed on the surface of the first drain doping layer 521;
a third drain doped layer 523 disposed on the surface of the second drain doped layer 522; and
a fourth drain doped layer 524 disposed on the surface of the third drain doped layer 523;
the doping concentrations of the first drain doping layer 521, the second drain doping layer 522, the third drain doping layer 523, and the fourth drain doping layer 524 are different from each other.
In the present embodiment, the drain barrier layer 52 includes four drain doping layers, the doping concentrations of the four drain doping layers are different from each other, and the four drain doping layers with different doping concentrations are used to increase the barrier energy barrier in the thin film transistor, that is, the energy barrier is increased step by step, thereby enhancing the stability of the thin film transistor.
In one embodiment, the drain doped layer is doped N-type. The drain doping layer is formed by doping an N-type element in the polysilicon, and specifically, the concentration of the N-type element doped in the multi-layered source doping layer in the drain barrier layer 52 is different.
In one embodiment, the doped N-type element in the drain doped layer may be at least one of phosphorus, arsenic, and antimony.
In one embodiment, the first drain doping layer 521 has a first drain doping concentration, the second drain doping layer 522 has a second drain doping concentration, the third drain doping layer 523 has a third drain doping concentration, and the fourth drain doping layer 524 has a fourth drain doping concentration; wherein the first drain doping concentration is less than the second drain doping concentration, the second drain doping concentration is less than the third drain doping concentration, and the third drain doping concentration is less than the fourth drain doping concentration. By increasing the doping concentration of the multiple drain doping layers in the drain barrier layer 52 layer by layer, electrons gradually cross a higher energy level barrier when passing through the drain doping layers, thereby reducing the leakage of the thin film transistor and improving the image sticking phenomenon of the display panel.
Fig. 3 is a schematic energy band diagram of the source barrier layer 51 including four source doping layers and the drain barrier layer 52 including four drain doping layers, as shown in fig. 3, the conduction band and the valence band of the thin film transistor device gradually increase, and at this time, the voltage variation of the transistor decreases, and the stability of the signal increases.
In one embodiment, the barrier layer 30 may be an insulator. By using the insulator as the resistance layer 30, electron transmission between the active layer 40 and the gate electrode layer 20 can be isolated, thereby preventing the thin film transistor device from generating electric leakage or short circuit during operation.
In one embodiment, the barrier layer 30 comprises at least one of silicon nitride, silicon dioxide. Can be isolated by barrier layer 30
In one embodiment, the barrier layer 30 may also be a combination of one or more of silicon oxide, silicon nitride, silicon oxide, zirconium oxide, and organic materials.
In one embodiment, the barrier layer 30 has a thickness of 5nm to 300 nm. In one embodiment, the active layer 40 is amorphous silicon.
In one embodiment, the amorphous silicon is hydrogenated amorphous silicon, and the dangling bonds in the amorphous silicon are filled with hydrogen, so that the density of the dangling bonds of the hydrogenated amorphous silicon after hydrogenation is significantly reduced, and the density of the interstitial states is reduced to be less than 10E16/cm3, thereby reducing the probability of recombination of carriers through the interstitial states, and enabling the active layer 40 to show better electrical performance.
In one embodiment, the active layer 40 may also be polysilicon.
In one embodiment, the active layer 40 may also be an N-type metal oxide thin film material such as zinc oxide, indium zinc oxide, boron doped zinc oxide, and the like.
In one embodiment, the active layer 40 may also be silicon, germanium, silicon-germanium alloy, and other compound semiconductor thin films.
In one embodiment, the active layer 40 has a thickness of 10nm to 500 nm.
In one embodiment, as shown in fig. 4, the source barrier layer 51 includes:
a fifth source doped layer 515 disposed on the surface of the active layer 40, wherein the fifth source doped layer 515 is located in a third predetermined region on the surface of the active layer 40;
a sixth source doped layer 516 disposed on the surface of the fifth source doped layer 515; and
a seventh source doped layer 517 disposed on the surface of the sixth source doped layer 516;
the doping concentrations of the fifth source doped layer 515, the sixth source doped layer 516, and the seventh source doped layer 517 are different from each other.
In one embodiment, the source barrier layer 51 includes three source doping layers, the doping concentrations of the three source doping layers are different from each other, and the barrier energy barrier in the thin film transistor is increased by using the three source doping layers with the doping concentrations different from each other, that is, the energy barrier is increased step by step, so that the stability of the thin film transistor is enhanced.
In one embodiment, the fifth source doped layer 515 has a fifth source doping concentration, the sixth source doped layer 516 has a sixth source doping concentration, and the seventh source doped layer 517 has a seventh source doping concentration; the fifth source doping concentration is less than the sixth source doping concentration, and the sixth source doping concentration is less than the seventh source doping concentration. By increasing the doping concentration of the multiple source doping layers in the source barrier layer 51 layer by layer, electrons gradually cross the higher energy level barrier when passing through the source doping layers, thereby reducing the leakage of the thin film transistor and improving the image sticking phenomenon of the display panel.
In one embodiment, the sixth source doped layer 516 may be hydrogenated amorphous silicon.
In one embodiment, as shown in fig. 4, the drain barrier layer 52 includes:
a fifth drain doped layer 525 disposed on the surface of the active layer 40, wherein the fifth drain doped layer 525 is located in a fourth predetermined region on the surface of the active layer 40;
a sixth drain doping layer 526 disposed on the surface of the fifth drain doping layer 525; and
a seventh drain doping layer 527 disposed on the surface of the sixth drain doping layer 526;
the doping concentrations of the fifth drain doping layer 525, the sixth drain doping layer 526, and the seventh drain doping layer 527 are different from each other.
In the present embodiment, the drain barrier layer 52 includes four drain doping layers, the doping concentrations of the four drain doping layers are different from each other, and the four drain doping layers with different doping concentrations are used to increase the barrier energy barrier in the thin film transistor, that is, the energy barrier is increased step by step, thereby enhancing the stability of the thin film transistor.
In one embodiment, the fifth drain doped layer 525 has a fifth drain doping concentration, the sixth drain doped layer 526 has a sixth drain doping concentration, and the seventh drain doped layer 527 has a seventh drain doping concentration; the fifth drain doping concentration is less than the sixth drain doping concentration, which is less than the seventh drain doping concentration. By increasing the doping concentration of the multiple drain doping layers in the drain barrier layer 52 layer by layer, electrons gradually cross the higher energy level barrier when passing through the drain doping layers, thereby reducing the leakage of the thin film transistor and improving the image sticking phenomenon of the display panel
In this embodiment, the doping concentrations of the fifth drain doping layer 525, the sixth drain doping layer 526 and the seventh drain doping layer 527 gradually increase.
Fig. 5 is a schematic energy band diagram of the case where the source barrier layer 51 includes three source doping layers and the drain barrier layer 52 includes three drain doping layers, as shown in fig. 5, the barrier energy of the thin film transistor device rises, and at this time, the voltage variation of the transistor falls, and the stability of the signal is improved.
Under the conditions of 4000 seconds of illumination and 70 ℃ of temperature, the voltage variation of the thin film transistor with the source barrier layer 51 comprising a single-layer source doping layer and the drain barrier layer 52 comprising a single-layer drain doping layer is-4V, the maximum current reached under the voltage of 20V is 7.71E-6A, and the leakage current reached under the voltage of-6V is 2.24E-11A; the voltage variation of the thin film transistor in which the source barrier layer 51 includes three source doping layers and the drain barrier layer 52 includes three drain doping layers is-3.2V, the maximum current reached at a voltage of 20V is 6.74E-6A, and the leakage current reached at a voltage of-6V is 1.94E-11A; the source barrier layer 51 includes four source doping layers and the drain barrier layer 52 includes four drain doping layers, the variation of voltage of the thin film transistor is-2, 6V, the maximum current reached at a voltage of 20V is 8.49E-6A, and the leakage current reached at a voltage of-6V is 1.35E-12A. As can be seen, when the source doping layer included in the source barrier layer 51 gradually increases and the drain doping layer included in the drain barrier layer 52 gradually increases, the barrier energy of the thin film transistor gradually decreases and the voltage variation amount also gradually decreases.
By comparing the image sticking comparison graph of the tft device applied to the display device, it can be seen that when the source barrier layer 51 includes three source doping layers and the drain barrier layer 52 includes three drain doping layers, the image sticking pattern of the display panel is better improved than the image sticking pattern of the display panel using the tft in which the source barrier layer 51 includes a single source doping layer and the drain barrier layer 52 includes a single drain doping layer, and at this time, the display panel only has a slight image sticking. When the source barrier layer 51 includes four source doped layers and the drain barrier layer 52 includes four drain doped layers, the uniformity of the pattern of the display panel is relatively uniform, and the afterimage phenomenon after the image aging is greatly improved.
Fig. 6 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure, and as shown in fig. 6, an insulating filling layer 70 is further disposed between the source barrier layer 51 and the drain barrier layer 52.
In one embodiment, the insulating filling layer 70 may be one or a combination of silicon oxide, silicon nitride, silicon oxide, zirconium oxide and organic material.
Fig. 7 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure, and as shown in fig. 7, a source electrode 81 is disposed on the source layer 61.
In one embodiment, the source electrode 81 may be made of an alloy of any one or more metals, such as gold, silver, copper, chromium, aluminum, and the like.
In one embodiment, the thickness of the source electrode 81 is 50nm-500 nm.
As shown in fig. 7, a drain electrode 82 is provided on the drain layer 62.
In one embodiment, the drain electrode 82 may be made of an alloy of any one or more of gold, silver, copper, chromium, aluminum, and the like.
In one embodiment, the thickness of the drain electrode 82 is 50nm-500 nm.
In one embodiment, the present application provides a driving circuit including a thin film transistor device as described in any one of the above embodiments.
In one embodiment, the present application provides a display device, including:
a display panel; and
a control unit electrically connected to the display panel, the control unit including the thin film transistor device as described in any one of the above.
In one embodiment, the Display device may be any type of Display device provided with the above-described thin film transistor device, such as a liquid Crystal Display device (L acquired Crystal Display, L CD), an organic electroluminescent Display (O L ED) Display device, a Quantum Dot light emitting diode (Quantum Dot L lighting Diodes, Q L ED) Display device, or a curved Display device.
In one embodiment, the display panel includes a pixel array comprised of rows of pixels and columns of pixels.
In one embodiment, the control Unit may be implemented by a general-purpose integrated circuit, such as a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC).
In an embodiment of the present application, a thin film transistor device, a driving circuit and a display apparatus are provided, the thin film transistor device includes a substrate, a gate layer disposed on the substrate, a barrier layer disposed on the gate layer, an active layer disposed on the barrier layer, and a source barrier layer and a drain barrier layer disposed on the surface of the active layer, wherein the source barrier layer includes at least two source doping layers with different doping concentrations, the drain barrier layer includes at least two drain doping layers with different doping concentrations, the source barrier layer is located in a third preset region on the surface of the active layer, the drain barrier layer is located in a fourth preset region on the surface of the active layer, the source barrier layer includes at least two source doping layers with different doping concentrations, and the drain barrier layer includes at least two drain doping layers with different doping concentrations, the method has the advantages that potential barrier energy barriers inside the thin film transistor are increased, the stability of the thin film transistor is improved, the image sticking phenomenon of the display panel is improved, the back channel interface state in the thin film transistor structure with back channel etching is improved, the electric leakage of the thin film transistor is reduced, and the image sticking phenomenon of the display panel is eliminated.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (10)
1. A thin film transistor device, comprising:
a substrate;
the gate electrode layer is arranged on the substrate, the surface of the substrate comprises a first preset area and a second preset area, and the gate electrode layer is arranged in the first preset area on the surface of the substrate;
the barrier layer is arranged on the gate layer and is arranged on the surface of the gate layer and a second preset area on the surface of the substrate;
the active layer is arranged on the surface of the barrier layer, the surface of the active layer comprises a third preset area and a fourth preset area, and the third preset area is not contacted with the fourth preset area;
the source barrier layer and the drain barrier layer are arranged on the surface of the active layer, wherein the source barrier layer comprises at least two source doping layers with different doping concentrations, the drain barrier layer comprises at least two drain doping layers with different doping concentrations, the source barrier layer is positioned in a third preset area on the surface of the active layer, and the drain barrier layer is positioned in a fourth preset area on the surface of the active layer;
the source electrode layer is arranged on the surface of the source electrode barrier layer; and
and the drain layer is arranged on the surface of the drain potential barrier layer.
2. The thin film transistor device of claim 1, wherein the source barrier layer comprises:
the first source electrode doping layer is arranged on the surface of the active layer, and the first source electrode doping layer is located in a third preset area on the surface of the active layer;
the second source electrode doping layer is arranged on the surface of the first source electrode doping layer;
the third source electrode doping layer is arranged on the surface of the second source electrode doping layer; and
the fourth source electrode doping layer is arranged on the surface of the third source electrode doping layer;
the doping concentrations of the first source doping layer, the second source doping layer, the third source doping layer and the fourth source doping layer are different from each other.
3. The thin film transistor device of claim 2, wherein the first source doped layer has a first source doping concentration, the second source doped layer has a second source doping concentration, the third source doped layer has a third source doping concentration, and the fourth source doped layer has a fourth source doping concentration;
the first source doping concentration is less than the second source doping concentration, the second source doping concentration is less than the third source doping concentration, and the third source doping concentration is less than the fourth source doping concentration.
4. The thin film transistor device of claim 1, wherein the drain barrier layer comprises:
the first drain electrode doping layer is arranged on the surface of the active layer and is positioned in a fourth preset area on the surface of the active layer;
the second drain electrode doping layer is arranged on the surface of the first drain electrode doping layer;
the third drain electrode doping layer is arranged on the surface of the second drain electrode doping layer; and
the fourth drain electrode doping layer is arranged on the surface of the third drain electrode doping layer;
the first drain doped layer, the second drain doped layer, the third drain doped layer, and the fourth drain doped layer have different doping concentrations.
5. The thin film transistor device of claim 1, wherein the barrier layer comprises at least one of silicon nitride, silicon dioxide.
6. The thin film transistor device of claim 1, wherein the source doped layer is doped N-type.
7. The thin film transistor device of claim 1, wherein the active layer is amorphous silicon.
8. The thin film transistor device of claim 7, wherein the amorphous silicon is hydrogenated amorphous silicon.
9. A driver circuit comprising a thin film transistor device according to any one of claims 1 to 8.
10. A display device, comprising:
a display panel; and
the control unit is electrically connected with the display panel; wherein the display panel comprises a thin film transistor device as claimed in any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910020460.3A CN111430446A (en) | 2019-01-09 | 2019-01-09 | Thin film transistor device, driving circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910020460.3A CN111430446A (en) | 2019-01-09 | 2019-01-09 | Thin film transistor device, driving circuit and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111430446A true CN111430446A (en) | 2020-07-17 |
Family
ID=71546110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910020460.3A Withdrawn CN111430446A (en) | 2019-01-09 | 2019-01-09 | Thin film transistor device, driving circuit and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111430446A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000150898A (en) * | 1998-11-17 | 2000-05-30 | Matsushita Electric Ind Co Ltd | Thin-film transistor and its manufacture |
| JP2002076361A (en) * | 2000-09-05 | 2002-03-15 | Sharp Corp | Semiconductor device, its manufacturing method and image display device |
| CN107591411A (en) * | 2017-07-06 | 2018-01-16 | 惠科股份有限公司 | Display panel and display device |
| CN109065632A (en) * | 2018-07-26 | 2018-12-21 | 惠科股份有限公司 | Thin film transistor, manufacturing method thereof and display device |
| CN109119484A (en) * | 2018-07-16 | 2019-01-01 | 惠科股份有限公司 | Thin film transistor and method for manufacturing thin film transistor |
| CN109545690A (en) * | 2018-12-03 | 2019-03-29 | 惠科股份有限公司 | Thin film transistor structure, manufacturing method thereof and display device |
| CN109786440A (en) * | 2018-12-25 | 2019-05-21 | 惠科股份有限公司 | Array substrate manufacturing method and device and array substrate |
-
2019
- 2019-01-09 CN CN201910020460.3A patent/CN111430446A/en not_active Withdrawn
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000150898A (en) * | 1998-11-17 | 2000-05-30 | Matsushita Electric Ind Co Ltd | Thin-film transistor and its manufacture |
| JP2002076361A (en) * | 2000-09-05 | 2002-03-15 | Sharp Corp | Semiconductor device, its manufacturing method and image display device |
| CN107591411A (en) * | 2017-07-06 | 2018-01-16 | 惠科股份有限公司 | Display panel and display device |
| CN109119484A (en) * | 2018-07-16 | 2019-01-01 | 惠科股份有限公司 | Thin film transistor and method for manufacturing thin film transistor |
| CN109065632A (en) * | 2018-07-26 | 2018-12-21 | 惠科股份有限公司 | Thin film transistor, manufacturing method thereof and display device |
| CN109545690A (en) * | 2018-12-03 | 2019-03-29 | 惠科股份有限公司 | Thin film transistor structure, manufacturing method thereof and display device |
| CN109786440A (en) * | 2018-12-25 | 2019-05-21 | 惠科股份有限公司 | Array substrate manufacturing method and device and array substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR102519087B1 (en) | Display device and method for manufacturing the same | |
| KR101944644B1 (en) | Amoled back plate manufacturing method | |
| US10424607B2 (en) | TFT substrate and manufacturing method thereof | |
| TWI524514B (en) | Method of manufacturing organic light emitting display device | |
| EP1865559B1 (en) | Organic light-emitting display device and method for fabricating the same | |
| US20160181387A1 (en) | Thin film transistor and organic light-emitting display | |
| US10331001B2 (en) | TFT substrate and manufacturing method thereof | |
| US20110073863A1 (en) | Organic light emitting diode display | |
| US20190096919A1 (en) | Active matrix substrate, liquid crystal display device, organic electroluminescent display device and method for producing active matrix substrate | |
| US9786791B2 (en) | Thin film transistor, array substrate and method of manufacturing the same | |
| US9741588B2 (en) | Method of manufacturing thin-film transistor substrate | |
| US10529786B2 (en) | Thin-film transistor and organic light-emitting display device including the same | |
| US9570624B2 (en) | Thin film transistor and method for fabricating the same | |
| CN111403418B (en) | Array substrate, manufacturing method thereof and display device | |
| CN113903797B (en) | Active device and method for manufacturing the same | |
| US20210343543A1 (en) | Manufacturing method of thin film transistor | |
| US20020149054A1 (en) | Flat panel display device and method of manufacturing the same | |
| US8815692B2 (en) | Thin film transistor array substrate and method for manufacturing the same | |
| CN111092077B (en) | Double-thin-film transistor, preparation method thereof and display panel | |
| CN102881709B (en) | Organic light emitting diode display device | |
| CN111430446A (en) | Thin film transistor device, driving circuit and display device | |
| US11996418B2 (en) | Display device and manufacturing method | |
| KR102124063B1 (en) | Display device and manufacturing method thereof | |
| KR102235421B1 (en) | Array substrate and method of fabricating the same | |
| JP4811397B2 (en) | Light receiving element and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20200717 |