KR102235421B1 - Array substrate and method of fabricating the same - Google Patents

Abstract

In the present invention, first and second GOLDD regions and the first and second GOLDD regions formed in each pixel region on a substrate in which a plurality of pixel regions are defined, and doped with impurities at a first concentration at both sides of the active region and the active region. A polysilicon semiconductor layer having source and drain regions doped with impurities at a second concentration greater than the first concentration outside the region; A gate insulating film formed over the semiconductor layer of polysilicon; A gate electrode formed over the gate insulating layer and overlapping the active region and the first and second GOLDD regions; An interlayer insulating layer having a semiconductor layer contact hole exposing the source and drain regions over the gate electrode, respectively; An array substrate including source and drain electrodes formed on the interlayer insulating layer and in contact with the source region and the drain region, respectively, and spaced apart from each other through the semiconductor layer contact hole, and a method of manufacturing the same.

Description

Array substrate and method of fabricating the same}

The present invention relates to an array substrate, in particular, an array substrate comprising a thin film transistor having a semiconductor layer of polysilicon, and capable of improving device characteristics and reliability by reducing the off current (Ioff) of the thin film transistor, and a method of manufacturing the same It is about.

In recent years, as society enters the era of full-fledged information, the field of display processing and displaying a large amount of information has developed rapidly. Liquid crystal displays or organic electroluminescent devices have been developed to replace the existing cathode ray tube (CRT).

Among liquid crystal display devices, an active matrix liquid crystal display device including an array substrate equipped with a thin film transistor, which is a switching element capable of adjusting the voltage on and off for each pixel, realizes resolution and video. It is attracting the most attention because of its ability.

In addition, the organic light emitting device has high luminance and low operating voltage characteristics, and is a self-luminous type that emits light by itself, so the contrast ratio is large, it is possible to implement an ultra-thin display, and the response time is several microseconds ( ㎲) is easy to implement a moving image, there is no limit on the viewing angle, it is stable even at low temperatures, and it is driven with a low voltage of 5 to 15V DC, so that it is easy to manufacture and design a driving circuit, and thus, it has recently attracted attention as a flat panel display device.

In such a liquid crystal display device and an organic light emitting device, an array substrate having a thin film transistor essentially serving as a switching device is constructed in order to remove each pixel region on/off in common.

Meanwhile, the thin film transistor generally includes a gate electrode, a semiconductor layer, and source and drain electrodes, and the semiconductor layer mainly uses amorphous silicon.

The semiconductor layer using such amorphous silicon generally forms a double-layer structure of an active region of pure amorphous silicon and an ohmic contact layer made of impurity amorphous silicon, spaced apart from each other above the active region. As a result of the formation of the thin film transistor, the central portion of the active region, which influences the characteristics of the thin film transistor, is also etched, resulting in a problem of deteriorating the characteristics.

Furthermore, the carrier mobility characteristics that influence the device characteristics are about 0.1 to 1.0 cm 2 /V·s, so it is not a problem to use as a switching device, but it is unreasonable to use it as a driving device.

Accordingly, an array substrate using polysilicon, which has a carrier mobility of 100 to 200 times faster than that of amorphous silicon, is provided as a semiconductor layer and a thin-film transistor implemented as a semiconductor layer, has been proposed.

However, in an array substrate including a thin film transistor having a semiconductor layer made of polysilicon, the thin film transistor having a semiconductor layer made of polysilicon has an off current value (drain flowing during the off operation of the thin film transistor). The increase in current) is a problem.

That is, a thin film transistor having a semiconductor layer of polysilicon has a higher value for both on and off currents than a thin film transistor made of amorphous silicon as a semiconductor layer. This is because the leakage current increases at the interface between the source-drain doped region and the undoped region of the active region (channel) due to its high mobility.

Therefore, when the thin film transistor including the polysilicon semiconductor layer in the array substrate serves as a switching thin film transistor, it is important to sufficiently lower the off current value as a characteristic required for the thin film transistor operating as a switching element.

In order to solve this problem, that is, the leakage current increases inside the semiconductor layer of polysilicon, the most commonly used method is to remove impurities between the heavily doped source and drain regions and the undoped active region corresponding to the lower portion of the gate electrode. By doping at a low concentration, a lightly doped drain (LDD) is formed.

1A to 1B are cross-sectional views of manufacturing steps showing steps of forming source and drain regions and LDD regions in the polysilicon semiconductor layer in a conventional array substrate including a polysilicon semiconductor layer.

As shown in FIG. 1A, a polysilicon layer is formed by forming an amorphous silicon material layer (not shown) on the substrate 10 and performing a crystallization process thereon.

Thereafter, the polysilicon layer (not shown) is patterned to form a polysilicon semiconductor layer 15 in the form of an island.

Next, a gate insulating layer 18 is formed over the semiconductor layer 15 of polysilicon, and further, a gate electrode 20 is formed over the gate insulating layer 18 corresponding to the central portion of the semiconductor layer 15 of polysilicon. do.

Next, by doping the substrate 10 with the gate electrode 20 formed thereon at a first concentration (low concentration), the portion of the polysilicon semiconductor layer 15 exposed to the outside of the gate electrode 20 is removed. Both are made to be the LDD regions 15b and 15c.

Next, as shown in FIG. 1B, a photoresist pattern having a width greater than the width of the gate electrode 20 in a form that completely covers the upper surface and both sides of the gate electrode 20 over the gate electrode 20 ( 92).

Thereafter, the substrate 10 in which the photoresist pattern 92 is formed is doped with an impurity at a second concentration (high concentration) greater than the first concentration to correspond to the portion exposed to the outside of the photoresist pattern 92 The LDD regions (15b and 15c in FIG. 1A) to form the source and drain regions 15d and 15e.

Thereafter, the photoresist pattern 92 located on the gate electrode 20 is removed by performing a strip to expose the gate electrode 20.

Through this process, the area corresponding to the gate electrode 20 of the polysilicon semiconductor layer 15 forms an active area 15a of pure polysilicon, and the polysilicon exposed to the outside of the gate electrode 20 A region doped with only a first concentration of impurities among the semiconductor layers 15, that is, the active region 15a and a predetermined width adjacent to both sides thereof form the LDD regions 15b and 15c, and each of the LDD regions 15b , 15c) A region doped with the impurities of the first and second concentration twice to the outside forms the source and drain regions 15d and 15e doped with a high concentration of impurities.

As described above, a relatively low concentration of impurity doping is performed on some of the polysilicon semiconductor layers 15 exposed to the outside of the gate electrode 20 to form the LDD regions 15b and 15c. The thin film transistor Tr including the semiconductor layer 15 of may reduce off-current characteristics.

However, the LDD regions 15b and 15c doped with a low concentration (first concentration) impurity in the polysilicon semiconductor layer 15 by the above-described method have higher resistance than the source and drain regions 15d and 15e. The region is formed, and thus, the mobility characteristics of the carrier are also reduced.

The present invention has been proposed in order to solve the above-described problem, and an object thereof is to provide an array substrate capable of lowering an off-current value without deteriorating the mobility characteristics of carriers in a polysilicon semiconductor layer.

The array substrate according to an exemplary embodiment of the present invention includes first and second GOLDD regions formed in each pixel region on a substrate in which a plurality of pixel regions are defined, and doped with impurities at a first concentration on both sides of the active region and the active region. A polysilicon semiconductor layer having source and drain regions doped with impurities at a second concentration greater than the first concentration outside the first and second GOLDD regions; A gate insulating film formed over the semiconductor layer of polysilicon; A gate electrode formed over the gate insulating layer and overlapping the active region and the first and second GOLDD regions; An interlayer insulating layer having a semiconductor layer contact hole exposing the source and drain regions over the gate electrode, respectively; And source and drain electrodes formed on the interlayer insulating layer to be in contact with the source region and the drain region, respectively, and spaced apart from each other through the semiconductor layer contact hole.

In this case, each of the first and second GOLDD regions has a width of 0.5 to 2 μm.

In addition, a first LDD region having a third concentration smaller than the second concentration is provided between the first GOLDD region and the source region, and a second LDD region having the third concentration is provided between the second GOLDD region and the drain region. In this case, widths of the first GOLDD area and the first LDD area, and the widths of the second GOLDD area and the second LDD area are each 0.5 to 2 μm, and the first And widths of each of the second LDD regions are equal to or smaller than the widths of the first and second GOLDD regions.

In addition, the doping of the first and third concentrations ^{is characterized in that the impurities are doped with a dose of 1*10 12} to 9*10 ¹³ , respectively, and the doping of the second concentration is characterized in that the impurities are 1*10 ¹⁷ It is characterized by doping with a dose of 9*10 ^18.

In addition, the first and second GOLDD regions and the first and second LDD regions are doped with the same impurities and have the same concentration, or the first and second GOLDD regions and the first and second LDD regions are the same. Or doped with different impurities, and the first concentration and the second concentration are different from each other.

Meanwhile, a protective layer having a drain contact hole exposing the drain electrode on the thin film transistor; The protective layer further includes a pixel electrode in contact with the drain electrode through the drain contact hole for each pixel region.

In the manufacturing method of an array substrate according to an embodiment of the present invention, an active region in each pixel region on a substrate in which a plurality of pixel regions are defined, and first and second GOLDD doped with impurities at a first concentration at both sides of the active region. A semiconductor layer of polysilicon having a source and drain regions doped with impurities at a second concentration greater than the first concentration outside the first and second GOLDD regions, and a gate insulating layer over the semiconductor layer of the polysilicon; And forming a gate electrode over the gate insulating layer and overlapping the active region and the first and second GOLDD regions; Forming an interlayer insulating film having a semiconductor layer contact hole over the gate electrode to expose the source and drain regions, respectively; And forming source and drain electrodes on the interlayer insulating layer and spaced apart from each other while in contact with the source region and the drain region, respectively, through the semiconductor layer contact hole.

At this time, in each pixel region on the substrate in which a plurality of pixel regions are defined, the active region and the first and second GOLDD regions doped with impurities at a first concentration at both sides of the active region, and the first and second GOLDD regions outside the active region. A semiconductor layer of polysilicon having source and drain regions doped with impurities at a second concentration greater than a first concentration, a gate insulating layer over the semiconductor layer of polysilicon, and the active region and the first and second layers over the gate insulating layer. The forming of the gate electrode overlapping the second GOLDD region may include forming an island-shaped polysilicon semiconductor layer in each pixel region on the substrate; Forming a gate insulating film over the semiconductor layer; Forming a photoresist pattern having a first width with respect to the central portion of the semiconductor layer of the polysilicon over the gate insulating layer; Forming a low-doped region by doping an impurity of the first concentration on the semiconductor layer of the polysilicon exposed outside the first photoresist pattern, and simultaneously forming an active region in which doping is not performed; Removing the first photoresist pattern; Forming a gate electrode and a second photoresist pattern having a second width greater than the first width in a sequentially stacked form on the gate insulating layer; The second photoresist pattern is used as a doping blocking mask to form the source and drain regions by doping the second concentration of impurities on the low-doped region exposed outside the second photoresist pattern, while simultaneously forming the source and drain regions, and the gate electrode and the gate electrode. And forming the first and second GOLDD regions doped with the impurities of the first concentration for a predetermined overlapping width.

In addition, a first LDD region having a third concentration smaller than the second concentration is provided between the first GOLDD region and the source region, and a second LDD region having the third concentration is provided between the second GOLDD region and the drain region. It is characterized in that the area is further provided.

In addition, in each pixel region on a substrate in which a plurality of pixel regions are defined, the active region and the first and second GOLDD regions doped with impurities at a first concentration at both sides of the active region, and the first and second GOLDD regions outside the first and second GOLDD regions. A first LDD region having a third concentration smaller than the second concentration is provided between the source and drain regions doped with impurities at a second concentration greater than 1 concentration, and the first GOLDD region and the source region, and the second GOLDD Between the region and the drain region, a semiconductor layer of polysilicon further provided with a second LDD region of the third concentration, a gate insulating layer over the semiconductor layer of polysilicon, and the active region and the first and over the gate insulating layer The forming of the gate electrode overlapping the second GOLDD region may include forming an island-shaped polysilicon semiconductor layer in each pixel region on the substrate; Forming a gate insulating film over the semiconductor layer; Forming a photoresist pattern having a first width with respect to the central portion of the semiconductor layer of the polysilicon over the gate insulating layer; Forming a low-doped region by doping an impurity of the first concentration on the semiconductor layer of the polysilicon exposed outside the first photoresist pattern, and simultaneously forming an active region in which doping is not performed; Removing the first photoresist pattern; Forming a gate electrode having a second width greater than the first width and a second photoresist pattern having a third width greater than the second width in a form sequentially stacked on the gate insulating layer; Using the second photoresist pattern as a doping blocking mask, the source and drain regions are formed by doping an impurity of the second concentration on the low doped region exposed outside the second photoresist pattern, and the gate electrode and The first and second GOLDD regions doped with impurities of the first concentration for a predetermined overlapping width are formed, and at the same time, the second concentration for portions overlapping the second photoresist pattern outside the gate electrode. Forming the first and second LDD regions doped with impurities of And removing the second photoresist pattern.

At this time, the first and second LDD regions are doped with the third concentration of impurities on the portion of the semiconductor layer of the polysilicon exposed outside the gate electrode using the gate electrode as a doping blocking mask. And achieving this doped state.

In addition, forming a protective layer having a drain contact hole exposing the drain electrode on the thin film transistor; And forming a pixel electrode on the passivation layer for each pixel region to contact the drain electrode through the drain contact hole.

In the array substrate according to an embodiment of the present invention, the first and second GOLDD regions in which the semiconductor layer of polysilicon is doped with a low concentration of impurities on both sides of the active region and the gate electrode, and the first and second GOLDD regions Since the source and drain regions are doped with high-concentration impurities on both sides, predetermined channels are provided in the first and second GOLDD regions overlapping the gate electrode to facilitate the movement of carriers.

Therefore, since the first and second GOLDD regions doped with low concentration impurities are provided, the mobility characteristics of the thin film transistor itself are not degraded, and at the same time, the first and second GOLDD regions have high resistance characteristics due to the influence of the gate electrode. Since it can be reduced, there is an effect of lowering the off-current value of the thin film transistor.

1A to 1B are cross-sectional views of manufacturing steps showing a step of forming source and drain regions and LDD regions in the polysilicon semiconductor layer in a conventional array substrate including a polysilicon semiconductor layer.
2 is a cross-sectional view of a portion in which a thin film transistor is formed in one pixel region in an array substrate including a thin film transistor including a polysilicon semiconductor layer according to an exemplary embodiment of the present invention.
3 is a cross-sectional view of a portion in which a thin film transistor is formed in one pixel region in an array substrate including a thin film transistor including a semiconductor layer of polysilicon according to a modified example of the embodiment of the present invention.
4A to 4M are cross-sectional views of manufacturing steps of an array substrate including a thin film transistor having a semiconductor layer of polysilicon according to an embodiment of the present invention.
5A to 5C are cross-sectional views of manufacturing steps of an array substrate including a thin film transistor having a semiconductor layer of polysilicon according to a modified example of the embodiment of the present invention.

Hereinafter, an array substrate including a semiconductor layer of polysilicon and a method of manufacturing the same according to an embodiment of the present invention capable of lowering an off current value without deteriorating carrier mobility characteristics will be described with reference to the drawings.

2 is a cross-sectional view of a portion in which a thin film transistor is formed in one pixel region in an array substrate including a thin film transistor including a polysilicon semiconductor layer according to an exemplary embodiment of the present invention.

As shown, in the device region TrA in which the thin film transistor is formed in each pixel region P on the substrate 110, a semiconductor layer 115 made of polysilicon and the substrate 110 are formed above the semiconductor layer 115. ) A gate insulating layer 118 is formed on the entire surface, and a gate electrode 120 is formed on the gate insulating layer 118 to correspond to a central portion of the upper semiconductor layer 115.

In addition, a semiconductor layer exposing the heavily doped source and drain regions 115d and 115e of the semiconductor layers 115 exposed to the outside of the gate electrode 120 on the entire surface of the substrate 110 over the gate electrode 120, respectively. An interlayer insulating layer 123 having a contact hole 125 is formed.

In addition, source and drain electrodes 133 and 136 are formed on the interlayer insulating layer 123 through the semiconductor layer contact hole 125 and in contact with the source region 115d and the drain region 115e, respectively, and spaced apart from each other. In addition, a protective layer 150 having a drain contact hole 153 exposing the drain electrode 136 is formed over the source and drain electrodes 133 and 136, and the drain The pixel electrode 160 is formed in contact with the drain electrode 136 through the contact hole 153.

The most characteristic of the array substrate 110 according to the embodiment of the present invention having such a configuration is the structure of the semiconductor layer 115 made of polysilicon (hereinafter referred to as a semiconductor layer of polysilicon).

In the polysilicon semiconductor layer 115, an active region 115a made of pure undoped polysilicon is provided corresponding to the gate electrode 120, and the portion overlapping the gate electrode 120 is provided with the The first and second GOLDD (gate overlapped lightly) characterized in that a low concentration impurity is doped with respect to each predetermined width of each side of the active region 115a to serve as an LDD region and overlap with the gate electrode 120. Dopped drain) regions 115b and 155c are provided.

At this time, it was found that the width of each of the first and second GOLDD regions 115b and 155c is 0.5 to 2 μm, which is preferable for reducing leakage current and preventing degradation of mobility characteristics.

Meanwhile, referring to FIG. 3 (a cross-sectional view of a portion in which a thin film transistor is formed in one pixel region in an array substrate including a thin film transistor having a semiconductor layer of polysilicon according to a modified example of the present invention), The polysilicon semiconductor layer 115 includes source and drain regions 115d and 115e doped with high concentration impurities outside each of the first and second GOLDD regions 115b and 155c, and the source A first LDD region 115f is further provided between the region 115d and the first GOLDD region 115b, and a second LDD region 115g is further provided between the second GOLDD region 115c and the drain region 115e. May be.

In this case, the first and second LDD regions 115f and 115g have a width of less than 1/2 compared to the LDD regions provided in the conventional array substrate.

The total width of the first LDD region 115f and the first GOLDD region 115b adjacent to each other (or (and) the second LDD region 115g and the second GOLDD region 115c) is about 0.5 to 2 μm It was found experimentally that it is most preferable to be, and at this time, it was found that the width of the first LDD region 115f is preferably equal to or smaller than the width of the first GOLDD region 115b. Could.

Meanwhile, the first and second LDD regions 115f and 115g may be doped with the same impurities at the same concentration as the first and second GOLDD regions 115b and 155c, or the first and second GOLDD regions It is formed of the same or different impurities as 115b and 155c, and further, its concentration may be different from that of the first and second GOLDD regions 115b and 155c.

This is due to the manufacturing method and will be described in detail later through the manufacturing method.

Meanwhile, referring to FIG. 2, unlike the conventional array substrate (10 of FIG. 1B), the semiconductor layer 115 of the polysilicon is doped with impurities of a lower concentration than the source and drain regions 115d and 115e. When the GOLDD regions 115b and 115c are formed by being formed so as to overlap the gate electrode 120, the GOLDD regions 115b and 115c have channels formed therein under the influence of the gate electrode 120. As the mobility characteristics increase in size compared to the general LDD region, the mobility characteristics in the semiconductor layer 115 of the polysilicon are improved in the semiconductor layer of polysilicon provided with the conventional LDD region (15b and 15d in Fig. 1b) (Fig. 1b). 15) Contrast is improved.

Therefore, in the case of the thin film transistor Tr including the polysilicon semiconductor layer 115 provided on the array substrate 110 according to the embodiment of the present invention, the mobility characteristics include the semiconductor layer provided with the LDD region. It is superior to that of a thin film transistor, and has a similar level to that of a thin film transistor including a semiconductor layer of polysilicon consisting only of an active region and a source and drain region doped with high concentrations of impurities without an LDD region.

Furthermore, in terms of reducing the off-current (Ioff), it can be seen that it is significantly improved compared to a thin film transistor including a polysilicon semiconductor layer without an LDD region.

Table 1 is a table showing the results of measuring the mobility characteristics and off-current characteristics of a thin film transistor in a conventional array substrate and an array substrate according to an embodiment of the present invention.

Ref1 denotes a thin film transistor having a polysilicon semiconductor layer without an LDD region, Ref2 denotes a thin film transistor (with a general LDD region) of a conventional array substrate, and GOLDD denotes the array substrate according to an embodiment of the present invention. It represents a thin film transistor, and each value represents an average value of a number of measured results.

At this time, Ref2 and the impurities implanted into the LDD region and the GOLDD region in the present invention are of the same type, and are doped with the same ^{dose of 6.0*10 13} , and the LDD region and the GOLDD region use thin film transistors having the same width. It was measured using.

Mobility (mobility, unit ㎠/V·s) Off current (I _off, unit A) Ref 1 134.4 5.47*10 ^-11 Ref 2 83.6 4.68*10 ^-12 GOLDD 142.8 1.59*10 ^-11

Referring to Table 1, in terms of mobility characteristics, a thin film transistor including a semiconductor layer provided with a GOLDD region provided on an array substrate according to an embodiment of the present invention is 142.8 cm2/V·s, which is 134.4 cm2. It can be seen that the level is similar to that of a thin film transistor (Ref 1) with a semiconductor layer without an LDD region having a size of /V·s, and furthermore, a conventional LDD region having a size of 83.6 cm2/V·s is provided. It can be seen that it is improved by about 30% compared to the thin film transistor including the semiconductor layer.

On the other hand, looking at the off-current (Ioff) characteristics, the thin film transistor GOLDD provided on the array substrate according to the embodiment of the present invention is 1.59 * 10 ^-11 A, although a thin film including a semiconductor layer having an LDD region It can be seen that it is larger than the transistor (Ref 2, 4.68 * 10 ^-12 A), but has a smaller value compared to the thin film transistor (Ref 1, 5.47 * 10 ^{-11 A) having a semiconductor layer without an LDD region.}

Accordingly, the off-current characteristics are also reduced compared to the thin film transistor Ref 2 provided with the LDD region, but improved compared to the thin film transistor Ref 1 without the LDD region.

Next, a method of manufacturing an array substrate including a thin film transistor including a polysilicon semiconductor layer according to an embodiment of the present invention having the above-described structure and a modified example thereof will be described.

4A to 4M are cross-sectional views of manufacturing steps of an array substrate including a thin film transistor including a polysilicon semiconductor layer according to an exemplary embodiment of the present invention. In this case, for convenience of description, a portion in which the thin film transistor Tr is formed in each pixel region P is defined as a device region TrA.

First, as shown in FIG. 4A, an amorphous silicon layer (not shown) is formed by depositing amorphous silicon on the entire surface of a transparent insulating substrate 110, for example, a glass material or a plastic material having a flexible characteristic.

Thereafter, the polysilicon layer 112 is formed by performing a crystallization process such as heat treatment or irradiation of a laser beam on the amorphous silicon layer (not shown).

Next, as shown in FIG. 4B, the polysilicon layer (112 in FIG. 4A) is coated with a photoresist to form a photoresist layer (not shown), exposure using an exposure mask (not shown), and exposed photos. Formation of a photoresist pattern (not shown) through development of a resist layer (not shown), etching of the polysilicon layer (112 in FIG. 4A) using the photoresist pattern (not shown), and the photoresist pattern (not shown) A mask process including a plurality of unit processes such as a strip of) is performed and patterned to form an island-shaped polysilicon semiconductor layer 115 in the device region TrA in each pixel region P.

Next, as shown in Fig. 4c, by depositing an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) on the entire surface of the substrate 110 over the polysilicon semiconductor layer 115 An insulating film 118 is formed.

Next, as shown in FIG. 4D, a photoresist is applied over the gate insulating layer 118 to form a first photoresist layer (not shown) on the entire surface of the substrate 110, and an exposure mask (not shown) is applied thereto. A first photoresist pattern 191 having a first width is formed in each of the device regions TrA by performing exposure and development processes using TrA, corresponding to the central portion of the semiconductor layer 115 of each polysilicon.

Thereafter, by performing low-concentration doping of impurities using the first photoresist pattern 191 as a doping blocking mask, a portion of the polysilicon semiconductor layer 115 exposed to the outside of the first photoresist pattern 191 is In the meantime, a low concentration of impurities is injected.

In this way, the portion of the polysilicon semiconductor layer 115 into which the low concentration impurity is implanted forms a low concentration region 116 in the current state, and a portion corresponding to the first photoresist pattern 191 between the low concentration regions 116 is The doping of impurities is not performed, thereby forming the active region 115a.

In this case, the low-concentration doping is preferably doped with an impurity at ^{a dose of 1*10 12} to 9*10 ¹³ , and the high-concentration doping carried out later includes impurities of 1*10 ¹⁷ to 9*10 ¹⁸ . It is preferred to be doped in a dose amount.

In the case of n-type, the impurity may be any one of antimony (Sb), arsenic (As), and phosphorus (P), which are Group 5 elements, and in the case of the p-type, boron (B) and gallium (Ga), which are Group 3 elements. ), indium (In).

Next, as shown in FIG. 4E, the first photoresist pattern on the gate insulating layer 118 ( 191 of FIG. 4D is removed by performing a strip.

Next, as shown in FIG. 4F, a metal material having a low resistance characteristic above the gate insulating layer 118 in a state in which the first photoresist pattern (191 in FIG. 4D) is removed, for example, aluminum (Al), aluminum By depositing one of an alloy (AlNd), molybdenum (Mo), molybdenum alloy (MoTi), copper (Cu), or a copper alloy, or depositing two or more in succession, the first metal layer 119 having a single layer or multilayer structure To form.

In the drawings, an example in which the first metal layer 119 is formed so as to have a single-layer structure will be described as an example in which the first metal layer 119 is formed as a single layer.

Next, as shown in FIG. 4G, a photoresist is applied on the entire surface over the first metal layer (119 in FIG. 4F) to form a second photoresist layer (not shown), and the second photoresist layer (not shown) ) After placing an exposure mask (not shown) above, exposure is performed on the second photoresist layer (not shown) through the exposure mask (not shown), and the exposed photoresist layer (not shown) is By developing, a second photoresist pattern 192 is formed on the first metal layer (119 in FIG. 4F) corresponding to the portion where the gate electrode 120 is to be formed and the portion where the gate wiring (not shown) is to be formed.

Thereafter, a gate wiring (not shown) extending in one direction over the gate insulating layer 118 is formed by etching and removing the first metal layer (119 in FIG. 4F) exposed to the outside of the second photoresist pattern 192 At the same time, a gate electrode 120 having a second width greater than the first width is formed in each device region TrA, corresponding to the central portion of the polysilicon semiconductor layer 115.

The gate electrode 120 formed as described above corresponds to the active region 115a of the polysilicon semiconductor layer 115 and the low-concentration region 116 located on both sides thereof and completely covers it. to be.

Next, as shown in FIG. 4H, a low-concentration region exposed to the outside of the semiconductor layer 115 using the gate electrode 120 and the second photoresist pattern 192 positioned thereon as a doping blocking mask (Fig. The high-concentration impurity is doped on the 4g of 116 to form the source region 115d and the drain region 115e into which the high-concentration impurities are implanted.

Accordingly, the polysilicon semiconductor layer 115 overlaps the gate electrode 120 and the active region 115a is not doped with impurities at all, and the low-concentration impurities are respectively on both sides of the polysilicon semiconductor layer 115. These doped first and second GOLDD regions 115b and 155c are formed, and regions located outside the gate electrode 120 include the source region 115d and the drain region 115e doped with high concentration impurities. Will be achieved.

At this time, by appropriately adjusting the first width of the first photoresist pattern (191 in FIG. 4D) and the second width of the gate electrode 120, each of the first and second GOLDD regions 115b and 115c is 0.5 It is characterized in that it achieves a width of 2 μm.

On the other hand, in the case of the manufacturing method of the array substrate 110 including the thin film transistor (Tr) having the semiconductor layer 115 of polysilicon according to the embodiment of the present invention, the semiconductor layer 115 of polysilicon is active A method of forming the region 115a, the first and second GOLDD regions 115b and 155c, and the source and drain regions 115d and 115e is provided, but the first and second GOLDD regions 115b and 155c are A method of forming a semiconductor layer of polysilicon may be variously modified.

In the case of the array substrate (110 in FIG. 3) according to a modified example of the embodiment of the present invention, the semiconductor layer 115 of polysilicon includes a first LDD region 115f between the first GOLDD region 115b and the source region 115d. ) Is provided, and the second LDD region 115g is further provided between the second GOLDD region 115c and the drain region 115e. A method of manufacturing an array substrate according to a modified example of the example will be described.

5A to 5C are cross-sectional views of manufacturing steps of an array substrate including a thin film transistor including a polysilicon semiconductor layer according to a modified example of the embodiment of the present invention. In this case, in the method of manufacturing an array substrate according to the modification of the above embodiment, a semiconductor layer 115 of polysilicon, a gate insulating layer 118, and a first photoresist pattern (not shown) having a first width are formed, and a low concentration Up to the step of performing doping, since the method of manufacturing the array substrate according to the above-described embodiment (see FIGS. 4A to 4F) proceeds in the same manner, a description thereof will be omitted.

As shown in FIG. 5A, a second photoresist pattern having a first metal layer (not shown) formed over the gate insulating layer 118 and having a second width greater than the first width over the first metal layer (not shown) Form 192.

Thereafter, the first metal layer (not shown) exposed to the outside of the second photoresist pattern 192 is etched and removed to form a gate wiring (not shown) extending in one direction, and at the same time, each device region ( A gate electrode 120 is formed on TrA).

In this case, as one of the most characteristic features of the manufacturing method according to the modified example of the embodiment, over-etching is performed when the first metal layer (not shown) is etched to form under the second photoresist pattern 192. The gate electrode 120 is formed to have a third width that is larger than a first width of the first photoresist pattern (not shown) and smaller than the second width.

Accordingly, the gate electrode 120 is characterized in that it forms an under cut shape under the second photoresist 192 by over-etching the first metal layer (not shown).

Next, as shown in FIG. 5B, impurities are applied to the low-concentration region (116 in FIG. 5A) exposed outside the second photoresist pattern 192 by using the second photoresist pattern 192 as a doping blocking mask. The high concentration doping is performed to form the source region 115d and the drain region 115e into which high concentration impurities are implanted.

The semiconductor layer 115 of polysilicon formed by the method of manufacturing an array substrate according to the modified example of the present invention comprises an active region 115a overlapping the gate electrode 120 and the first and second sides thereof. 2 GOLDD regions 115b and 155c are provided, and are located outside the gate electrode 120 without overlapping, and a low concentration of impurities outside the first and second GOLDD regions 115b and 155c, respectively. The doped first and second LDD regions 115f and 115g are provided, and source and drain regions 115d and 115e doped with a high concentration of impurities outside the first and second LDD regions 115f and 115g are It will achieve the provided configuration.

In this case, the first and second GOLDD regions 115b and 155c and the first and second LDD regions 115f and 115g are characterized in that they are implanted with substantially the same impurities and the same amount of increase.

In the method of manufacturing an array substrate according to a modification of the embodiment of the present invention, the first width of the first photoresist pattern (not shown), the second width of the second photoresist pattern 192, and the gate electrode ( By appropriately adjusting the third width of 120), the combined width of the first GOLDD area 115b and the first LDD area 115f and the combined width of the second GOLDD area 115c and the second LDD area 115g It is characterized by having a size of about 0.5 to 2 μm, respectively.

Meanwhile, in order to make a difference in impurity or (and) a difference in the implanted concentration between the first and second LDD regions 115f and 115g and the first and second GOLDD regions 115b and 155c, As a result, the process shown in FIG. 5C may be further performed.

That is, as shown in FIG. 5C, the second photoresist pattern (192 in FIG. 5B) having a second width positioned above the gate electrode 120 having the third width is subjected to a strip. By removing it, the gate electrode 120 is exposed.

Thereafter, low concentrations of the first and second LDD regions 115f and 115g and the source and drain regions 115d and 115e exposed to the outside of the gate electrode 120 using the gate electrode 120 as a doping blocking mask Doping of impurities is carried out.

In this case, the impurities used in this step may be the same or different types of impurities as the impurities used during the doping of the low concentration impurities previously performed to form the low concentration region.

In this way, the doping amount of impurities in the first and second LDD regions 115f and 115g exposed to the outside of the gate electrode 120 and the first and second GOLDD regions 115b and 115c are performed by performing one more doping of the impurity at a low concentration. The impurity doping amount of can be varied, and further, the type of impurity doped with a low concentration can be varied.

Even if the doping of impurities with a low concentration is performed twice, the source and drain regions 115d and 115e doped with a high concentration with a dose that is tens of thousands of times greater than the dose thereof are not affected and are still a source doped with a high concentration of impurities. And drain regions 115d and 115e.

In the case of performing two low-concentration doping, the second photoresist pattern (192 in FIG. 5B) formed to form the gate electrode 120 is used, so that an additional mask process is not required.

Next, as shown in FIG. 4I, by removing the second photoresist pattern (192 in FIG. 4H) remaining on the gate electrode 120 through a strip, the gate electrode 120 and the gate wiring ( Not shown).

_{Next, as shown in Figure 4j, by depositing an inorganic insulating material such as silicon oxide (SiO 2} ) or silicon nitride (SiNx) over the gate wiring (not shown) and the gate electrode 120 An insulating film 123 is formed.

Thereafter, the interlayer insulating layer 123 is patterned by performing a mask process to form a semiconductor layer contact hole 125 exposing the source and drain regions 115d and 115e of the polysilicon semiconductor layers, respectively.

Next, as shown in FIG. 4K, a low-resistance metal material such as aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo ), molybdenum alloy (MoTi), copper (Cu), one or two or more selected from a copper alloy is deposited to form a second metal layer (not shown) having a single layer or multilayer structure.

Thereafter, the second metal layer (not shown) is patterned by performing a mask process, so that a data line (not shown) crossing the gate line (not shown) on the interlayer insulating layer 123 to define the pixel region P is formed. And at the same time, in the device region TrA, a source electrode 133 and the source electrode 133 contacting the source region 115d through the one semiconductor layer contact hole 125a over the interlayer insulating film 123, and the source electrode ( A drain electrode 136 spaced apart from 133 and in contact with the drain region 115e through the another semiconductor layer contact hole 125 is formed.

At this time, by proceeding to the above-described part, a thin film transistor having a semiconductor layer 115 of polysilicon including the first and second GOLDD regions 115b and 115c in the array substrate 110 according to the embodiment of the present invention ( Tr) is completed.

The thin film transistor Tr includes a polysilicon semiconductor layer 115, a gate insulating film, a gate electrode 120, and a semiconductor layer contact hole 125 in the device region TrA on the substrate 110. The interlayer insulating layer 123 and the source and drain electrodes 133 and 136 which are in contact with each of the source and drain regions 115d and 115e through the semiconductor layer contact hole 125 and are spaced apart from each other are formed in a stacked configuration.

Next, as shown in FIG. 4L, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is deposited on the entire surface over the source and drain electrodes 133 and 136, or an organic insulating material example For example, the protective layer 150 is formed by applying photo acryl.

Thereafter, the protective layer 150 is patterned to form a drain contact hole 153 exposing the drain electrode 136.

Next, as shown in FIG. 4M, a transparent conductive material, for example, indium-tin-oxide (ITO) or indium-zinc-oxide (IZO), is deposited on the protective layer 150 having the drain contact hole 153. The present invention is formed by depositing on the entire surface to form a transparent conductive material layer, and patterning the pixel electrode 160 in contact with the drain electrode 136 through the drain contact hole 153 for each pixel region (P). Complete the array substrate 110 according to the embodiment of.

The present invention is not limited to the above-described embodiments and modifications, and various changes and modifications are possible without departing from the spirit of the present invention.

110: array substrate
115: semiconductor layer
115a: active area
115b, 115c: GOLDD area
115d, 115e: source and drain regions
118: gate insulating film
120: gate electrode
123: interlayer insulating film
125: semiconductor layer contact hole
133: source electrode
136: drain electrode
150: protective layer
153: drain contact hole
160: pixel electrode
P: pixel area
Tr: thin film transistor
TrA: element area

Claims (18)

delete delete delete delete delete delete delete delete delete a) In each pixel region on a substrate in which a plurality of pixel regions are defined, the active region and the first and second GOLDD regions doped with impurities at a first concentration at both sides of the active region, and the first and second GOLDD regions outside the active region. A semiconductor layer of polysilicon having source and drain regions doped with impurities at a second concentration greater than a first concentration, a gate insulating layer over the semiconductor layer of polysilicon, and the active region and the first and second layers over the gate insulating layer. Forming a gate electrode overlapping the second GOLDD region;
b) forming an interlayer insulating layer having a semiconductor layer contact hole over the gate electrode to expose the source and drain regions, respectively;
c) forming source and drain electrodes on the interlayer insulating layer and spaced apart from each other in contact with the source region and the drain region, respectively, through the semiconductor layer contact hole.
Including,
A first LDD region having a third concentration smaller than the second concentration is provided between the first GOLDD region and the source region, and a second LDD region having the third concentration is provided between the second GOLDD region and the drain region. More equipped,
The first and second LDD regions have a width narrower than that of the first and second GOLDD regions,
In the step a), after forming a low-doped region and an active region through a first photoresist pattern, removing the first photoresist pattern, and the source and drain regions and the source through a second photoresist pattern After forming the first and second GOLDD regions, further comprising the step of removing the second photoresist pattern,
After the second photoresist pattern is removed, the gate electrode is used as a doping blocking mask, and the first and second GOLDD regions and the source and drain regions are each doped with impurities of the first concentration. Way.
delete delete The method of claim 10,
In the step a), forming an island-shaped semiconductor layer of the polysilicon in each of the pixel regions on the substrate;
Forming the gate insulating layer over the semiconductor layer;
Forming the photoresist pattern having a first width with respect to the central portion of the semiconductor layer of the polysilicon over the gate insulating layer;
Forming the low-doped region by doping an impurity of the first concentration on the semiconductor layer of the polysilicon exposed outside the first photoresist pattern, and simultaneously forming the doped active region;
After removing the first photoresist pattern, the gate electrode having a second width greater than the first width in a form sequentially stacked on the gate insulating layer and the second photoresist pattern having a third width greater than the second width Forming a;
Using the second photoresist pattern as a doping blocking mask, the source and drain regions are formed by doping an impurity of the second concentration on the low doped region exposed outside the second photoresist pattern, and the gate electrode and Forming the first and second GOLDD regions doped with the impurities of the first concentration for a predetermined overlapping width;
Forming the first and second LDD regions doped with the impurities of the third concentration, respectively, at a portion overlapping the second photoresist pattern outside the gate electrode
Method of manufacturing an array substrate comprising a.
The method of claim 13,
The first and second LDD regions are doped with impurities of the third concentration by doping the semiconductor layer portion of the polysilicon exposed outside the gate electrode with the impurities of the third concentration using the gate electrode as a doping blocking mask. To achieve the state of being
Method of manufacturing an array substrate comprising a.
The method of claim 10,
Forming a protective layer having a drain contact hole exposing the drain electrode over the source and drain electrodes;
Forming a pixel electrode on the protective layer and in contact with the drain electrode through the drain contact hole for each pixel region
Method of manufacturing an array substrate further comprising a.
delete The method of claim 10,
The method of manufacturing an array substrate in which the gate electrode is not positioned to overlap with the source and drain electrodes.



delete

Images