KR102068960B1 - Method of fabricating array substrate - Google Patents

Abstract

The present invention provides a method of forming a semiconductor device, comprising: forming a first storage electrode comprising a semiconductor layer of polysilicon and a semiconductor material of polysilicon doped with impurities on a substrate on which a pixel region is defined; Forming a gate insulating film over the semiconductor layer of the polysilicon and the first storage electrode; Forming a gate electrode and a second storage electrode corresponding to the first storage electrode corresponding to a central portion of the semiconductor layer of the polysilicon over the gate insulating layer; Doping an impurity into a semiconductor layer of the polysilicon exposed to the outside of the gate electrode to form an ohmic region, and a portion corresponding to the gate electrode to form an active region of pure polysilicon; Forming an interlayer insulating film having a semiconductor layer contact hole exposing the ohmic region on the gate electrode and the first storage electrode, respectively; And forming a source electrode and a drain electrode that are in contact with the ohmic region and spaced apart from each other through the semiconductor layer contact hole on the interlayer insulating layer.

Description

Method of fabricating array substrate

TECHNICAL FIELD The present invention relates to an array substrate, and more particularly, to a method of manufacturing an array substrate having a semiconductor layer of polysilicon.

In recent years, as the society enters the information age, the display field for processing and displaying a large amount of information has been rapidly developed. In recent years, as a flat panel display device having excellent performance of thinning, light weight, and low power consumption, Liquid crystal displays or organic light emitting diodes have been developed to replace existing cathode ray tubes (CRTs).

Among the liquid crystal display devices, an active matrix liquid crystal display device including an array substrate having a thin film transistor, which is a switching element capable of controlling voltage on and off, is realized in each pixel. Excellent ability is attracting the most attention.

In addition, the organic light emitting diode has a high brightness and low operating voltage characteristics, and because it is a self-luminous type that emits light by itself, it has a high contrast ratio, an ultra-thin display, and a response time of several microseconds ( Iii) It is easy to implement a moving image, there is no limit of viewing angle, it is stable even at low temperature, and it is attracting attention as a flat panel display device because it is easy to manufacture and design a driving circuit because it is driven at a low voltage of DC 5 to 15V.

In such a liquid crystal display and an organic light emitting device, an array substrate including a thin film transistor, which essentially serves as a switching element, is configured to remove each pixel area on / off.

On the other hand, the thin film transistor typically includes a gate electrode, a semiconductor layer, a source and a drain electrode as main components, and at this time, the semiconductor layer mainly uses amorphous silicon.

Such a semiconductor layer using amorphous silicon typically forms a double layer structure of an active layer of pure amorphous silicon and an ohmic contact layer formed of impurity amorphous silicon spaced apart from each other on top of the active layer. As the channel is formed and the center portion of the active layer which determines the characteristics of the thin film transistor is also etched, the problem of deterioration of the characteristics is generated.

Further, the carrier mobility characteristic that influences the device characteristics is about 0.1 to 1.0 cm 2 / V · s, which is not a problem for use as a switching device, but is difficult to use as a drive device.

Accordingly, an array substrate having a thin film transistor having polysilicon as a semiconductor layer has been proposed, which has a carrier mobility of about 100 to 200 times higher than that of amorphous silicon.

1 is a cross-sectional view of one pixel region of an array substrate having a semiconductor layer of a conventional polysilicon. For convenience of description, an area where the thin film transistor Tr is formed in each pixel area P is referred to as an element area DA and an area where the storage capacitor StgC is formed as a storage area StgA.

As shown, a buffer layer 10 is provided on the entire surface of the transparent insulating substrate 1.

In addition, a polysilicon semiconductor layer 13 including an active region 13a of pure polysilicon and an ohmic region 13b doped with impurities on both sides thereof is provided in the device region DA on the buffer layer 10. The first storage electrode 15 made of the same material forming the semiconductor layer 13 of polysilicon and doped with impurities is formed in the storage region StgA.

In addition, a gate insulating layer 16 is formed on the entire surface of the polysilicon semiconductor layer 13 and the first storage electrode 15, and the gate insulating layer 16 is disposed in one direction on the boundary of each pixel region P. And a gate wiring (not shown) is formed.

The gate electrode 18 is formed on the gate insulating layer 16 to correspond to the active region 13a in the device region DA, and the second storage electrode 19 is formed in the storage region StgA. ) Is formed.

In this case, the gate insulating layer 16 interposed between the first and second storage electrodes 15 and 19 and the two storage electrodes 15 and 19 forms a first storage capacitor StgC1.

Meanwhile, an interlayer insulating film 23 having a semiconductor layer contact hole 25 exposing the ohmic region 13b on the gate electrode 18 and the second storage electrode 19, respectively, is provided. In the device area DA, a source electrode 33 and a drain electrode 36 are formed in contact with the ohmic region 13b and spaced apart from each other through the semiconductor layer contact hole 25. have.

At this time, the interlayer insulating film 23 having the semiconductor layer 13, the gate insulating film 16, the gate electrode 18, and the semiconductor layer contact hole 25 of the polysilicon sequentially stacked on the device region DA. ) And the source and drain electrodes 33 and 36 spaced apart from each other form a thin film transistor Tr having a top gate structure.

In addition, a passivation layer 40 having the thin film transistor Tr and a drain contact hole 43 exposing the drain electrode 36 upward is provided, and the drain contact hole 43 is disposed on the passivation layer 40. The pixel electrode 50 in contact with the drain electrode 36 is formed.

The array substrate 1 having the conventional polysilicon semiconductor layer having such a configuration requires a total of seven mask processes.

That is, forming the semiconductor layer 13 and the polysilicon pattern (not shown) of polysilicon, and selectively doping the polysilicon pattern (not shown) in the storage area (StgA) to improve the conductivity characteristics Forming a first storage electrode 15, forming a gate electrode 18, forming an interlayer insulating layer 23 having a semiconductor layer contact hole 25, and source and drain electrodes 33 and 36. The semiconductor layer 13 of the conventional polysilicon is formed through a seven mask process of forming a film, forming a protective layer 40 having a drain contact hole 43, and forming a pixel electrode 50. One array substrate 1 is completed.

However, since the mask process includes a total of five unit processes of application of photoresist, exposure using an exposure mask, development of exposed photoresist, etching, and strip, the process is complicated and a large number of chemicals are used. As it increases, the production time increases, resulting in poor productivity per unit time, a high frequency of defects, and an increase in manufacturing cost.

Therefore, the conventional array substrate 1 provided with the thin film transistor Tr having the semiconductor layer 13 of polysilicon is required to reduce the mask process to improve productivity per unit time and reduce manufacturing cost.

In order to solve the above problems, the present invention implements a thin film transistor having a polysilicon semiconductor layer by a total of six processes by omitting one mask process to reduce the manufacturing process through the mask process reduction It is an object of the present invention to provide a method for producing a substrate.

In order to achieve the above object, a method of manufacturing an array substrate according to an embodiment of the present invention, the first storage electrode consisting of a semiconductor layer of polysilicon and a semiconductor material of polysilicon doped with impurities on a substrate on which a pixel region is defined Forming a; Forming a gate insulating film over the semiconductor layer of the polysilicon and the first storage electrode; Forming a gate electrode and a second storage electrode corresponding to the first storage electrode corresponding to a central portion of the semiconductor layer of the polysilicon over the gate insulating layer; Doping an impurity into a semiconductor layer of the polysilicon exposed to the outside of the gate electrode to form an ohmic region, and forming a portion corresponding to the gate electrode to form an active region of pure polysilicon; Forming an interlayer insulating film having a semiconductor layer contact hole exposing the ohmic region on the gate electrode and the first storage electrode, respectively; Forming a source electrode and a drain electrode on the interlayer insulating layer, the source and drain electrodes being in contact with the ohmic region and spaced apart from each other through the semiconductor layer contact hole.

The forming of the first storage electrode made of the semiconductor layer of polysilicon and the semiconductor material of polysilicon doped with impurities may include forming an amorphous silicon layer by depositing amorphous silicon on the substrate; Performing a crystallization process to crystallize the amorphous silicon layer into a polysilicon layer; Forming a first photoresist pattern having a first thickness and a second photoresist pattern having a second thickness thinner than the first thickness over the polysilicon layer; Removing the polysilicon layer exposed to the outside of the first and second photoresist patterns to form a polysilicon pattern spaced apart from the semiconductor layer of the polysilicon; Exposing the entire surface of the polysilicon pattern by first ashing to remove the second photoresist pattern and simultaneously reducing the thickness and width of the first photoresist pattern to expose the edge portion of the semiconductor layer of the polysilicon; ; Applying a photoresist over the exposed polysilicon pattern to form a photoresist layer such that a portion formed on a side of the first photoresist pattern covers an exposed edge of the semiconductor layer of the polysilicon; Performing secondary ashing to expose the polysilicon pattern without exposing the edge portion of the semiconductor layer of the polysilicon; Doping an impurity to the exposed polysilicon pattern to improve conductivity and to form the first storage electrode; Advancing the strip to remove the first photoresist pattern and the photoresist layer remaining on the side thereof.

The photoresist layer is thinner than the second thickness, and the portion formed on the side of the first photoresist pattern has a thickness such that the edge portion of the polysilicon may not be exposed by the second ashing process. It is characterized by.

The forming of the gate electrode may include forming a gate line extending in one direction at a boundary of the pixel region and connected to the gate electrode, and forming the source electrode and the drain electrode may include forming the gate line. Defining a pixel area to intersect the pixel area, the data line connected to the source electrode, and forming a third storage electrode corresponding to the second storage electrode.

Forming a protective layer having a drain contact hole exposing the drain electrode over the source electrode, the drain electrode, and the third storage electrode; Forming a pixel electrode in contact with the drain electrode through the drain contact hole in the pixel area over the passivation layer.

And forming a buffer layer on the entire surface of the substrate before forming the semiconductor layer of the polysilicon and the first storage electrode.

As described above, in the method of manufacturing the array substrate according to the exemplary embodiment of the present invention, the semiconductor layer of pure polysilicon and the first storage electrode doped with impurities are manufactured through a single mask process to form the pixel electrode in total six times. The mask process is performed, and a total of four mask processes are performed to form the thin film transistor and the first and third storage capacitors, which can serve as an array substrate.

Therefore, since one mask process can be reduced compared to a conventional method for manufacturing an array substrate using polysilicon as a semiconductor layer, the process per unit time can be improved by simplifying the process and shortening the process time.

Furthermore, the productivity per unit time is improved, thereby reducing the manufacturing cost of the product.

1 is a cross-sectional view of one pixel region of an array substrate having a conventional polysilicon semiconductor layer.
2A to 2O are cross-sectional views of manufacturing steps of one pixel region of an array substrate including a thin film transistor having a polysilicon semiconductor layer according to an embodiment of the present invention.

 Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

2A to 2O are cross-sectional views illustrating manufacturing steps of one pixel region P of an array substrate including a thin film transistor having a semiconductor layer of polysilicon according to an exemplary embodiment of the present invention. In this case, for convenience of description, an area where the thin film transistor Tr is formed in each pixel area P is defined as an element area DA and an area where a storage capacitor is formed as a storage area StgA.

First, as shown in FIG. 2A, a buffer layer 111 is formed by depositing silicon nitride (SiNx) or silicon oxide (SiO ₂ ), which is an inorganic insulating material, on the transparent insulating substrate 101.

When the amorphous silicon is recrystallized from polysilicon, the buffer layer 111 may be formed of alkali ions, for example, potassium ions (K +) and sodium ions, which are present in the insulating substrate 101 due to heat generated by laser irradiation. (Na +) and the like may be generated to prevent the film properties of the semiconductor layer (120 of FIG. 2O) made of polysilicon from being degraded by such alkali ions.

In this case, the buffer layer 111 may be omitted depending on what material the substrate 101 is made of.

Thereafter, amorphous silicon is deposited on the buffer layer 111 to form an amorphous silicon layer (not shown) on the entire surface.

Next, the pure amorphous silicon layer (not shown) is crystallized to form the pure polysilicon layer 180 by performing a crystallization process to improve mobility characteristics of the amorphous silicon layer (not shown).

In this case, it is preferable that the crystallization process is a crystallization process using solid phase crystallization (SPC) or a laser.

The solid phase crystallization (SPC) process, for example, thermal crystallization (Thermal Crystallization) through heat treatment in an atmosphere of 600 ℃ to 800 ℃ or alternating magnetic field crystallization (Alternating Magnetic in a temperature atmosphere of 600 ℃ to 700 ℃ using an alternating magnetic field crystallization device It is preferable that the field crystallization process, and the crystallization using the laser is preferably crystallization through Excimer Laser Annealing (ELA) or sequential lateral solidification (SLS) using an excimer laser.

Next, as shown in FIG. 2B, a photoresist is applied on the polysilicon layer 180 to form a first photoresist layer 181, and a light transmitting region with respect to the first photoresist layer 181. A diffraction exposure mask 191 or a halftone exposure mask (not shown) having a TA, a blocking area BA, and a transflective area HTA smaller than the transmission area TA and having a larger light transmission than the blocking area BA. Exposure) is performed.

Next, as shown in FIG. 2C, a first photoresist pattern 181a having a first thickness over the first metal layer 186 by developing the exposed first photoresist layer (181 of FIG. 2B), A second photoresist pattern 181b having a second thickness thinner than the first thickness is formed.

The first photoresist pattern 181a may be formed in the device area DA to correspond to a portion where a semiconductor layer (113 in FIG. 2O) of polysilicon is to be formed later, and the second photoresist pattern 181b may be a storage device. In the region StgA, the first storage electrode 115 (see FIG. 2O) is formed to correspond to a portion to be formed later.

Next, as shown in FIG. 2D, the device region DA is disposed on the buffer layer by removing the polysilicon layer (180 of FIG. 2B) exposed to the outside of the first and second photoresist patterns 181a and 181b. The semiconductor layer 113 of pure polysilicon is formed, and the storage pattern 114 of pure polysilicon is formed in the storage region StgA.

Next, as shown in FIG. 2E, the storage pattern 114 is removed from the storage area StgA by first ashing to remove the second photoresist pattern 181b having the second thickness. Expose

At this time, the thickness of the first photoresist pattern 181a is also reduced by the first ashing, but still remains on the semiconductor layer 113 of pure polysilicon.

However, as a result of ashing, not only the thickness of the first photoresist pattern 181a is reduced but also the side surface of the first photoresist pattern 181a is removed together with a predetermined thickness so that the first photoresist pattern 181a is thin. Along with the load, the width is also reduced, thereby forming a predetermined width of the edge portion of the semiconductor layer 113 of pure polysilicon.

When the doping of the impurity in this state is doped along the edge of the semiconductor layer 113 of the pure polysilicon dopant has a conductive characteristic, so that the portion having this conductive characteristic in the active region (113a of FIG. 2o) later This is caused by the defect that the channel is not formed.

Therefore, as one of the most characteristic configurations of the method of manufacturing the array substrate 101 according to the embodiment of the present invention, as shown in FIG. 2F, the first ashing is performed to form the second photoresist pattern ( Simultaneously deleting 181b of FIG. 2E, the first photoresist pattern may be thinly coated on the entire surface over the first photoresist pattern 181a in a state in which the thickness and width of the first photoresist pattern 181a are reduced. A second photoresist layer 182 is formed to cover an edge portion of the semiconductor layer 113 of pure polysilicon exposed to the outside (181a).

The second photoresist layer 182 is thinner than the second thickness and has a thickness of the side surface of the first photoresist pattern 181a reduced by primary ashing (ie, the first photoresist pattern ( A portion formed on the side of the first photoresist pattern 181a completely covering the exposed edge portion of the semiconductor layer 113 of pure polysilicon, having a thickness thicker than the reduced one side width of 181a). Even when the second ashing is performed, an edge portion of the semiconductor layer 113 of pure polysilicon is formed to a thickness that may not be exposed.

Next, as illustrated in FIG. 2G, the second ashing process is performed on the entire surface of the second photoresist layer (182 of FIG. 2F) to remove the second photoresist layer (182 of FIG. 2F), thereby removing the storage pattern 114. ).

On the other hand, ashing has anisotropy, so ashing mainly proceeds in a direction perpendicular to the surface of the substrate 101, and in this case, a second photoresist layer in a direction perpendicular to the surface of the substrate 101 (Fig. The removal rate of 182 of 2f is much faster than the removal rate in the direction parallel to the substrate 101 plane.

Therefore, the second photoresist layer (182 of FIG. 2F) is removed from all portions formed parallel to the surface of the substrate 101, whereas the portion of the second photoresist layer (182 of FIG. Since the vertically formed portion is removed much smaller, the second photoresist layer 182 of FIG. 2F remains on the side surface of the first photoresist pattern 181a after the second ashing process. A photoresist pattern 183 is formed, and the third photoresist pattern 183 covers an edge portion of the semiconductor layer 113 of pure polysilicon exposed to the outside of the first photoresist pattern 181a.

Next, as shown in FIG. 2H, the semiconductor layer of pure polysilicon exposed to the outside of the first photoresist pattern 181a by the third photoresist pattern 183 remaining after the second ashing. A semiconductor pattern made of the polysilicon in the storage region StgA by doping a high concentration of p-type or n-type impurities to the surface of the substrate 101 while the edge portion of the 113 is covered. The p-type or n-type impurity is doped into 114 to form the first storage electrode 115 having improved conductivity.

The doping of the high concentration p-type or n-type impurities is performed on the entire surface of the substrate 101, but the first photoresist pattern 181a and the third photoresist pattern 183 are disposed on the semiconductor layer 113 of the pure polysilicon. Since it is covered, no doping of impurities occurs, so that a pure polysilicon state is still achieved.

Next, as shown in FIG. 2I, the pure polysilicon semiconductor is removed by performing a strip to remove the first photoresist pattern 181a of FIG. 2H and the third photoresist pattern 183 of FIG. 2H. Expose layer 113.

Next, as shown in FIG. 2J, an inorganic insulating material, such as silicon nitride (SiNx) or silicon oxide (SiO ₂ ), is disposed on the entire surface of the pure polysilicon semiconductor layer 113 and the first storage electrode 115. Is deposited to form a gate insulating film 116.

Subsequently, a metal material having low resistance on the gate insulating layer 116, for example, copper (Cu), copper alloy, aluminum (Al), aluminum alloy (AlNd), molybdenum (Mo), and molybdenum (MoTi) The first metal layer (not shown) having a single layer or a double layer or more multilayer structure is formed by depositing one or two or more selected materials.

The gate is formed by patterning the first metal layer through a mask process including a series of unit processes such as application of photoresist, exposure using an exposure mask, development of exposed photoresist, etching and stripping, and the like. A gate line (not shown) extending in one direction is formed on the insulating layer 116 to correspond to the boundary of the pixel region P, and at the same time, the pure polysilicon in the device region DA is formed on the gate insulating layer 116. A gate electrode 118 connected to the gate line (not shown) is formed to correspond to the central portion of the semiconductor layer 113.

In this case, the semiconductor layer 113 of pure polysilicon is exposed to both sides of the gate electrode 118.

At the same time, in the storage area StgA, a second storage electrode 119 is formed on the gate insulating layer 116 to correspond to the first storage electrode 115.

In this case, the first storage electrode 115, the gate insulating layer 116, and the second storage electrode 119 sequentially stacked in the storage region StgA form a first storage capacitor StgC1.

Next, as shown in FIG. 2K, by doping a high concentration of p-type or n-type impurities to the substrate 101 on which the second storage electrode 119, the gate wiring (not shown), and the gate electrode 118 are formed. The p-type or n-type impurity is implanted into the semiconductor layer 113 of the polysilicon exposed to the outside of the gate electrode 118 to improve the conductive properties to form the ohmic region 113b, respectively.

In this case, since the gate electrode 118 serves as a blocking mask for impurity doping, the center portion of the semiconductor layer 113 of polysilicon is not doped with impurities, and thus, the gate electrode 118 remains in a state of pure polysilicon. 113a).

Accordingly, the semiconductor layer 113 of the polysilicon has a state consisting of three regions including an active region 113a in a pure polysilicon state in the center and an ohmic region 113b doped with impurities on both sides thereof. Is achieved.

Next, as shown in FIG. 2L, an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiNx) is disposed on the gate wiring (not shown), the gate electrode 118, and the second storage electrode 119. Deposited to form an interlayer insulating film 123.

Subsequently, a mask process is performed on the interlayer insulating layer 123 and patterned together with the gate insulating layer 116 to expose each of the ohmic regions of both sides of the active region of the semiconductor layer 113. 125).

Next, as shown in FIG. 2M, a low-resistance metal material, for example, copper (Cu), a copper alloy, aluminum (Al), and aluminum, is disposed on the entire surface of the interlayer insulating layer 123 provided with the semiconductor layer contact hole 125. A second metal layer (not shown) is formed by depositing any one or two or more of alloys (AlNd), molybdenum (Mo), and molybdenum (MoTi).

Subsequently, the second metal layer (not shown) is patterned by a mask process so as to cross the gate line (not shown) at the boundary of the pixel area P to define a data line (not shown). Form

At the same time, in the device area DA, source and drain electrodes 133 and 136 are formed through the semiconductor layer contact hole 125 to contact the ohmic region 113b of the semiconductor layer 113 and to be spaced apart from each other. In the storage area StgA, a third storage electrode 137 is formed on the interlayer insulating layer to correspond to the second storage electrode 119.

In this case, the polysilicon semiconductor layer 113, the gate insulating layer 116, the gate electrode 118, the interlayer insulating layer 123, and the source and drain spaced apart from each other are sequentially stacked on the device region DA. The electrodes 133 and 136 form a thin film transistor Tr, which is a switching element, and the second storage electrode 119, the interlayer insulating layer 123, and the third storage electrode 137 sequentially stacked on the storage region StgA. Is the second storage capacitor StgC2.

In this configuration, the first and second storage capacitors StgC1 and StgC2 provided in the storage region StgA form a structure in which the first and second storage capacitors StgC1 and StgC2 are connected in parallel to each other via the second storage electrode 119 to increase the storage capacitor capacity. You can.

Next, as illustrated in FIG. 2N, silicon nitride (SiNx) or silicon oxide, which is an inorganic insulating material, is formed on the entire surface of the data line (not shown), the source and drain electrodes 133 and 136, and the third storage electrode 137. The protective layer 140 is formed by depositing (SiO ₂ ) or applying photo acryl, which is an organic insulating material.

Subsequently, the protective layer 140 is patterned by a mask process to form a drain contact hole 143 exposing the drain electrode 136 in the device area DA.

Next, as shown in FIG. 2O, indium-tin-oxide (ITO) or indium, which is a transparent conductive material on the entire surface of the protective layer 140 provided with the drain contact hole 143, in the device area DA. Zinc oxide (IZO) is deposited on the entire surface to form a transparent conductive material layer (not shown).

Subsequently, the transparent conductive material layer (not shown) is patterned by performing a mask process to contact the drain electrode 136 through the drain contact hole 143 in each pixel region P. By forming the array substrate 101 according to an embodiment of the present invention is completed.

On the other hand, the manufacturing method of the array substrate having the above-described configuration shows an example of the manufacturing method of the array substrate for the TN mode liquid crystal display device, it can be variously modified.

 For example, when the pixel electrode is formed in a bar shape in each pixel area, and in addition to the bar shape pixel area, a bar shape and an alternating common electrode are further formed. The array substrate is formed.

In this case, in the forming of the gate wiring, the common wiring is further formed in parallel with the gate wiring, and in the forming of the drain contact hole, the common contact hole for exposing the common wiring is further formed, and the pixel electrode is further formed. In the forming, the process of forming the bar-shaped common electrode to contact the common wiring through the common contact hole may be further performed.

Furthermore, in another example, when the array substrate forms an array substrate for a fringe field switching mode liquid crystal display device, an insulating layer is further formed on the pixel electrode after the forming of the pixel electrode, and an entire surface of the display area is formed on the insulating layer. The method may further include forming a common electrode having a plurality of openings having a bar shape corresponding to each pixel region in the form of being connected to each other.

Meanwhile, in the method of manufacturing the array substrate 150 according to the embodiment of the present invention as described above, the semiconductor layer 113 of pure polysilicon and the first storage electrode 115 doped with impurities are subjected to one mask process. In this process, a total of six mask processes are performed to form the pixel electrode 150, and in particular, the thin film transistor Tr and the first and second storage capacitors StgC1 and StgC2, which may serve as the array substrate 101, are processed. A total of four mask processes are required to form.

Therefore, since one mask process can be reduced compared to the conventional method of manufacturing an array substrate (1 of FIG. 1) having a semiconductor layer with a semiconductor layer, the process per unit time is improved by simplifying the process and shortening the process time. .

Furthermore, the productivity per unit time is improved, thereby reducing the manufacturing cost of the product.

The present invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit of the present invention.

101: substrate
111: buffer layer
113: pure polysilicon semiconductor layer
115: first storage electrode
181a: first photoresist pattern
183: third photoresist pattern
DA: device area
P: pixel area
StgA: Storage Area

Claims (6)

a) forming a first storage electrode comprising a semiconductor layer of polysilicon and a semiconductor material of polysilicon doped with impurities on a substrate on which a pixel region is defined;
b) forming a gate insulating film over the semiconductor layer of the polysilicon and the first storage electrode;
c) forming a gate electrode and a second storage electrode corresponding to the first storage electrode corresponding to a central portion of the semiconductor layer of the polysilicon over the gate insulating layer;
d) forming an ohmic region by doping impurities into the semiconductor layer of the polysilicon exposed to the outside of the gate electrode, and forming a portion corresponding to the gate electrode to form an active region of pure polysilicon;
e) forming an interlayer insulating film having a semiconductor layer contact hole exposing the ohmic region on the gate electrode and the first storage electrode, respectively;
f) forming a source electrode and a drain electrode on the interlayer insulating layer, the source and drain electrodes being in contact with the ohmic region and spaced apart from each other through the semiconductor layer contact hole;
Including;
Step a) is
a-1) forming a first photoresist pattern on the polysilicon layer,
a-2) subjecting the first photoresist pattern to primary ashing to expose edge portions of the polysilicon layer;
a-3) forming a photoresist layer over the first photoresist pattern including the exposed sidewalls of the polysilicon layer.
The method of claim 1,
Step a-1) further includes forming a first photoresist pattern having a first thickness and a second photoresist pattern having a second thickness thinner than the first thickness over the polysilicon layer,
Step a-2) removes the second photoresist pattern by performing the first ashing to expose the entire surface of the polysilicon pattern and simultaneously reduce the thickness and width of the first photoresist pattern to reduce the thickness of the semiconductor layer of polysilicon. Further comprising exposing an edge portion of the
In the step a-3, the photoresist layer is coated on the exposed polysilicon pattern so that a portion formed on the side surface of the first photoresist pattern covers an edge portion of the exposed semiconductor layer of the polysilicon. Further comprising forming a,
Before the step a-1), depositing amorphous silicon on the substrate to form an amorphous silicon layer; and performing a crystallization process to crystallize the amorphous silicon layer into the polysilicon layer. prior to step a-2), removing the polysilicon layer exposed to the outside of the first and second photoresist patterns to form a polysilicon pattern spaced apart from the semiconductor layer of the polysilicon,
After the step a-3), the second ashing is performed to expose the polysilicon pattern without exposing the edge portion of the semiconductor layer of the polysilicon, and the doping is performed by doping impurities to the exposed polysilicon pattern. Improving characteristics to form the first storage electrode; and stripping to remove the first photoresist pattern and the photoresist layer remaining on the side thereof.
The method of claim 2,
The photoresist layer is thinner than the second thickness, and the portion formed on the side of the first photoresist pattern has a thickness such that the edge portion of the polysilicon layer may not be exposed by the second ashing process. Method for producing an array substrate, characterized in that.
The method of claim 1,
In the step c), the gate electrode includes a step of forming a gate wiring extending in one direction to the boundary of the pixel region and connected to the gate electrode,
The forming of the source electrode and the drain electrode in step f) may include a data line connected to the source electrode and defining the pixel area crossing the gate line, and corresponding to the second storage electrode. Forming steps
Method of manufacturing an array substrate comprising a.
The method of claim 4, wherein
Forming a protective layer having a drain contact hole exposing the drain electrode over the source electrode and the drain electrode and the third storage electrode;
Forming a pixel electrode on the protective layer in contact with the drain electrode through the drain contact hole in the pixel area
Method of manufacturing an array substrate comprising a.
The method of claim 1,
Before the step a), forming a buffer layer on the entire surface of the substrate.

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