JP3292240B2 - Thin film transistor device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor device and a method of manufacturing the same, and more particularly, to a structure of a thin film transistor device used in an active matrix type liquid crystal display and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, active matrix type liquid crystal displays using thin film transistors (TFTs) using a hydrogenated amorphous silicon film as switching elements for each display pixel have been mass-produced. In particular, with the spread of notebook personal computers, acceptance of liquid crystal displays has rapidly increased, and improvement in productivity has been demanded.

FIG. 9 is a cross-sectional view of an inverted staggered thin film transistor element generally used as a switching element of a pixel of a liquid crystal display at present.

First, a gate electrode metal is formed on a transparent insulating substrate 1 and patterned into a desired shape to form a gate electrode 2. On this, a silicon film and an n ⁺ -type amorphous silicon film are sequentially formed to form a gate insulating film 3 made of a silicon nitride film, an amorphous silicon film 4, and an ohmic contact made of a source / drain region. ^{The +} type amorphous silicon film 5 and the amorphous silicon film 4 are patterned into an island shape. Subsequently, a source / drain electrode metal is formed and patterned into a desired shape to form a source electrode 6 and a drain electrode 7. Finally, the unnecessary n ⁺ -type amorphous silicon film 5 on the channel is removed by etching including a part of the amorphous silicon film 4 in consideration of a margin,
The thin film transistor device shown in FIG. 9 is completed.

[0005]

As described above, in the conventional inverted staggered type thin film transistor element, it is necessary to remove unnecessary n ⁺ type amorphous silicon film on the channel by etching during the manufacturing process. At this time, since it is difficult to selectively etch the n ⁺ -type amorphous silicon film with a high selectivity with respect to the underlying amorphous silicon film, the lower amorphous silicon Etching was performed including a part of the film.

However, the surface of the amorphous silicon film (back channel interface) exposed to the etching gas is strongly affected by process damage, and has a very high interface state density due to defects. Was. Therefore, when the thickness of the amorphous silicon film in the channel portion after the etching becomes about 150 nm or less, the on-state characteristics of the thin film transistor element are significantly reduced due to the influence of the interface state on the back channel side. For these reasons, it was necessary to form a film as thick as about 300 nm as an amorphous silicon film.

As described above, in the conventional inverted staggered type thin film transistor element, (1) a part of the lower amorphous silicon film is partially removed in consideration of a margin for an unnecessary n ⁺ type amorphous silicon film on the channel. It is necessary to etch including it. (2) In order to obtain good ON characteristics, the thickness of the amorphous silicon film must be increased. There were mainly two issues. These challenges are
The following reasons are considered to increase the cost of the liquid crystal display.

That is, regarding the problem (1),
Since the etching selectivity between the n ⁺ type amorphous silicon film and the amorphous silicon film is small, the distribution of the etching amount in the panel tends to occur, and therefore, the portion where the etching amount is deep (ie, the channel portion after etching) (Where the amorphous silicon film thickness is small), the on-characteristics of the thin film transistor element are reduced, and display unevenness occurs in the panel, thereby lowering the product yield.

Regarding the problem (2), the plasma C
The throughput in the VD film forming process and the islanding dry etching process is reduced, and the cost is increased. In addition, when the thickness of the amorphous silicon film having high photosensitivity is large, the off-state current value of the thin film transistor element increases, and the holding characteristics are reduced, which may cause display unevenness in the panel. Become.

As described above, in the inverted staggered thin film transistor element, there is no need to remove unnecessary n ⁺ -type amorphous silicon film on the channel by etching, and a device technology capable of reducing the thickness of the amorphous silicon film. Development is needed.

[0011]

According to the present invention, a gate electrode, a gate insulating film, an island-like intrinsic amorphous silicon film, a source / drain electrode,
And said island-shaped intrinsic amorphous silicon film and a source
An inverted staggered thin film transistor element having an n ⁺ -type amorphous silicon film formed as an intermediate layer in a portion where the drain electrode overlaps, and an intrinsic amorphous silicon film having a surface roughness of 10 nm or less on the gate insulating film. Forming an n ⁺ -type amorphous silicon film having a thickness of 3 nm or more and 10 nm or less on the intrinsic amorphous silicon film, and then forming the intrinsic amorphous silicon film and the n ⁺ -type amorphous silicon film. processing the both membranes in an island shape, and then on the n ⁺ -type amorphous silicon film, after forming the source and drain electrodes, by plasma treatment, in the n ⁺ -type amorphous silicon film, said vacuum non A thin-film transistor element provided with an insulation reforming layer in which a portion where the amorphous silicon film and the source / drain electrodes do not overlap each other is insulated by plasma treatment. .

The present invention further provides a gate electrode, a gate insulating film, an island-like intrinsic amorphous silicon film, a source / drain electrode, and the island-like intrinsic amorphous silicon film and a source / drain electrode on at least a transparent insulating substrate. An inverted staggered thin film transistor having an n ⁺ -type amorphous silicon film formed as an intermediate layer in a portion where the drain electrode overlaps, and a surface roughness of 1 nm on the gate insulating film.
Forming an intrinsic amorphous silicon film having a thickness of not more than 0 nm, forming an n ⁺ -type amorphous silicon film having a thickness of not less than 3 nm and not more than 10 nm on the intrinsic amorphous silicon film; And n ⁺ -type amorphous silicon film are both processed into an island shape, then a source / drain electrode is formed on the n ⁺ -type amorphous silicon film, and a pixel electrode is formed on the source / drain electrode. Is formed, a portion of the n ⁺ -type amorphous silicon film where the intrinsic amorphous silicon film does not overlap with either the source / drain electrode or the pixel electrode is subjected to plasma processing. The present invention relates to a thin-film transistor element provided with an insulation reforming layer insulated by the method.

The present invention further provides a gate electrode, a gate insulating film, an island-like amorphous silicon film, a source / drain electrode, and an island-like intrinsic amorphous silicon film and a source / drain at least on a transparent insulating substrate. An inverted staggered thin film transistor having an n ⁺ -type amorphous silicon film formed as an intermediate layer in a portion where the electrode overlaps, and a surface roughness of 10 n on the gate insulating film.
m to form the following intrinsic amorphous silicon film and then forming an n ⁺ -type amorphous silicon film of thickness less than 3nm or 10nm on the intrinsic amorphous silicon film, and then the n ⁺ -type amorphous A source / drain electrode is formed on a silicon film, and a portion of the n ⁺ -type amorphous silicon film where the intrinsic amorphous silicon film and the source / drain electrode do not overlap with each other is subjected to plasma treatment. The present invention relates to a thin film transistor device characterized in that both the intrinsic amorphous silicon film and the insulation reforming layer are processed into an island shape after insulating and providing an insulation reforming layer.

Further, the present invention provides at least a step (1-
1) a step of sequentially forming a gate electrode and a gate insulating film on a transparent insulating substrate, and step (1-2):
A step of forming an intrinsic amorphous silicon film having a surface roughness of 10 nm or less by a plasma CVD method in which a high-frequency power density to be supplied is kept low, and a step (1-3). By a plasma CVD method in which a high-frequency power density is kept low, n ^{+ of not} less than 3 nm and not more than 10 nm
Forming an amorphous silicon film, step (1-4) patterning both the intrinsic amorphous silicon film and the n ⁺ -type amorphous silicon film into a desired island shape, 5) forming a source / drain electrode metal on the n ⁺ type amorphous silicon film and patterning to form a source / drain electrode, and step (1-6) a substrate on which the source / drain electrode is formed Is exposed to a plasma containing oxygen ions or oxygen radicals, and in the n ⁺ -type amorphous silicon film, a portion where the intrinsic amorphous silicon film and the source / drain electrodes do not overlap with each other is insulated. And a step of forming layers sequentially.

Further, the present invention provides at least a step (2-
1) a step of sequentially forming a gate electrode and a gate insulating film on a transparent insulating substrate, and a step (2-2) on the gate insulating film,
A step of forming an intrinsic amorphous silicon film having a surface roughness of 10 nm or less by a plasma CVD method in which a high-frequency power density to be supplied is kept low, and a step (2-3). By a plasma CVD method in which a high-frequency power density is kept low, n ^{+ of not} less than 3 nm and not more than 10 nm
(2-4) a step of patterning both the intrinsic amorphous silicon film and the n ⁺ -type amorphous silicon film into a desired island shape; 5) forming a source / drain electrode metal and a pixel electrode metal on the n ⁺ type amorphous silicon film and patterning them to form both a source / drain electrode and a pixel electrode; exposing the substrate formed with the source and drain electrodes and the pixel electrodes in a plasma containing oxygen ions or oxygen radicals, the source and drain electrodes or the and said vacuum amorphous silicon film in the n ⁺ -type amorphous silicon film And forming a modified insulating layer in which a portion where one of the pixel electrodes does not overlap is insulated. .

Further, the present invention provides at least a step (3-
1) a step of sequentially forming a gate electrode and a gate insulating film on a transparent insulating substrate, and a step (3-2):
A step of forming an intrinsic amorphous silicon film having a surface roughness of 10 nm or less by a plasma CVD method in which a high-frequency power density to be supplied is kept low, and a step (3-3) supplying the intrinsic amorphous silicon film onto the intrinsic amorphous silicon film. By a plasma CVD method in which a high-frequency power density is kept low, n ^{+ of not} less than 3 nm and not more than 10 nm
Forming a type amorphous silicon film, step (3-4) forming a source / drain electrode metal on the n ⁺ type amorphous silicon film and patterning to form a source / drain electrode (3-5) the substrate formed of the source and drain electrodes exposed to plasma containing oxygen ions or oxygen radicals, in said n ⁺ -type amorphous silicon film, said source and said vacuum amorphous silicon film Forming an insulating modified layer insulated at a portion where the drain electrode does not overlap, step (3-6) forming the insulating modified layer, the intrinsic amorphous silicon film and the n ⁺ type amorphous silicon film; And a step of sequentially performing patterning into a desired island shape.

As described above, the thin film transistor element of the present invention has the following particularly important points.

First, a portion of the n ⁺ -type amorphous silicon film where the intrinsic amorphous silicon film and the source / drain electrodes do not overlap is modified by plasma treatment and is insulated to form an amorphous silicon film. The surface of the silicon film (back channel interface) is not directly exposed to plasma or the like, so that the surface is not damaged. This has been disclosed in Japanese Patent Application No. 9-302090 (applicant: NEC Corporation).

Second, the inventor of the present application has found that the ON / OFF characteristics of the thin film transistor may be insufficient when only the first feature is present.
The inventors have found that the surface roughness of the intrinsic amorphous silicon film and the film thickness of the n ⁺ -type amorphous silicon film are closely related to the on / off characteristics, and have reached the present invention.

In particular, for a thin film transistor element having a channel length of 20 μm and a channel width of 6 μm which is applied to a switching element of a liquid crystal display, the on / off characteristics are important, and the on-state current at which a good display is obtained in the liquid crystal display is obtained. The typical value of is about 1.8 × 10
^-8 A or more. Similarly, for the off current, about 1.0
× 10 ⁻¹² A or less. The relationship between the on / off characteristics and the surface roughness of the intrinsic amorphous silicon film and the thickness of the n ⁺ type amorphous silicon film will be described below.

As shown in FIG. 1, a thin-film transistor element used to clarify the above-mentioned relationship is composed of a gate electrode 2, a gate insulating film 3, an intrinsic amorphous silicon film 4, ^{+ An} amorphous silicon film 5, a source electrode 6, a drain electrode 7, and an insulation reforming layer 8, and the insulation reforming layer is an intrinsic amorphous silicon film of at least an n ⁺ -type amorphous silicon film once formed. And a source / drain electrode where the portions where they do not overlap are insulated by plasma treatment. In particular, the surface roughness of the surface of the intrinsic amorphous silicon film before the plasma treatment and the thickness of the n ⁺ type amorphous silicon film formed on the intrinsic amorphous silicon film will be described.

FIG. 2 shows a change in on-current when the surface roughness of the intrinsic amorphous silicon semiconductor layer is changed when the thickness of the n ⁺ type amorphous silicon layer is 5 nm. When the film thickness of the n ⁺ -type amorphous silicon layer is 5 nm, the on-current rapidly decreases when the surface roughness of the intrinsic amorphous silicon semiconductor layer exceeds 10 nm. When the surface roughness of the intrinsic amorphous silicon semiconductor layer is 10 nm or less, a normal and sufficiently high on-state current is exhibited. Thus, it can be seen that there is a sharp change around 10 nm. The inventor of the present application estimates the reason why such a tendency is obtained as follows.

As the surface roughness of the intrinsic amorphous silicon semiconductor layer increases, the film structure of the n ⁺ -type amorphous silicon layer is uniform and continuous (Frank-van der Merwe's growth mode: FM Granules (Vo
lmer-Weber's growth style: VW growth style). As such, the surface area of the n ⁺ -type amorphous silicon layer increases. As the surface area increases, the surface states also increase. Free electrons in the n ⁺ -type amorphous silicon layer decrease. Therefore, the on-current decreases.

FIG. 3 compares the on-current when the film thickness of the n ⁺ -type amorphous silicon layer is changed when the surface roughness of the intrinsic amorphous silicon semiconductor layer is 10 nm and 20 nm. Surface roughness of the intrinsic amorphous silicon semiconductor layer is 10 nm
In the case (● in FIG. 3), when the thickness of the n ⁺ -type amorphous silicon layer changes from 20 nm to 5 nm, the on-current is slightly reduced, but is a normal on-current. On the other hand, when the surface roughness of the intrinsic amorphous silicon layer is 20 nm (○ in FIG. 3),
As the thickness of the n ⁺ type amorphous silicon layer is reduced from 20 nm to 5 nm, the on-current decreases linearly. n
^When the film thickness of the ⁺ type amorphous silicon layer is 20 nm or less, normal and high ON current is not obtained. That is, it is understood that the surface roughness of the intrinsic amorphous silicon layer is a very important factor for securing a high on-current.

On the other hand, if the thickness of the n ⁺ type amorphous silicon layer is 1
When the thickness exceeds 0 nm, the off-current rapidly increases as shown in FIG. With the increased off current, good display characteristics cannot be obtained in the liquid crystal display. This tendency does not depend on the surface roughness of the intrinsic amorphous silicon layer. This is a phenomenon caused by the thickness of the n ⁺ -type amorphous silicon layer which is insulated by plasma oxidation.

The thickness of the insulation reforming layer is determined by
By performing the plasma treatment for about 5 minutes, an insulation modification layer of about 11 nm is formed. Accordingly, it is the film thickness of the n ⁺ -type amorphous silicon layer is 15nm or more is left n ⁺ -type amorphous silicon layer unoxidized insulated, as shown in FIG. 4, n ⁺ -type amorphous When the thickness of the high-quality silicon layer is around 15 nm, the result matches the result that the off-current has a sufficiently high value.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. (A) of FIG.
In steps (1-1) to (1-3), FIG. 10B is a step (1-4), FIG. 10C is a step (1-5), and FIG. FIG. 9 is a process schematic diagram of a thin film transistor, corresponding to step (1-6) and illustrating one embodiment of the present invention. In the step (1-1), a gate electrode and a gate insulating film are formed as follows. Al as a metal for the gate electrode,
Mo, Cr, or the like is approximately 0.1 to 0.4 μm on a transparent insulating substrate 101 such as a glass substrate by a sputtering method or the like.
With a film thickness of The gate electrode 102 is manufactured by a photolithography method, etching, and separation. The entire surface of the substrate is covered with the gate electrode 102 by a plasma CVD method.
The silicon nitride film 103 serving as a gate insulating layer is approximately 0.2
It is formed with a thickness of about 0.6 μm. Here, the conditions for forming the silicon nitride film include a silane flow rate of about 100 sccm, an ammonia flow rate of about 200 sccm, and a nitrogen flow rate of about 20 sccm.
The standard is about 00 sccm, the film forming chamber pressure is about 120 Pa, the high frequency power density is about 0.1 W / cm ² , and the substrate temperature is about 300 ° C.

Next, as a step (1-2), the intrinsic a-Si film 104 to be an intrinsic amorphous silicon film is formed to a thickness of about 0.05 to
It is formed with a thickness of 0.3 μm. Conditions for forming the intrinsic a-Si film include a silane flow rate of about 250 to 320 sccm,
Hydrogen flow rate of about 700 to 1000 sccm, deposition chamber pressure 1
About 00 to 120 Pa, high frequency power density 0.015 to
0.025 W / cm ² , substrate temperature 260-310 ° C
The degree is standard. Thus, it is particularly necessary to keep the high-frequency power density low. Under these conditions, an intrinsic amorphous silicon film having a surface roughness of 10 nm or less, which is a feature of the present invention, is formed. The surface roughness referred to here is JI
It means the center line average roughness Ra described in S-B0601.

Next, as a step (1-3), the n ⁺ a-Si film 105 serving as an ohmic contact layer is formed in the order of 3 to 1
Coat continuously with a film thickness of 0 nm. The conditions for forming the n ⁺ a-Si film include a silane flow rate of about 40 to 70 sccm and a hydrogen-based 0.5% phosphine mixed gas flow rate of 2%.
Approximately 00 to 350 sccm, pressure in the film forming chamber 100 to 120
About Pa, high frequency power density 0.01 to 0.02 W / cm
^A standard of about ² and a substrate temperature of about 260 to 310 ° C. are standard. Thus, it is particularly necessary to keep the high-frequency power density low. Under these conditions, an n ⁺ amorphous silicon film having a thickness of 10 nm or less, which is a feature of the present invention, is formed. The lower limit of the thickness of the n ⁺ amorphous silicon film needs to be 3 nm or more, which is enough to confirm that the n ⁺ amorphous silicon film is clearly formed. As the n-type impurity, phosphorus is preferable, but arsenic and antimony can be used in addition to phosphorus. (FIG. 10A) Next, the step (1-4)
Then, the n ⁺ a-Si film and the a-Si film are patterned into an island shape by photolithography, etching, and peeling, thereby forming an island-shaped ohmic contact layer and an intrinsic amorphous silicon semiconductor layer. (End of FIG. 10
(B)) In the step (1-5), the n ⁺ a-Si film 105 is coated with Al, Mo, Cr, or the like to a thickness of about 0.1 to 0.4 μm by a sputtering method or the like. The source electrode 106 and the drain electrode 107 are formed by photolithography and etching. Thereafter, since the substrate that has gone through these steps is exposed to oxygen plasma, the resist is not yet stripped. (FIG. 10 (c)) In step (1-6), the substrate that has undergone each of steps (1-1) to (1-5) is exposed to plasma containing oxygen ions or oxygen radicals. At this time, the oxygen plasma processing conditions include an oxygen flow rate of 30 seconds.
The standard is about ccm, gas pressure of about 10 Pa, high frequency power density of about 0.05 to 0.40 W / cm ² , and processing time of about 2 to 5 minutes. (FIG. 10 (d)) FIG. 5 shows the relationship between the plasma processing time and the plasma oxide film thickness (the thickness of the insulating modified layer). Oxidation reforming occurs when a substrate having an n ⁺ type amorphous silicon layer is placed on the anode side of the parallel plate type plasma processing apparatus (（in FIG. 5) and when it is placed on the cathode side (● in FIG. 5). The thicknesses of the layers formed differ greatly. When it is installed on the anode side, the oxide film thickness is constant at about 3 nm and does not increase even if the processing time is lengthened. In such a case, normal on / off characteristics cannot be obtained. On the other hand, when it is installed on the cathode side, if the processing time is lengthened, the oxide film thickness increases and reaches 11 nm in 5 minutes. Thus, it can be seen that the insulation reforming treatment by the plasma cathode oxidation method is effective for forming the insulation reforming layer. Also, +
It has been confirmed that a bias-applied plasma anodic oxidation method in which a processing substrate is placed on an anode electrode to which a bias voltage is applied and plasma is applied is also effective in forming an insulating modified layer having a thickness of 10 nm or more. The oxygen plasma processing conditions in this method include a bias voltage of 1 kV and an oxygen flow rate of 16 kV.
The standard is about 00 sccm, gas pressure is about 27 Pa, high frequency power density is about 1 to 3 W / cm ² , and processing time is about 3 minutes.

As the plasma processing apparatus, a parallel plate type was used, and the substrate was set on the cathode electrode in the plasma processing apparatus. Under this condition, the self-bias voltage was -600.
The treatment is performed using the plasma cathode oxidation method under the condition of -100V. By exposing the substrate to oxygen plasma under such conditions, the n ⁺ amorphous silicon layer at the portion where the island-like intrinsic amorphous silicon semiconductor layer and the source / drain electrodes do not overlap is subjected to insulation reforming. You. This portion is referred to as an insulating modified layer 108. This results in a thin film transistor that is turned on and off by the gate voltage.

Next, the resist is stripped. The source-drain electrodes were not oxidized because the resist was coated on the source-drain electrodes during the oxidizing plasma treatment.

FIG. 1 shows a thin film transistor device manufactured by the above steps. On a transparent insulating substrate 1, a gate electrode 2, a gate insulating film 3, an intrinsic amorphous silicon film 4, n ⁺
The amorphous silicon film 5, the source electrode 6, the drain electrode 7,
The thin film transistor is composed of the insulation reforming layer 8 and has this structure to be turned on and off by a gate voltage.

As another embodiment of the process shown in FIG. 10, in the process shown in FIG. 10C, the plasma processing shown in FIG. 10D is performed with the pixel electrode further provided on the source / drain electrodes. You can also. The pixel electrode can be formed by coating a transparent conductive metal oxide film typified by indium tin oxide with a thickness of about 0.03 to 0.1 μm using a sputtering method or the like. The portion subjected to the plasma treatment is a portion where the source / drain electrode and the intrinsic amorphous silicon film do not overlap, or a portion where the pixel electrode and the intrinsic amorphous silicon film do not overlap. For such a structure,
An active matrix substrate can be used by coating a silicon nitride film as a passivation film on the pixel electrode to a thickness of 50 to 300 nm by a plasma CVD method.

Also, unlike FIG. 10, after the island processing. Plasma treatment is also possible. That is, in the step of FIG. 10, the source electrode and the drain electrode were formed after the n ⁺ a-Si film and the a-Si film were patterned into an island shape, but after the source and drain electrodes were formed, the n ⁺ a- It is also possible to process the Si film and the a-Si film into an island shape. FIG. 11 shows a schematic view of the process in such a case. FIG. 11A shows the process (3-
1) to (3-3), FIG.
FIG. 11C illustrates the step (3-5) in FIG.
(D) corresponds to the step (3-6), and describes a thin film transistor for explaining an embodiment in which the n ⁺ a-Si film and the a-Si film are processed into island shapes after forming the source / drain electrodes. FIG.

Steps (3-1) to (3-3) show the steps from the formation of the gate electrode to the formation of the n ⁺ a-Si film. Substrate 1
01, a gate electrode 102, a gate insulating layer 103, a-
Si film (intrinsic amorphous silicon film) 104, n ⁺ a-Si
A film (n ⁺ amorphous silicon film) 105 is formed. (FIG. 11A) Next, in step (3-4), n ⁺ a-S
Source / drain electrodes are provided on the i-film 105. The source electrode 10 is formed by photolithography and etching.
6. The drain electrode 107 is formed. Thereafter, since the substrate that has gone through these steps (3-1) to (3-4) is exposed to oxygen plasma, the resist is not yet stripped. (The above figure 1
1 (b)) Next, in a step (3-5), the n ⁺ a-Si film 105 is insulated by plasma treatment to form an insulation modified layer 108. (FIG. 11 (c)) Next, in step (3-6), an a-Si film (intrinsic amorphous silicon film) 1
04 and the insulating layer 108 are removed by photolithography and etching to obtain a desired island shape.
(FIG. 11D) The film formation conditions and the like used in the above steps can be performed in exactly the same manner as in FIG.

A silicon nitride film is formed as a passivation film on the thin film transistor element substrate manufactured by the process of FIG. 10 or FIG.
It may be coated with a thickness of 00 nm.

Further, in order to form an active matrix substrate of the liquid crystal display shown in FIG. 7, a contact hole is formed in the passivation film 9 and the gate insulating layer 3 to form a conductive transparent metal oxide film (for example, indium tin oxide). And the pixel electrode 1 connected to the drain electrode 7
0 and the gate electrode terminal 11 may be formed. The resist was coated during the plasma oxidation, and the surface of the drain electrode could not be oxidized. Therefore, the drain electrode and the pixel electrode could be well contacted with low resistance.

[0038]

As described above, the portion of the n ⁺ -type amorphous silicon film where the intrinsic amorphous silicon film and the source / drain electrodes do not overlap is modified by plasma treatment to make it insulating. The surface of the amorphous silicon film (back channel interface) is not directly exposed to plasma or the like and is not damaged, and the surface roughness of the intrinsic amorphous silicon semiconductor layer is controlled to 10 nm or less. By controlling the thickness of the n ⁺ -type amorphous silicon layer to 10 nm or less, good on / off characteristics of the thin film transistor can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of an inverted staggered thin film transistor element according to an embodiment of the present invention.

FIG. 2 shows a change in on-state current when the surface roughness of the intrinsic amorphous silicon semiconductor layer is changed when the film thickness of the n ⁺ type amorphous silicon layer is 5 nm.

FIG. 3 shows that the intrinsic silicon semiconductor layer has a surface roughness of 10 nm.
It is a comparison of the on-current when the thickness of the n ⁺ type amorphous silicon layer is changed between (●) and 20 nm (（).

FIG. 4 shows the off-state current when the film thickness of the n ⁺ -type amorphous silicon layer is changed when the plasma oxidation treatment time is 5 minutes.

FIG. 5 is a comparison of the change in the thickness of the plasma oxidation treatment of the n ⁺ -type amorphous silicon layer when the treatment time is varied in the case of cathodic oxidation (●) and anodization (○).

FIG. 6 shows a change in the plasma oxide film thickness of the n ⁺ -type amorphous silicon layer when a positive bias voltage is applied to the anode electrode to change the thickness in the anodic oxidation.

FIG. 7 is a schematic sectional view of one pixel portion of an active matrix substrate of a liquid crystal display using an inverted staggered thin film transistor according to one embodiment of the present invention.

FIG. 8 is a schematic sectional view of one pixel portion of an active matrix substrate of a liquid crystal display using an inverted staggered thin film transistor according to one embodiment of the present invention.

FIG. 9 is a cross-sectional view of an inverted staggered thin film transistor element generally used as a switching element of a pixel of a liquid crystal display.

FIG. 10 is a process schematic diagram of a thin film transistor for explaining an embodiment of the present invention.

FIG. 11 is a process schematic view of a thin film transistor for explaining an embodiment of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 transparent insulating substrate 2 gate electrode 3 gate insulating layer 4 intrinsic amorphous silicon semiconductor layer 5 n ⁺ amorphous silicon semiconductor layer (ohmic contact layer) 6 source electrode 7 drain electrode 8 insulation modification layer 9 passivation film 10 pixel Electrode 11 Gate electrode terminal 101 Transparent insulating substrate 102 Gate electrode 103 Silicon nitride film 104 Intrinsic a-Si film (intrinsic amorphous silicon film) 105 n ⁺ a-Si film (n ⁺ amorphous silicon film) 106 Source electrode 107 Drain electrode 108 Insulation modification layer

Continuation of the front page (56) References JP-A-4-218926 (JP, A) JP-A-5-150268 (JP, A) JP-A-2-237161 (JP, A) JP-A-10-81968 (JP) JP-A-8-130315 (JP, A) JP-A-64-59863 (JP, A) JP-A-6-163592 (JP, A) JP-A-2-191374 (JP, A) (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/786 H01L 21/336

Claims (14)

(57) [Claims] 1. A gate electrode, a gate insulating film, an intrinsic amorphous silicon film, and n ⁺ formed sequentially on a transparent insulating substrate.
A thin film transistor element comprising a type amorphous silicon film, and a source electrode and a drain electrode, which can be used as a switching element of a liquid crystal display, wherein the intrinsic amorphous silicon film has a surface roughness of 10 nm or less; The thickness of the n ⁺ type amorphous silicon film is 3 nm or more and 10
a thin film transistor element having a structure in which an insulating modified layer formed by insulating the n ⁺ -type amorphous silicon film is provided between the source electrode and the drain electrode. 2. A gate electrode, a gate insulating film, an island-like intrinsic amorphous silicon film, a source electrode / drain electrode, and the island-like intrinsic amorphous silicon film and a source electrode / drain at least on a transparent insulating substrate. An inverted staggered thin film transistor element having an n ⁺ -type amorphous silicon film formed as an intermediate layer in a portion where an electrode overlaps, and an island-like intrinsic amorphous silicon film formed on the gate insulating film Has a surface roughness of 10 nm or less, and the thickness of the n ⁺ type amorphous silicon film formed on the island-like intrinsic amorphous silicon film is 3 nm or more and 10 nm or less.
nm or less, and the island-like intrinsic amorphous silicon film and the source electrode
In addition to the n ⁺ type amorphous silicon film present as an intermediate layer in the portion where the drain electrode overlaps, the island-like intrinsic amorphous silicon film and the source / drain electrode do not overlap, and at least the to have the island-shaped intrinsic amorphous silicon n ⁺ -type amorphous silicon film formed on the film insulated by the plasma treatment comprising providing an insulating modified layer structure between the source electrode and the drain electrode A thin film transistor element characterized by the above-mentioned. 3. The thin film transistor element according to claim 2, further comprising a pixel electrode electrically connected to the drain electrode of the thin film transistor element. 4. The thin film transistor device according to claim 2, wherein the thickness of the insulation reforming layer is larger than the thickness of the n ⁺ -type amorphous silicon film. 5. The method according to claim 2, wherein the insulation reforming layer is an oxide film formed by performing a plasma treatment on the n ⁺ -type amorphous silicon film. Thin film transistor element. 6. An oxide film formed by subjecting said n ⁺ -type amorphous silicon film to plasma treatment is formed by a plasma cathode oxidation method or a bias-applied plasma anodization method in the presence of oxygen ions or oxygen radicals. 6. The thin film transistor element according to claim 5, wherein the thin film transistor is an oxide film. 7. At least a step (1-1) a step of sequentially forming a gate electrode and a gate insulating film on a transparent insulating substrate, and a step (1-2) forming a surface on the gate insulating film by a plasma CVD method. Forming an intrinsic amorphous silicon film having a roughness of 10 nm or less, and step (1-3) forming an n ⁺ -type amorphous film having a thickness of 3 nm to 10 nm on the intrinsic amorphous silicon film by a plasma CVD method. Forming a crystalline silicon film; and (1-4) forming the intrinsic amorphous silicon film and the n ⁺
Patterning both the amorphous silicon film into a desired island shape; Step (1-5): forming a metal for a source electrode and a drain electrode on the n ⁺ -type amorphous silicon film; - forming a drain electrode, step (1-6) exposing a substrate formed of the source electrode and the drain electrode in a plasma containing oxygen ions or oxygen radicals, in said n ⁺ -type amorphous silicon film, the Forming an insulating modified layer by insulating a portion where the intrinsic amorphous silicon film and the source electrode / drain electrode do not overlap with each other, and forming the insulating modified layer. The method of manufacturing a thin film transistor device according to claim 1, wherein the steps are performed in the order of execution. 8. A step (2-1) of sequentially forming a gate electrode and a gate insulating film on a transparent insulating substrate, and step (2-2) forming a surface on the gate insulating film by a plasma CVD method. Forming an intrinsic amorphous silicon film having a roughness of 10 nm or less, step (2-3) forming an n ⁺ -type amorphous film having a thickness of 3 nm to 10 nm on the intrinsic amorphous silicon film by a plasma CVD method; (2-4) forming the intrinsic amorphous silicon film and the n +
Patterning both the amorphous silicon film into a desired island shape; and (2-5) forming a metal for a source electrode / drain electrode and a pixel electrode metal on the n ⁺ -type amorphous silicon film;
Patterning to form both a source electrode / drain electrode and a pixel electrode; and step (2-6) exposing the substrate on which the source electrode / drain electrode and the pixel electrode are formed to a plasma containing oxygen ions or oxygen radicals. In the n ⁺ -type amorphous silicon film, a portion where the intrinsic amorphous silicon film does not overlap with any one of the source electrode / drain electrode or the pixel electrode is insulated to form an insulation modified layer. A method of manufacturing a thin film transistor element, wherein the steps (2-1) to (2-6) are performed in the order of execution. 9. At least a step (3-1) a step of sequentially forming a gate electrode and a gate insulating film on a transparent insulating substrate; and a step (3-2) forming a surface on the gate insulating film by a plasma CVD method. Forming an intrinsic amorphous silicon film having a roughness of 10 nm or less, and (3-3) forming an n ⁺ -type amorphous film having a thickness of 3 nm to 10 nm on the intrinsic amorphous silicon film by a plasma CVD method. (3-4) forming a source electrode / drain electrode metal on the n ⁺ -type amorphous silicon film and patterning to form a source electrode / drain electrode; 3-5) exposing a substrate formed of the source electrode and the drain electrode in a plasma containing oxygen ions or oxygen radicals, in said n ⁺ -type amorphous silicon film, the source and said vacuum amorphous silicon film The portion where the electrode and the drain electrode do not overlap with insulated, forming an insulating modified layer, step (3-6) wherein the insulating reforming layer, an intrinsic amorphous silicon film and the n ⁺ -type amorphous A step of patterning the silicon film into a desired island shape, wherein each of the steps (3-1) to (3-6) is performed according to the order of execution. Manufacturing method. 10. The step (1-2), the step (2-
2), the high frequency power density supplied in the plasma CVD process in the process (3-2) is 0.015 to 0.025 W
/ Cm ² is selected within the range.
10. The method for manufacturing a thin film transistor element according to any one of the above items 9. 11. The step (1-3) and the step (2-
3), the high frequency power density supplied in the plasma CVD step in the step (3-3) is 0.01 to 0.02 W / c.
The method for manufacturing a thin film transistor device according to claim 7, wherein the thickness is selected within a range of m ² . 12. The step (1-2) and the step (2-
2) The film forming conditions of the plasma CVD method in the step (3-2) are as follows: silane flow rate 250 to 320 sccm, hydrogen flow rate 700 to 1000 sccm, and film forming pressure 100 to 120.
The method for manufacturing a thin film transistor device according to claim 10, wherein the temperature is selected from Pa and a substrate temperature of 260 to 310C. 13. The step (1-3) and the step (2-
3) The film forming conditions of the plasma CVD method in the step (3-3) are set as follows: the silane flow rate is 40 to 70 sccm, and the flow rate of hydrogen containing 0.5% phosphine is 200 to 350 sccc.
m, film formation pressure 100 to 120 Pa, substrate temperature 26
The method according to claim 11, wherein the temperature is selected from 0 to 310C. 14. The step (1-2) and the step (2-
2) The film forming conditions of the plasma CVD method in the step (3-2) are as follows: silane flow rate 250 to 320 sccm, hydrogen flow rate 700 to 1000 sccm, and film forming pressure 100 to 120.
Pa, high frequency power density 0.015 to 0.025 W / cm
^{2. The} substrate temperature is selected from 260 to 310 ° C., and the film forming conditions of the plasma CVD method in the steps (1-3), (2-3), and (3-3) are set as follows.
Silane flow rate 40-70 sccm, flow rate of hydrogen containing 0.5% phosphine 200-350 sccm, film formation pressure 100-120 Pa, high frequency power density 0.01-
The method according to claim 7, wherein the temperature is selected to be 0.02 W / cm ² and the substrate temperature is 260 to 310 ° C. 11.