JP2000124463A - Thin film transistor element and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a reverse staggered type thin film transistor element which is formed to a thin film while good ON/OFF characteristic is maintained. SOLUTION: A transparent insulation substrate 101, a gate electrode 102 and a gate insulation film 103 are formed one by one and an intrinsic amorphous silicon film 104, whose surface roughness is at most 10 nm and an n+-type amorphous silicon film whose thickness is 3 nm or more and 10 nm or less are formed thereon. Then, both the intrinsic amorphous silicon film and the n+-type amorphous silicon film are processed to an island shape. Then, in the thin film transistor after a source/drain electrode is formed on the n+-type amorphous silicon film, an insulation modified layer whose part wherein the intrinsic amorphous silicon film and the source/drain electrode do not overlap each other is insulated by plasma treatment is provided in the n+-type amorphous silicon film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor device and a method of manufacturing the same, and more particularly, to a structure of a thin film transistor device used in an active matrix type liquid crystal display and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, active matrix type liquid crystal displays using thin film transistors (TFTs) using a hydrogenated amorphous silicon film as switching elements for each display pixel have been mass-produced. In particular, with the spread of notebook personal computers, acceptance of liquid crystal displays has rapidly increased, and improvement in productivity has been demanded.

FIG. 9 is a cross-sectional view of an inverted staggered thin film transistor element generally used as a switching element of a pixel of a liquid crystal display at present.

First, a gate electrode metal is formed on a transparent insulating substrate 1 and patterned into a desired shape to form a gate electrode 2. On this, a silicon film and an n ⁺ -type amorphous silicon film are sequentially formed to form a gate insulating film 3 made of a silicon nitride film, an amorphous silicon film 4, and an ohmic contact made of a source / drain region. ^{The +} type amorphous silicon film 5 and the amorphous silicon film 4 are patterned into an island shape. Subsequently, a source / drain electrode metal is formed and patterned into a desired shape to form a source electrode 6 and a drain electrode 7. Finally, the unnecessary n ⁺ -type amorphous silicon film 5 on the channel is removed by etching including a part of the amorphous silicon film 4 in consideration of a margin,
The thin film transistor device shown in FIG. 9 is completed.

[0005]

As described above, in the conventional inverted staggered type thin film transistor element, it is necessary to remove unnecessary n ⁺ type amorphous silicon film on the channel by etching during the manufacturing process. At this time, since it is difficult to selectively etch the n ⁺ -type amorphous silicon film with a high selectivity with respect to the underlying amorphous silicon film, the lower amorphous silicon Etching was performed including a part of the film.

However, the surface of the amorphous silicon film (back channel interface) exposed to the etching gas is strongly affected by process damage, and has a very high interface state density due to defects. Was. Therefore, when the thickness of the amorphous silicon film in the channel portion after the etching becomes about 150 nm or less, the on-state characteristics of the thin film transistor element are significantly reduced due to the influence of the interface state on the back channel side. For these reasons, it was necessary to form a film as thick as about 300 nm as an amorphous silicon film.

As described above, in the conventional inverted staggered type thin film transistor element, (1) a part of the lower amorphous silicon film is partially removed in consideration of a margin for an unnecessary n ⁺ type amorphous silicon film on the channel. It is necessary to etch including it. (2) In order to obtain good ON characteristics, the thickness of the amorphous silicon film must be increased. There were mainly two issues. These challenges are
The following reasons are considered to increase the cost of the liquid crystal display.

That is, regarding the problem (1),
Since the etching selectivity between the n ⁺ type amorphous silicon film and the amorphous silicon film is small, the distribution of the etching amount in the panel tends to occur, and therefore, the portion where the etching amount is deep (that is, the channel portion after the etching) (Where the amorphous silicon film thickness is small), the on-characteristics of the thin film transistor element are reduced, and display unevenness occurs in the panel, thereby lowering the product yield.

Regarding the problem (2), the plasma C
The throughput in the VD film forming process and the islanding dry etching process is reduced, and the cost is increased. In addition, when the thickness of the amorphous silicon film having high photosensitivity is large, the off-state current value of the thin film transistor element increases, and the holding characteristics are reduced, which may cause display unevenness in the panel. Become.

As described above, in the inverted staggered thin film transistor element, there is no need to remove unnecessary n ⁺ -type amorphous silicon film on the channel by etching, and a device technology capable of reducing the thickness of the amorphous silicon film. Development is needed.

[0011]

According to the present invention, a gate electrode, a gate insulating film, an island-like intrinsic amorphous silicon film, a source / drain electrode,
And said island-shaped intrinsic amorphous silicon film and a source
An inverted staggered thin film transistor element having an n ⁺ -type amorphous silicon film formed as an intermediate layer in a portion where the drain electrode overlaps, and an intrinsic amorphous silicon film having a surface roughness of 10 nm or less on the gate insulating film. Forming an n ⁺ -type amorphous silicon film having a thickness of 3 nm or more and 10 nm or less on the intrinsic amorphous silicon film, and then forming the intrinsic amorphous silicon film and the n ⁺ -type amorphous silicon film. processing the both membranes in an island shape, and then on the n ⁺ -type amorphous silicon film, after forming the source and drain electrodes, by plasma treatment, in the n ⁺ -type amorphous silicon film, said vacuum non A thin-film transistor element provided with an insulation reforming layer in which a portion where the amorphous silicon film and the source / drain electrodes do not overlap each other is insulated by plasma treatment. .

The present invention further provides a gate electrode, a gate insulating film, an island-like intrinsic amorphous silicon film, a source / drain electrode, and the island-like intrinsic amorphous silicon film and a source / drain electrode on at least a transparent insulating substrate. An inverted staggered thin film transistor having an n ⁺ -type amorphous silicon film formed as an intermediate layer in a portion where the drain electrode overlaps, and a surface roughness of 1 nm on the gate insulating film.
Forming an intrinsic amorphous silicon film having a thickness of not more than 0 nm, forming an n ⁺ -type amorphous silicon film having a thickness of not less than 3 nm and not more than 10 nm on the intrinsic amorphous silicon film; And n ⁺ -type amorphous silicon film are both processed into an island shape, then a source / drain electrode is formed on the n ⁺ -type amorphous silicon film, and a pixel electrode is formed on the source / drain electrode. Is formed, a portion of the n ⁺ -type amorphous silicon film where the intrinsic amorphous silicon film does not overlap with either the source / drain electrode or the pixel electrode is subjected to plasma processing. The present invention relates to a thin-film transistor element provided with an insulation reforming layer insulated by the method.

The present invention further provides a gate electrode, a gate insulating film, an island-like amorphous silicon film, a source / drain electrode, and an island-like intrinsic amorphous silicon film and a source / drain at least on a transparent insulating substrate. An inverted staggered thin film transistor having an n ⁺ -type amorphous silicon film formed as an intermediate layer in a portion where the electrode overlaps, and a surface roughness of 10 n on the gate insulating film.
m to form the following intrinsic amorphous silicon film and then forming an n ⁺ -type amorphous silicon film of thickness less than 3nm or 10nm on the intrinsic amorphous silicon film, and then the n ⁺ -type amorphous A source / drain electrode is formed on a silicon film, and a portion of the n ⁺ -type amorphous silicon film where the intrinsic amorphous silicon film and the source / drain electrode do not overlap with each other is subjected to plasma treatment. The present invention relates to a thin film transistor device characterized in that both the intrinsic amorphous silicon film and the insulation reforming layer are processed into an island shape after insulating and providing an insulation reforming layer.

Further, the present invention provides, at least, (1) a step of sequentially forming a gate electrode and a gate insulating film on a transparent insulating substrate, and (2) a low-frequency power density applied to the gate insulating film. A step of forming an intrinsic amorphous silicon film having a surface roughness of 10 nm or less by a plasma CVD method, and (3) a plasma CVD method in which a high-frequency power density applied to the intrinsic amorphous silicon film is kept low. Forming an n ⁺ -type amorphous silicon film having a thickness of 3 nm or more and 10 nm or less; (4) patterning both the intrinsic amorphous silicon film and the n ⁺ -type amorphous silicon film into a desired island shape; (5) forming a source / drain electrode metal on the n ⁺ -type amorphous silicon film and patterning to form a source / drain electrode; (6)
The substrate on which the source / drain electrodes are formed is exposed to plasma containing oxygen ions or oxygen radicals, and in the n ⁺ type amorphous silicon film, the intrinsic amorphous silicon film and the source / drain electrodes overlap. And a step of forming an insulation reforming layer in which the portions that do not match are insulated are sequentially performed.

Further, the present invention provides at least (1) a step of sequentially forming a gate electrode and a gate insulating film on a transparent insulating substrate, and (2) a low-frequency power density applied to the gate insulating film. A step of forming an intrinsic amorphous silicon film having a surface roughness of 10 nm or less by a plasma CVD method, and (3) a plasma CVD method in which a high-frequency power density applied to the intrinsic amorphous silicon film is kept low. Forming an n ⁺ -type amorphous silicon film having a thickness of 3 nm or more and 10 nm or less; (4) patterning both the intrinsic amorphous silicon film and the n ⁺ -type amorphous silicon film into a desired island shape; step, to form both the (5) the n ⁺ -type amorphous silicon film to form a metal and the pixel electrode metal for the source and drain electrodes on the patterning to the source and drain electrodes and the pixel electrodes Step, (6) a substrate formed of the source and drain electrodes and the pixel electrode exposed to plasma containing oxygen ions or oxygen radicals, wherein the said vacuum amorphous silicon film in the n ⁺ -type amorphous silicon film And forming a modified insulating layer in which a portion where either the source / drain electrode or the pixel electrode does not overlap is insulated.

Further, according to the present invention, at least (1) a step of sequentially forming a gate electrode and a gate insulating film on a transparent insulating substrate, and (2) a high-frequency power density applied to the gate insulating film is suppressed to be low. A step of forming an intrinsic amorphous silicon film having a surface roughness of 10 nm or less by a plasma CVD method, and (3) a plasma CVD method in which a high-frequency power density applied to the intrinsic amorphous silicon film is kept low. Forming an n ⁺ -type amorphous silicon film having a thickness of 3 nm or more and 10 nm or less; (4) forming a source / drain electrode metal on the n ⁺ -type amorphous silicon film and patterning the same; forming a, (5) the exposing substrate formed of source and drain electrodes in a plasma containing oxygen ions or oxygen radicals, in said n ⁺ -type amorphous silicon film, said vacuum Forming an insulating modified layer portions were insulated to said source-drain electrode and the amorphous silicon film do not overlap, (6) the insulating reforming layer, an intrinsic amorphous silicon film and the n ⁺ -type And a step of sequentially patterning the amorphous silicon film into a desired island shape.

As described above, the thin film transistor element of the present invention has the following particularly important points.

First, a portion of the n ⁺ -type amorphous silicon film where the intrinsic amorphous silicon film and the source / drain electrodes do not overlap is modified by plasma treatment and is insulated to form an amorphous silicon film. The surface of the silicon film (back channel interface) is not directly exposed to plasma or the like, so that the surface is not damaged. This has been disclosed in Japanese Patent Application No. 9-302090 (applicant: NEC Corporation).

Second, the inventor of the present application has found that the ON / OFF characteristics of the thin film transistor may be insufficient when only the first feature is present.
The inventors have found that the surface roughness of the intrinsic amorphous silicon film and the film thickness of the n ⁺ -type amorphous silicon film are closely related to the on / off characteristics, and have reached the present invention.

In particular, for a thin film transistor element having a channel length of 20 μm and a channel width of 6 μm which is applied to a switching element of a liquid crystal display, the on / off characteristics are important, and the on-state current at which a good display is obtained in the liquid crystal display is obtained. The typical value of is about 1.8 × 10
^-8 A or more. Similarly, for the off current, about 1.0
× 10 ⁻¹² A or less. The relationship between the on / off characteristics and the surface roughness of the intrinsic amorphous silicon film and the thickness of the n ⁺ type amorphous silicon film will be described below.

As shown in FIG. 1, a thin-film transistor element used to clarify the above-mentioned relationship is composed of a gate electrode 2, a gate insulating film 3, an intrinsic amorphous silicon film 4, ^{+ An} amorphous silicon film 5, a source electrode 6, a drain electrode 7, and an insulation reforming layer 8, and the insulation reforming layer is an intrinsic amorphous silicon film of at least an n ⁺ -type amorphous silicon film once formed. And a source / drain electrode where the portions where they do not overlap are insulated by plasma treatment. In particular, the surface roughness of the surface of the intrinsic amorphous silicon film before the plasma treatment and the thickness of the n ⁺ type amorphous silicon film formed on the intrinsic amorphous silicon film will be described.

FIG. 2 shows a change in on-current when the surface roughness of the intrinsic amorphous silicon semiconductor layer is changed when the thickness of the n ⁺ type amorphous silicon layer is 5 nm. When the film thickness of the n ⁺ -type amorphous silicon layer is 5 nm, the on-current rapidly decreases when the surface roughness of the intrinsic amorphous silicon semiconductor layer exceeds 10 nm. When the surface roughness of the intrinsic amorphous silicon semiconductor layer is 10 nm or less, a normal and sufficiently high on-state current is exhibited. Thus, it can be seen that there is a sharp change around 10 nm. The inventor of the present application estimates the reason why such a tendency is obtained as follows.

As the surface roughness of the intrinsic amorphous silicon semiconductor layer increases, the film structure of the n ⁺ -type amorphous silicon layer is uniform and continuous (Frank-van der Merwe's growth mode: FM Granules (Vo
lmer-Weber's growth style: VW growth style). As such, the surface area of the n ⁺ -type amorphous silicon layer increases. As the surface area increases, the surface states also increase. Free electrons in the n ⁺ -type amorphous silicon layer decrease. Therefore, the on-current decreases.

FIG. 3 compares the on-current when the film thickness of the n ⁺ -type amorphous silicon layer is changed when the surface roughness of the intrinsic amorphous silicon semiconductor layer is 10 nm and 20 nm. Surface roughness of the intrinsic amorphous silicon semiconductor layer is 10 nm
In the case (● in FIG. 3), when the thickness of the n ⁺ -type amorphous silicon layer changes from 20 nm to 5 nm, the on-current is slightly reduced, but is a normal on-current. On the other hand, when the surface roughness of the intrinsic amorphous silicon layer is 20 nm (○ in FIG. 3),
As the thickness of the n ⁺ type amorphous silicon layer is reduced from 20 nm to 5 nm, the on-current decreases linearly. n
^When the film thickness of the ⁺ type amorphous silicon layer is 20 nm or less, normal and high ON current is not obtained. That is, it is understood that the surface roughness of the intrinsic amorphous silicon layer is a very important factor for securing a high on-current.

On the other hand, if the thickness of the n ⁺ type amorphous silicon layer is 1
When the thickness exceeds 0 nm, the off-current rapidly increases as shown in FIG. With the increased off current, good display characteristics cannot be obtained in the liquid crystal display. This tendency does not depend on the surface roughness of the intrinsic amorphous silicon layer. This is a phenomenon caused by the thickness of the n ⁺ -type amorphous silicon layer which is insulated by plasma oxidation.

The thickness of the insulation reforming layer is determined by
By performing the plasma treatment for about 5 minutes, an insulation modification layer of about 11 nm is formed. Accordingly, it is the film thickness of the n ⁺ -type amorphous silicon layer is 15nm or more is left n ⁺ -type amorphous silicon layer unoxidized insulated, as shown in FIG. 4, n ⁺ -type amorphous When the thickness of the high-quality silicon layer is around 15 nm, the result matches the result that the off-current has a sufficiently high value.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. (A) of FIG.
FIG. 10 (b) corresponds to claim 7 (4), and FIG. 10 (c) corresponds to claim 7 (5).
FIG. 10D is a process schematic diagram of a thin film transistor according to an embodiment of the present invention, corresponding to claim 7. In the step (1), a gate electrode and a gate insulating film are formed as follows. Al, Mo, Cr, or the like as a metal for a gate electrode is formed on a transparent insulating substrate 101, for example, a glass substrate by a sputtering method or the like.
Coat with a thickness of 0.4 μm. The gate electrode 102 is manufactured by a photolithography method, etching, and separation. Plasma CV covering the gate electrode 102 and covering the entire surface of the substrate
The silicon nitride film 103 serving as a gate insulating layer is formed by the method D.
Is formed with a film thickness of approximately 0.2 to 0.6 μm. here,
Conditions for forming the silicon nitride film include a silane flow rate of 100
sccm, ammonia flow about 200 sccm, nitrogen flow about 2000 sccm, film forming chamber pressure about 120 Pa, high frequency power density about 0.1 W / cm ² , substrate temperature 3
About 00 ° C. is standard.

Next, in the step (2) of claim 7, the intrinsic a-Si film 104 to be the intrinsic amorphous silicon film is formed to a thickness of about 0.1.
It is formed with a thickness of from 0.5 to 0.3 μm. Conditions for forming the intrinsic a-Si film include a silane flow rate of 250 to 320 sccm.
About, hydrogen flow rate about 700 to 1000 sccm, film forming chamber pressure about 100 to 120 Pa, high frequency power density 0.01
5 to 0.025 W / cm ² , substrate temperature 260 to 31
About 0 ° C. is standard. Thus, it is particularly necessary to keep the high-frequency power density low. Under these conditions,
An intrinsic amorphous silicon film having a surface roughness of 10 nm or less, which is a feature of the present invention, is formed. The surface roughness here is
It means the center line average roughness Ra described in JIS-B0601.

Next, in step (3) of claim 7, the n ⁺ a-Si film 105 serving as an ohmic contact layer is formed in a thickness of approximately 3 mm.
Coat continuously with a film thickness of 〜１０10 nm. This n ⁺ a-S
The conditions for forming the i-film are as follows: silane flow rate 40 to 70 scc
m, hydrogen-based 0.5% phosphine mixed gas flow rate of about 200 to 350 sccm, film formation chamber pressure of 100 to 1
About 20 Pa, high frequency power density 0.01 to 0.02 W /
The standard is about ² cm ² and the substrate temperature is about 260 to 310 ° C. Thus, it is particularly necessary to keep the high-frequency power density low. Under these conditions, an n ⁺ amorphous silicon film having a thickness of 10 nm or less, which is a feature of the present invention, is formed. The n ⁺ lower limit of the amorphous silicon film thickness, it is necessary that the n ⁺ amorphous silicon film is 3nm or more is the degree to which it can be confirmed that is clearly formed. As the n-type impurity, phosphorus is preferable, but arsenic and antimony can be used in addition to phosphorus. (FIG. 10 (a)) Next, in step (4) of claim 7, the n ⁺ a-Si film and the a-Si film are patterned into an island shape by photolithography, etching, and stripping, thereby forming an island-shaped ohmic contact. Forming a layer and an intrinsic amorphous silicon semiconductor layer. (End of FIG. 10
(B)) the n ⁺ a-Si film 105 in the step (5) of claim 7;
Al, Mo, Cr and the like are coated on the upper surface by a sputtering method or the like so as to have a thickness of about 0.1 to 0.4 μm. The source electrode 106 and the drain electrode 107 are formed by photolithography and etching. Thereafter, since the substrate that has gone through these steps is exposed to oxygen plasma, the resist is not yet stripped. (FIG. 10 (c)) In the step (6) of claim 7, the substrate having undergone the steps (1) to (5) is exposed to a plasma containing oxygen ions or oxygen radicals. At this time, the oxygen plasma processing conditions include an oxygen flow rate of about 30 sccm, a gas pressure of about 10 Pa, and a high-frequency power density of 0.05 to
The standard is about 0.40 W / cm ² and the processing time is about 2 to 5 minutes. (FIG. 10 (d)) FIG. 5 shows the relationship between the plasma processing time and the plasma oxide film thickness (the thickness of the insulating modified layer). Oxidation reforming occurs when a substrate having an n ⁺ type amorphous silicon layer is placed on the anode side of the parallel plate type plasma processing apparatus (（in FIG. 5) and when it is placed on the cathode side (● in FIG. 5). The thicknesses of the layers formed differ greatly. When installed on the anode side, the oxide film thickness is about 3 n even if the processing time is extended.
m and does not increase. In such a case, normal on / off characteristics cannot be obtained. On the other hand, when it is installed on the cathode side, if the processing time is lengthened, the oxide film thickness increases and reaches 11 nm in 5 minutes. Thus, it can be seen that the insulation reforming treatment by the plasma cathode oxidation method is effective for forming the insulation reforming layer. In addition, it has been confirmed that a bias-applied plasma anodic oxidation method in which a processing substrate is placed on an anode electrode to which a + bias voltage has been applied and plasma is applied is also effective in forming an insulating modified layer having a thickness of 10 nm or more. . The oxygen plasma processing conditions in this method include:
Bias voltage 1 kV, oxygen flow rate 1600 sccm,
Gas pressure about 27Pa, high frequency power density 1-3W / cm
^The standard is about ² and the processing time is about 3 minutes.

As the plasma processing apparatus, a parallel plate type was used, and the substrate was set on the cathode electrode in the plasma processing apparatus. Under this condition, the self-bias voltage was -600.
The treatment is performed using the plasma cathode oxidation method under the condition of -100V. By exposing the substrate to oxygen plasma under such conditions, the n ⁺ amorphous silicon layer at the portion where the island-like intrinsic amorphous silicon semiconductor layer and the source / drain electrodes do not overlap is subjected to insulation reforming. You. This portion is referred to as an insulating modified layer 108. This results in a thin film transistor that is turned on and off by the gate voltage.

Next, the resist is stripped. The source-drain electrodes were not oxidized because the resist was coated on the source-drain electrodes during the oxidizing plasma treatment.

FIG. 1 shows a thin film transistor device manufactured by the above steps. On a transparent insulating substrate 1, a gate electrode 2, a gate insulating film 3, an intrinsic amorphous silicon film 4, n ⁺
The amorphous silicon film 5, the source electrode 6, the drain electrode 7,
The thin film transistor is composed of the insulation reforming layer 8 and has this structure to be turned on and off by a gate voltage.

As another embodiment of the process shown in FIG. 10, in the process shown in FIG. 10C, the plasma processing shown in FIG. 10D is performed with the pixel electrode further provided on the source / drain electrodes. You can also. The pixel electrode can be formed by coating a transparent conductive metal oxide film typified by indium tin oxide with a thickness of about 0.03 to 0.1 μm using a sputtering method or the like. The portion subjected to the plasma treatment is a portion where the source / drain electrode and the intrinsic amorphous silicon film do not overlap, or a portion where the pixel electrode and the intrinsic amorphous silicon film do not overlap. For such a structure,
An active matrix substrate can be used by coating a silicon nitride film as a passivation film on the pixel electrode to a thickness of 50 to 300 nm by a plasma CVD method.

Also, unlike FIG. 10, after the island processing. Plasma treatment is also possible. That is, in the step of FIG. 10, the source electrode and the drain electrode were formed after the n ⁺ a-Si film and the a-Si film were patterned into an island shape, but after the source and drain electrodes were formed, the n ⁺ a- It is also possible to process the Si film and the a-Si film into an island shape. FIG. 11 shows a schematic view of the process in such a case. FIG. 11 (a) corresponds to claim 9 (1) to (3), FIG. 11 (b) corresponds to claim 9 (4), and FIG. 11 (c) corresponds to claim 9 FIG. 11 (d) corresponds to (9) of (9) in FIG.
After forming the drain electrode, the n ⁺ a-Si film and the a-Si
It is a process schematic diagram of a thin-film transistor explaining one embodiment when processing a film into an island shape.

Steps (1) to (3) of the ninth aspect show the steps from the formation of the gate electrode to the formation of the n ⁺ a-Si film. 1
01, a gate electrode 102, a gate insulating layer 103, and n ⁺
a-Si film (intrinsic amorphous silicon film) 104, n ⁺ a-
An Si film (n ⁺ amorphous silicon film) 105 is formed.
(FIG. 11A) Next, in the step (4) of claim 9,
Source / drain electrodes are provided on the n ⁺ a-Si film 105. The source electrode 106 and the drain electrode 107 are formed by photolithography and etching. Thereafter, since the substrate that has gone through these steps is exposed to oxygen plasma, the resist is not yet stripped. (FIG. 11B) Next, in step (5) of claim 9, n ⁺ a
-Insulating the Si film 105 to form an insulating modified layer 108. (FIG. 11 (c)) Next, (6) of claim 9
In the process, the a-Si film (intrinsic amorphous silicon film) 104 and the insulating layer 108 are removed by photolithography and etching to obtain a desired island shape. (FIG. 11D) The film formation conditions and the like used in the above steps can be performed in exactly the same manner as in FIG.

A silicon nitride film is formed as a passivation film on the thin film transistor element substrate manufactured by the process of FIG. 10 or FIG.
It may be coated with a thickness of 00 nm.

Further, in order to form an active matrix substrate of the liquid crystal display shown in FIG. 7, a contact hole is formed in the passivation film 9 and the gate insulating layer 3 to form a conductive transparent metal oxide film (for example, indium tin oxide). And the pixel electrode 1 connected to the drain electrode 7
0 and the gate electrode terminal 11 may be formed. The resist was coated during the plasma oxidation, and the surface of the drain electrode could not be oxidized. Therefore, the drain electrode and the pixel electrode could be well contacted with low resistance.

[0038]

As described above, the portion of the n ⁺ -type amorphous silicon film where the intrinsic amorphous silicon film and the source / drain electrodes do not overlap is modified by plasma treatment to make it insulating. The surface of the amorphous silicon film (back channel interface) is not directly exposed to plasma or the like and is not damaged, and the surface roughness of the intrinsic amorphous silicon semiconductor layer is controlled to 10 nm or less. By controlling the thickness of the n ⁺ -type amorphous silicon layer to 10 nm or less, good on / off characteristics of the thin film transistor can be obtained.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of an inverted staggered thin film transistor element according to an embodiment of the present invention.

FIG. 2 shows a change in on-state current when the surface roughness of the intrinsic amorphous silicon semiconductor layer is changed when the film thickness of the n ⁺ type amorphous silicon layer is 5 nm.

FIG. 3 shows that the intrinsic silicon semiconductor layer has a surface roughness of 10 nm.
It is a comparison of the on-current when the thickness of the n ⁺ type amorphous silicon layer is changed between (●) and 20 nm (（).

FIG. 4 shows the off-state current when the film thickness of the n ⁺ -type amorphous silicon layer is changed when the plasma oxidation treatment time is 5 minutes.

FIG. 5 is a comparison of the change in the thickness of the plasma oxidation treatment of the n ⁺ -type amorphous silicon layer when the treatment time is varied in the case of cathodic oxidation (●) and anodization (○).

FIG. 6 shows a change in the plasma oxide film thickness of the n ⁺ -type amorphous silicon layer when a positive bias voltage is applied to the anode electrode to change the thickness in the anodic oxidation.

FIG. 7 is a schematic sectional view of one pixel portion of an active matrix substrate of a liquid crystal display using an inverted staggered thin film transistor according to one embodiment of the present invention.

FIG. 8 is a schematic sectional view of one pixel portion of an active matrix substrate of a liquid crystal display using an inverted staggered thin film transistor according to one embodiment of the present invention.

FIG. 9 is a cross-sectional view of an inverted staggered thin film transistor element generally used as a switching element of a pixel of a liquid crystal display.

FIG. 10 is a process schematic diagram of a thin film transistor for explaining an embodiment of the present invention.

FIG. 11 is a process schematic view of a thin film transistor for explaining an embodiment of the present invention.

[Explanation of symbols]

REFERENCE SIGNS LIST 1 transparent insulating substrate 2 gate electrode 3 gate insulating layer 4 intrinsic amorphous silicon semiconductor layer 5 n ⁺ amorphous silicon semiconductor layer (ohmic contact layer) 6 source electrode 7 drain electrode 8 insulation modification layer 9 passivation film 10 pixel Electrode 11 Gate electrode terminal 101 Transparent insulating substrate 102 Gate electrode 103 Silicon nitride film 104 Intrinsic a-Si film (intrinsic amorphous silicon film) 105 n ⁺ a-Si film (n ⁺ amorphous silicon film) 106 Source electrode 107 Drain electrode 108 Insulation modification layer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5F110 AA05 CC03 CC07 EE03 EE04 EE44 FF03 FF30 GG02 GG15 GG25 GG35 GG45 HK09 HK16 HK25 HL03 HL04 HL23 NN23 NN24 NN38 QQ03

Claims (14)

[Claims] 1. A gate electrode, a gate insulating film, an island-like intrinsic amorphous silicon film, a source / drain electrode, and the island-like intrinsic amorphous silicon film and a source / drain electrode on at least a transparent insulating substrate. Is an inverted staggered thin film transistor having an n ⁺ -type amorphous silicon film formed as an intermediate layer in an overlapping portion, wherein an intrinsic amorphous silicon film having a surface roughness of 10 nm or less is formed on the gate insulating film. Then, an n ⁺ -type amorphous silicon film having a thickness of 3 nm or more and 10 nm or less is formed on the intrinsic amorphous silicon film, and then both the intrinsic amorphous silicon film and the n ⁺ -type amorphous silicon film are formed. Is processed into an island shape, and then a source / drain electrode is formed on the n ⁺ -type amorphous silicon film, and then a plasma process is performed.
A thin film transistor element comprising: an insulating modified layer in which a portion of the n ⁺ -type amorphous silicon film where the intrinsic amorphous silicon film and the source / drain electrodes do not overlap is insulated. 2. A gate electrode, a gate insulating film, an island-like intrinsic amorphous silicon film, a source / drain electrode, and the island-like intrinsic amorphous silicon film and a source / drain electrode on at least a transparent insulating substrate. Is an inverted staggered thin film transistor having an n ⁺ -type amorphous silicon film formed as an intermediate layer in an overlapping portion, wherein an intrinsic amorphous silicon film having a surface roughness of 10 nm or less is formed on the gate insulating film. Then, an n ⁺ -type amorphous silicon film having a thickness of 3 nm or more and 10 nm or less is formed on the intrinsic amorphous silicon film, and then both the intrinsic amorphous silicon film and the n ⁺ -type amorphous silicon film are formed. processed into an island shape, and then on the n ⁺ -type amorphous silicon film to form source and drain electrodes, and then the pixel electrode on the source and drain electrodes After forming, by plasma treatment, in the n ⁺ -type amorphous silicon film, a Either bets do not overlap portion between said vacuum amorphous silicon film and the source and drain electrodes or the pixel electrode and insulated A thin film transistor element provided with an insulation reforming layer. 3. A gate electrode, a gate insulating film, an island-like amorphous silicon film,
An inverted staggered thin film transistor element having a source / drain electrode and an n ⁺ -type amorphous silicon film formed as an intermediate layer in a portion where the island-like intrinsic amorphous silicon film overlaps the source / drain electrode. Forming an intrinsic amorphous silicon film having a surface roughness of 10 nm or less on the gate insulating film, and forming an n ⁺ -type amorphous silicon film having a thickness of 3 nm or more and 10 nm or less on the intrinsic amorphous silicon film; Then, a source / drain electrode is formed on the n ⁺ type amorphous silicon film, and the intrinsic amorphous silicon film of the n ⁺ type amorphous silicon film and the source / drain electrode are formed by plasma treatment. After insulating the non-overlapping portion to provide an insulation reforming layer, both the intrinsic amorphous silicon film and the insulation reforming layer are processed into an island shape. Thin film transistor element. 4. The thin film transistor device according to claim 1, wherein the thickness of the insulation reforming layer is larger than the thickness of the n ⁺ type amorphous silicon film. 5. The thin film transistor element according to claim 1, wherein said insulation reforming layer is an oxide film. 6. The thin film transistor element according to claim 5, wherein said oxide film is formed by a plasma cathode oxidation method or a bias-applied plasma anodic oxidation method in the presence of oxygen ions or oxygen radicals. 7. At least (1) a step of sequentially forming a gate electrode and a gate insulating film on a transparent insulating substrate, and (2) a plasma CVD method in which a high-frequency power density to be applied is suppressed low on the gate insulating film. The surface roughness is 10n
m, a step of forming an intrinsic amorphous silicon film having a thickness of 3 n or less on the intrinsic amorphous silicon film by a plasma CVD method with a low applied high frequency power density.
forming an n ⁺ -type amorphous silicon film having a thickness of not less than m and not more than 10 nm; (4) patterning both the intrinsic amorphous silicon film and the n ⁺ -type amorphous silicon film into a desired island shape; (5) forming a source / drain electrode metal on the n ⁺ -type amorphous silicon film and patterning it to form a source / drain electrode; (6) forming a substrate on which the source / drain electrode is formed by oxygen Exposure in a plasma containing ions or oxygen radicals to form an insulating reformed layer in which a portion of the n ⁺ -type amorphous silicon film where the intrinsic amorphous silicon film and the source / drain electrodes do not overlap with each other is insulated. And a forming step are sequentially performed. 8. At least (1) a step of sequentially forming a gate electrode and a gate insulating film on a transparent insulating substrate, and (2) a plasma CVD method in which a high-frequency power density applied on the gate insulating film is suppressed low. The surface roughness is 10n
m, a step of forming an intrinsic amorphous silicon film having a thickness of 3 n or less on the intrinsic amorphous silicon film by a plasma CVD method with a low applied high frequency power density.
forming an n ⁺ -type amorphous silicon film having a thickness of not less than m and not more than 10 nm; (4) patterning both the intrinsic amorphous silicon film and the n ⁺ -type amorphous silicon film into a desired island shape; (5) forming a source / drain electrode metal and a pixel electrode metal on the n ⁺ type amorphous silicon film and patterning them to form both a source / drain electrode and a pixel electrode; The substrate on which the drain electrode and the pixel electrode are formed is exposed to plasma containing oxygen ions or oxygen radicals, and the intrinsic amorphous silicon film and the source / drain electrode or the pixel electrode in the n ⁺ -type amorphous silicon film Forming an insulation-modified layer in which a portion that does not overlap with either one of them is insulated. 9. At least (1) a step of sequentially forming a gate electrode and a gate insulating film on a transparent insulating substrate; and (2) a plasma CVD method in which a high-frequency power density applied on the gate insulating film is kept low. The surface roughness is 10n
m, a step of forming an intrinsic amorphous silicon film having a thickness of 3 n or less on the intrinsic amorphous silicon film by a plasma CVD method with a low applied high frequency power density.
forming an n ⁺ -type amorphous silicon film having a thickness of not less than m and not more than 10 nm; (4) forming a source-drain electrode metal on the n ⁺ -type amorphous silicon film and patterning to form a source-drain electrode (5) exposing the substrate, on which the source / drain electrodes are formed, to plasma containing oxygen ions or oxygen radicals, and in the n ⁺ -type amorphous silicon film, the intrinsic amorphous silicon film and the source A step of forming an insulating modified layer in which a portion not overlapping with the drain electrode is insulated; (6) forming the insulating modified layer, the intrinsic amorphous silicon film and the n ⁺ -type amorphous silicon film in a desired manner; And a step of patterning in an island shape. 10. The method according to claim 7, wherein the high frequency power density in the step (2) is in a range of 0.015 to 0.025 W / cm ^2. Method. 11. The method according to claim 7, wherein the high frequency power density in the step (3) is in the range of 0.01 to 0.02 W / cm ^2. Method. 12. The plasma CV in the step (2)
The film forming condition of the method D is set as follows.
m, hydrogen flow rate 700-1000 sccm, film formation pressure 1
The method according to claim 10, wherein the method is performed at a temperature of 00 to 120 Pa and a substrate temperature of 260 to 310 ° C. 11. 13. The plasma CV in the step (3)
The film forming conditions of the method D are set as follows: a silane flow rate of 40 to 70 sccm;
Flow rate of hydrogen containing 0.5% phosphine 200-
The method according to claim 11, wherein the method is performed at 350 sccm, a film forming pressure of 100 to 120 Pa, and a substrate temperature of 260 to 310 ° C. 13. 14. The plasma CV in the step (2)
The film forming condition of the method D is set as follows.
m, hydrogen flow rate 700-1000 sccm, film formation pressure 1
00 to 120 Pa, high frequency power density 0.015 to 0.0
The deposition was performed at 25 W / cm ^{2 at} a substrate temperature of 260 to 310 ° C. and the plasma CVD method in the step (3) was performed under the following conditions: ~ 350sc
cm, film formation pressure of 100 to 120 Pa, high frequency power density of 0.01 to 0.02 W / cm ² , substrate temperature of 260 to
The method according to claim 7, wherein the method is performed at 310 ° C.