JPH09139508A - Manufacture of thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a transistor wherein flatness can be improved by relieving unevenness by forming an element in a recessed part of a substrate. SOLUTION: A recessed part is formed on a substratum insulating film 12 of a glass substrate 50 or the glass substrate itself. A gate electrode 13 is formed in the recessed part by using self alignment, a gate insulating film 15 is spread on the gate electrode 13, and a part except the recessed part is eliminated by etch back. A channel part 17 and a channel stopper are formed on the gate insulating film 15 by using self alignment, and a sorce.drain part 20 which is in contact with a side wall of the channel part 17 is formed by using self alignment.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor used as, for example, a switching element of an active matrix type display device. More specifically, the substrate is provided with a concave portion for element formation, and the thin film transistor is provided in the concave portion. The present invention relates to a method of manufacturing a thin film transistor which is planarized by forming the thin film transistor.

[0002]

2. Description of the Related Art Conventionally, in an active matrix type display device using a display material such as liquid crystal, a thin film transistor is used as a switching element of each pixel. Such a thin film transistor is described in, for example, JP-A-63-224258.

This type of thin film transistor is schematically shown in FIG.
It is manufactured by the procedure shown in FIG. That is, first, a gate electrode having a predetermined shape is formed on a glass substrate (a). Then, a gate insulating film is formed by CVD (chemical vapor deposition) (b), and a channel portion is formed on the gate electrode and the gate insulating film (c). Next, a channel stopper portion is formed on this channel portion by plasma CVD (d). The channel stopper portion serves as an etching stopper during the subsequent source / drain processing.
Then, the channel portion is etched into a predetermined shape (e), source / drain portions having a predetermined shape are formed thereon (f), and source / drain electrodes having a predetermined shape are further formed thereon (g). . When the source / drain portions and the source / drain electrodes are etched into a predetermined shape, the channel stopper portions prevent the channel portions from being etched.

The thin film transistor thus manufactured is
It has the structure shown in FIG. That is, the gate electrode 51 having a predetermined shape is arranged on a part of the transparent glass substrate 50, and the gate electrode 51 is covered with the gate insulating film 52. Then, a channel portion 53 is formed on the gate insulating film 52, and the channel portion 53 protrudes on both sides of the gate electrode 51 by a predetermined dimension (S ₃ ).
A channel stopper portion 54, which is slightly smaller than the gate electrode 51, is provided on the channel portion 53. Then, a portion of the channel portion 53 which is not covered by the channel stopper portion 54, a predetermined dimension (S ₂ ) portion at both ends of the channel stopper portion 54, and a predetermined dimension (S ₁ ) portion outside the channel portion 53 are covered. Source / drain portions 55 are formed. And the source / drain electrode 56 on it
Is provided. The element height T of the thin film transistor as a whole reaches about 1 μm.

[0005]

As described above, according to the conventional method for manufacturing a thin film transistor, the thin film transistor is manufactured by sequentially laminating each layer on the glass substrate 50, and thus the completed thin film transistor has a large element height T and the thin film transistor is thin. There are severe irregularities in the areas with and without.
Therefore, when used in a liquid crystal display device or the like, the gap with the counter electrode fluctuates by the element height T, so that the accuracy of the gap adjustment is low, and there is a problem that the counter electrode is likely to be improperly attached. There is.

The present invention has been made in order to solve such a problem, and a concave portion for element formation is provided in a substrate to form at least a part of a thin film transistor therein, thereby alleviating irregularities. Accordingly, it is an object of the present invention to provide a method for manufacturing a thin film transistor capable of improving flatness, thereby facilitating adjustment of a gap between the thin film transistor and a counter electrode.

[0007]

In order to achieve this object, a method of manufacturing a thin film transistor according to the invention of claim 1 is
A recess forming step of forming a recess having at least the depth of the gate electrode in the substrate; a gate structure forming step of forming a gate electrode and a gate insulating film covering the gate electrode; and a channel portion, a source portion, and a drain on the gate insulating film. A channel structure forming step of forming a portion, and at least the gate electrode is formed in the recess.

According to this manufacturing method, the recess is formed in the substrate in the recess forming step. By forming at least the gate electrode in the thin film transistor, the concave portion is intended to reduce unevenness between a portion where the thin film transistor is provided and a portion where the thin film transistor is not provided. Then, a gate electrode is formed in the recess by the gate structure forming step and is covered with the gate insulating film. Then, a channel portion, a source portion, and a drain portion are formed on the gate insulating film by the channel structure forming step, and a thin film transistor is manufactured. In the thin film transistor thus manufactured, at least the gate electrode is located in the concave portion, and the concave and convex portions are relaxed by the depth of the concave portion.

The invention according to claim 2 is the method of manufacturing a thin film transistor according to claim 1, wherein in the step of forming the gate structure, a gate electrode film is formed, and a full-surface resist layer is formed thereon. It is characterized in that the gate electrode film is processed by etchback to form a gate electrode.

According to the gate electrode forming step of this manufacturing method, the gate electrode film is formed after forming the recess. The gate electrode film covers the substrate inside and outside the recess, and has an uneven shape corresponding to the recess of the substrate. Then, a resist layer is formed on the entire surface of this gate electrode film. The resist layer also has an uneven shape corresponding to the unevenness of the substrate and the gate electrode film, but since the resist is a liquid at the time of coating, the unevenness thereof is smaller than the unevenness of the substrate and the gate electrode film. That is, the resist layer inside the recess becomes thicker than the resist layer outside the recess. Then, when etching back is performed until the resist layer and the gate electrode film disappear outside the recess, the gate electrode film remains in the recess where the resist layer is thick. This is used as a gate electrode. Therefore, the gate electrode is positioned and processed by self-alignment by the concave portion formed in the substrate, and a photomask for forming the gate electrode is not required.

As a modified example of the invention according to claim 1,
(1) “Concave forming step of forming a concave portion having a depth of at least a gate electrode and a gate insulating film on a substrate; a gate structure forming step of forming a gate electrode and a gate insulating film covering the concave portion in the concave portion; And a channel structure forming step of forming a channel portion, a source portion, and a drain portion on the gate insulating film. "

According to this manufacturing method, after the recess is formed in the substrate by the recess forming step, the gate electrode and the gate insulating film are formed in the recess by the gate structure forming step, and the gate electrode is covered with the gate insulating film. . After that, a channel portion, a source portion, and a drain portion are formed on the insulating film by a channel structure forming step, and a thin film transistor is manufactured. In the thin film transistor thus manufactured, at least the gate electrode and the gate insulating film are located in the concave portion, and the concave and convex are reduced by the depth of the concave portion.

In the step (1) of forming the gate structure of the manufacturing method, a gate insulating film may be formed in the recess to cover the gate electrode by the same procedure as in forming the gate electrode of the manufacturing method of claim 2. it can. That is, “after forming a gate electrode in the recess, a gate insulating film is formed to cover the gate electrode, a full-surface resist layer is formed thereon, and the gate insulating film is processed by etching back to form the recess. The gate insulating film is left only inside. "

In this case, when the gate insulating film is formed,
The gate insulating film extends inside and outside the concave portion, covers the gate electrode inside the concave portion, and covers the substrate outside the concave portion.
Therefore, it has an uneven shape corresponding to the concave portion of the substrate. Then, a resist layer is formed on the entire surface of this gate insulating film. The resist layer also has an uneven shape corresponding to the unevenness of the substrate and the gate insulating film, but since the resist is a liquid at the time of application, the unevenness is smaller than that of the gate insulating film. That is, the resist layer inside the recess becomes thicker than the resist layer outside the recess. Then, when etching back is performed until the resist layer and the gate insulating film disappear outside the recess, the gate insulating film remains in the recess where the resist layer is thick, and the gate electrode remains covered with the gate insulating film. Therefore,
The gate insulating film is positioned and processed by self-alignment by the recess formed in the substrate, and a photomask for processing the gate insulating film is not required.

In the gate structure forming step of the manufacturing method of (1), both the gate electrode formation and the gate insulating film formation can be performed in the same procedure as the gate electrode formation of the manufacturing method according to the second aspect. That is, "a gate electrode film is formed, a resist layer is formed on the entire surface, and the gate electrode film is processed by etchback to form a gate electrode,
A gate insulating film is formed to cover the gate electrode, a resist layer is entirely formed on the gate insulating film, and the gate insulating film is processed by etching back to leave the gate insulating film only in the recess. "

In this case, the positioning and processing of the gate electrode and the positioning and processing of the gate insulating film are both self-aligned by the recess formed in the substrate, and a photomask for the gate structure forming step is not required. .

Further, as a further modified example of the manufacturing method of (1), (2) "a recess forming step of forming a recess having at least a depth of a gate electrode, a gate insulating film, and a channel portion in a substrate; The step of forming a channel structure includes a step of forming a gate electrode and a gate insulating film covering the gate electrode in the recess, and a step of forming a channel structure, a source part and a drain part on the gate insulating film. There is a method of manufacturing a thin film transistor, wherein at least the channel portion is formed in the recess among those formed in the process. "

According to this manufacturing method, in addition to the gate electrode and the gate insulating film, the channel portion is also formed in the concave portion of the substrate. Therefore, in the manufactured thin film transistor, at least the gate electrode, the gate insulating film, and the channel portion are located in the concave portion, and the irregularity is reduced by the depth of the concave portion.

Further, in the step (2) of forming a channel structure in the invention, "a channel film is formed, a channel stopper film is formed thereon, and a full-scale resist layer is formed thereon, and then an etchback is performed. The channel stopper film may be processed to form a channel stopper, and the channel film may be processed to form a channel portion by etching, and a source portion and a drain portion in contact with a sidewall of the channel portion can be formed. "

In this case, when the channel film is formed, the channel film extends inside and outside the concave portion, covers the gate insulating film inside the concave portion, and covers the substrate outside the concave portion. Therefore, it has an uneven shape corresponding to the concave portion of the substrate. Then, when the channel stopper film is formed thereon, the channel stopper film covers the channel film inside and outside the recess. Therefore, it has an uneven shape corresponding to the concave portion of the channel film. Then, a resist layer is formed on the entire surface of this channel stopper film. The resist layer also has an uneven shape corresponding to the unevenness of the channel stopper film, but since the resist is a liquid at the time of coating, the unevenness is smaller than the unevenness of the channel stopper film. That is, the resist layer inside the recess becomes thicker than the resist layer outside the recess. Then, if etching back is performed under the condition that the channel film is not etched until the resist layer and the channel stopper film disappear outside the concave portion, the channel stopper film remains in the concave portion where the resist layer is thick and becomes a channel stopper. Therefore,
The channel stopper is positioned and processed by self-alignment by the recess formed in the substrate, and a photomask for forming the channel stopper is not required.

When etching is performed under the condition that the channel film is etched and the channel stopper is not etched, the channel stopper acts as a mask, so that the portion of the channel film which is not covered by the channel stopper is removed and covered by the channel stopper. The part that has been broken away becomes the remaining channel part. As a result, a laminate of the channel portion and the channel stopper is formed in the recess, and both side walls of the channel portion are exposed. Therefore, the channel stopper is self-aligned to position and process the channel portion, and a photomask for forming the channel portion is not required. Then, a source part and a drain part which are in contact with both side walls of the channel part are formed. In the thin film transistor thus manufactured, the channel portion is in contact with the source portion and the drain portion at the side wall of the channel portion.

In the recess forming step in each of the above-mentioned manufacturing methods, the surface of the substrate itself, such as a glass substrate, may be processed to form the recess, or the recess may be formed on the surface of the substrate. May be formed and the recess may be formed by processing this layer.

[0023]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the present embodiment,
To be used as a switching element of a liquid crystal display device, a large number of thin film transistors are manufactured on a transparent glass substrate,
Arrange them in a matrix. However, for convenience, only one thin film transistor is shown in the drawing.

In this embodiment, a thin film transistor is manufactured by the schematic procedure shown in FIG. That is, first, a concave portion, which is a thin film transistor formation location, is formed on a substrate (S1),
Then, a gate electrode is formed in the recess (S2), a gate insulating film is formed to cover the gate electrode (S3), a channel film is formed on the gate insulating film (S4), and a channel is formed on the channel film. A stopper is formed (S5), the channel film is processed using the channel stopper as a mask to form a channel portion (S6), and source / drain portions are formed (S5).
7), source / drain electrodes are formed (S8). Hereinafter, detailed description will be given by showing structural cross-sectional views in each step.

First, the formation of the recess (S1 in FIG. 9) will be described. The glass substrate is thoroughly washed to form a base insulating film on its surface, and the base insulating film is processed by photolithography and etching to partially remove it over the entire thickness, and the removed portion is made into a recess. This state is shown in FIG. According to FIG. 1, the glass substrate 50 is provided at the location of the recess 11.
Are exposed, and the base insulating film 12 covers the glass substrate 50 at other portions.

Here, the base insulating film 12 is formed by
800 nm thick silicon oxide (S
iO ₂ ) film is formed. Then, etching after forming the resist mask by photolithography is performed by tetrafluoromethane (CF ₄ ) -3 fluoromethane (C
HF ₃ ) Ion etching is performed from above with a mixed gas. This etching is performed until the underlying insulating film 12 at the portion without the resist mask disappears, and the resist mask is removed, resulting in the state shown in FIG. Therefore, the depth D of the recess 11 is equal to the film thickness of the base insulating film 12 and is 8
00 nm. The width of the recess 11 is about 2 μm.

Next, formation of the gate electrode inside the recess 11 (S2 in FIG. 9) will be described with reference to FIG. First, a gate electrode film 13a of molybdenum (Mo), which is the material of the gate electrode, is formed on the entire surface by a sputtering method. The film thickness is 200 nm. At this time, as shown in FIG. 2A, not only the upper surface of the base insulating film 12 (hereinafter, referred to as “external”) but also the bottom surface (glass substrate 50) and side wall of the recess 11 are formed. Then, a photoresist having a thickness of 1 μm is applied onto the gate electrode film 13a, and the entire surface is exposed. Then, as shown in FIG. 2B, the gate electrode film 13
The entire a is covered with the resist mask 14. Surface tension acts because the photoresist is a liquid at the time of application,
A depression 14 of the resist mask 14 formed in the concave portion 11
The depth of a is smaller than the depth of the recess 11. Therefore, the thickness T ₂ of the resist mask 14 at the location of the recess 11 is
Is the thickness T ₁ (1 μm) of the resist mask 14 on the outside.
m) thicker. This resist mask 14 acts as an etch back resist in the subsequent etching process.

Then, from above, anisotropic etching is performed under the condition that the resist mask 14 and the gate electrode film 13a are corroded but the base insulating film 12 is not corroded. Specifically, ion etching is performed from above with a mixed gas of hydrogen bromide (HBr) and chlorine (Cl ₂ ). At this time, the outside is concave 1
Since the resist mask 14 is thicker than the inside of No. 1, the resist mask 14 remains inside the recess 11 even if the resist mask 14 disappears outside by etching (FIG. 2C). After that, if etching is continued inside the recess 11 until the resist mask 14 disappears, the gate electrode film 13a outside and on the upper end of the side wall disappears, and the gate electrode film 13a disappears as shown in FIG. It remains in the interior only.

Thus, by etching back, the gate electrode 13 is formed by self-alignment based on the shape of the recess 11 without using a photomask. In addition, the concave portion 1
If the gate electrode 13 has the shape shown in FIG. 2D before the resist mask 14 inside 1 disappears completely,
The etching is stopped at that point, and the remaining resist mask 14 is removed by ashing or the like.

In forming the gate electrode 13, the material of the gate electrode film 13a, that is, the material of the gate electrode 13 is not limited to molybdenum, and may be any conductive and conductive material such as aluminum ( A
l), tungsten (W), chromium (Cr), tantalum (Ta), iron (Fe), and other metals, high impurity concentration polycrystalline or amorphous silicon (Si), indium oxide-tin oxide (ITO) Can be mentioned. The film formation method is
Not only the sputtering method but also the CVD method can form a film by C
The film may be formed by the VD method. Further, as the etch back resist, an SOG film formed by a spin coater may be used instead of the photoresist resist mask 14. When other materials are used in this way, the etching conditions are also adapted accordingly.

Next, the formation of the gate insulating film on the gate electrode 13 (S3 in FIG. 9) will be described with reference to FIG.
First, silicon nitride (S
A thin film 15a of iN _x ) is formed by plasma CVD. The film thickness is 200 nm. At this time, as shown in FIG. 3A, the film is formed not only on the outside but also on the bottom surface (gate electrode 13) and side wall of the recess 11. Then, a photoresist is applied to the silicon nitride film 15a to a thickness of 1 μm, and the entire surface is exposed. Then, as shown in FIG.
The entire silicon nitride film 15a is covered with the resist mask 16. As in the case of the resist mask 14 (FIG. 2B), the thickness T of the resist mask 16 formed in the concave portion 11
₃ becomes thicker than the thickness T ₄ of the resist mask 16 on the outside. This resist mask 16 acts as an etch back resist in the subsequent etching process.

Then, anisotropic etching is performed from above under the condition that the resist mask 16 and the silicon nitride film 15a are corroded but the base insulating film 12 is not corroded. Specifically, CF
Ion etching is applied from above with ₄ gases. At this time, the resist mask 1 is more exposed outside than inside the recess 11.
Since 6 is thick, the resist mask 14 and the gate electrode 13
As in the case of the above etching, the resist mask 16 on the outside is first erased by the etching. After that, if etching is continued until the resist mask 16 inside the concave portion 11 disappears, the external silicon nitride film 15a is removed.
Disappear, and the silicon nitride film 15 is removed as shown in FIG.
a remains in only the inside of the recess 11 and is used as the gate insulating film 15.

Thus, by etching back, the gate insulating film 15 is formed by self-alignment based on the shape of the recess 11 without using a photomask.
3 is covered by this. The gate insulating film 15 is formed before the resist mask 16 inside the recess 11 is completely disappeared.
3C has the shape shown in FIG. 3C, the etching is stopped at that point, and the remaining resist mask 16 is removed by ashing or the like.

In forming the gate insulating film 15,
The material of the gate insulating film 15 may be any material other than silicon nitride, as long as it can be formed and etched, is a stable material having an insulating property, and is different from the base insulating film 12, and the film forming method is plasma CVD. Other CVD or sputtering method may be used. For example, polyimide or SOG film may be used. When a material other than silicon oxide is used as the base insulating film 12, silicon oxide may be used as the gate insulating film 15. Further, as the etch back resist, an SOG film may be used in place of the photoresist resist mask 16 except when the SOG film is used as the gate insulating film 15. When other materials are used in this way, the etching conditions are also adapted accordingly.

Next, formation of the channel portion on the gate insulating film 15 (S4 to S6 in FIG. 9) will be described with reference to FIG. First, a channel film 17a of amorphous silicon (Si), which is the material of the channel portion, is formed on the entire surface by low pressure CVD (S4 in FIG. 9). Then the channel film 17
A silicon nitride channel stopper film 18a is formed on the entire surface of a by plasma CVD. Both film thickness is 200 nm
And At this time, as shown in FIG. 4A, both the outside and the gate insulating film 15 are covered with the double layer of the channel film 17a and the channel stopper film 18a. Then, a photoresist of 1 μm is formed on the channel stopper film 18a.
The thickness is applied and the entire surface is exposed. Then, as shown in FIG. 4B, the entire channel stopper film 18 a is covered with the resist mask 19. Similar to the case of the resist masks 14 and 16 (FIGS. 2B and 3B), the thickness T ₅ of the resist mask 19 formed in the recess 11 is smaller than the thickness T ₆ of the resist mask 19 on the outside. Get thicker. This resist mask 19 acts as an etch back resist in the subsequent etching process.

Then, from above, anisotropic etching is performed under the condition that the resist mask 19 and the channel stopper film 18a are corroded but the channel film 17a is not corroded. Specifically, ion etching is performed from above with a mixed gas of tetrafluoromethane and trifluoromethane. At this time, since the resist mask 19 is thicker on the outside than on the inside of the recess 11, the resist mask 19 on the outside is removed by etching, as in the case of etching the resist mask 14, the gate electrode 13, the resist mask 16, and the gate insulating film 15.
Disappears first. After that, if etching is continued until the resist mask 19 inside the recess 11 disappears,
The external channel stopper film 18a disappears, and FIG.
As shown in FIG. 9, the channel stopper film 18a remains in the recess 11 only, and this is used as the channel stopper 18 (S5 in FIG. 9). If the channel stopper 18 has the shape shown in FIG. 4C before the resist mask 19 inside the recess 11 completely disappears, the etching is stopped at that point and the remaining resist mask 19 is ashed. Etc. to remove.

Then, a slight wet etching is performed to drop the edge portion of the channel stopper 18, and then the channel film 17a is corroded and the channel stopper 18, the gate insulating film 15, and the base insulating film 12 are not corroded. Perform anisotropic etching. Specifically, ion etching is performed from above with a hydrogen bromide-chlorine mixed gas. Then, only the portion of the channel film 17a covered by the channel stopper 18 remains, and the other portions disappear. Therefore, as shown in FIG. 4D, the channel portion 17 whose upper surface is covered by the channel stopper 18 is formed in the region of the recess 11. Thus, by etching back, the channel portion 17 is formed by self-alignment based on the shape of the recess 11 without using a photomask (S6 in FIG. 9). The surfaces of both side walls of the channel portion 17 are exposed.

In forming the channel portion 17, the material of the channel portion 17 may be polycrystalline silicon in addition to amorphous silicon. Further, if the concentration is low, impurities may be added. Further, the material of the channel stopper 18 may be, for example, silicon oxide other than silicon nitride as long as it functions as a protective film for the channel portion 17, and a sputtering method may be used instead of CVD as a film forming method. Further, as the etch back resist, an SOG film may be used instead of the photoresist resist mask 19. However, when using other materials like this,
Etching conditions are also adapted accordingly.

Next, the formation of the source / drain portions in contact with both side surfaces of the channel portion 17 (S7 in FIG. 9) will be described with reference to FIG.
This will be described below. First, a source / drain film 20a of polycrystalline silicon, which is the material of the source / drain portion, is formed on the entire surface by low pressure CVD. The film thickness is 200 nm. At this time, as shown in FIG. 5A, the underlying insulating film 12, the gate insulating film 15 in the recess 11, the sidewalls of the channel portion 17 and the channel stopper 18, and the upper surface of the channel stopper 18 are all the source / drain film 20a. Covered in. The formation of the source / drain film 20a proceeds not only upward on the upper surface of the base insulating film 12 and the channel stopper 18, but also laterally on the side walls of the channel portion 17 and the channel stopper 18. Therefore, the channel unit 1
7 and the film thickness T ₇ of the source / drain film 20a in the vicinity of the side wall of the channel stopper 18 in the vertical direction is T ₈ (200 nm) outside or on the channel stopper 18.
Much thicker.

Then, on the source / drain film 20a,
Impurity for introducing conductivity is introduced. This impurity is
A dopant that gives carriers (free electrons or holes) to silicon, such as phosphorus (P) and arsenic (As) as n-type (free electrons), boron (B) as p-type (holes), There is gallium (Ga) or the like. This impurity is introduced by ion implantation, vapor phase diffusion, solid phase diffusion, or the like. Alternatively, instead of being introduced after film formation, it may be contained during film formation.

From above, the source / drain film 20 is formed.
Anisotropic etching is performed under the condition that a is corroded and the underlying insulating film 12, the channel stopper 18, and the gate insulating film 15 are not corroded. Specifically, ion etching is performed from above with a hydrogen bromide-chlorine mixed gas. This etching is performed on the base insulating film 12 and the source on the channel stopper 18.
When the drain film 20a disappears and is stopped there, the source / drain film 20a is formed in the vicinity of both side walls of the vertically thick channel portion 17 and the channel stopper 18.
Remain (FIG. 5 (b)). The remaining portions are in contact with the sidewalls of the channel portion 17 and serve as the source / drain portions 20 and 20 of the thin film transistor. Thus, the source / source is self-aligned based on the shapes of the channel portion 17 and the channel stopper 18 without using a photomask.
The drain parts 20, 20 are formed.

In forming the source / drain portions 20 and 20, the material of the source / drain portions 20 and 20 is
In addition to polycrystalline silicon, amorphous silicon, titanium silicide (TiSi), tungsten silicide (WS)
i) or the like may be used. Further, the film forming method may be CVD or sputtering other than the low pressure CVD. However, when other materials are used as described above, the etching conditions are also adapted accordingly.

Next, a source / drain electrode which makes ohmic contact with the source / drain portions 20 and 20 is formed (S8 in FIG. 9). First, a thin film of aluminum, which is the material of the source / drain electrodes, is formed on the entire surface. Then, this thin film is processed by photolithography and etching so that the upper portions of the source / drain portions 20 and 20 are left, and the remaining portions are processed into the source / drain electrodes 2.
1 and 21. This state is shown in FIG.

Here, the aluminum thin film is formed by the sputtering method, and the film thickness is 800 nm. Then, the etching after forming the resist mask by photolithography corrodes the aluminum thin film, and the resist mask and the channel stopper 18 and the base insulating film 12 are etched.
Anisotropic etching is performed under conditions that do not corrode. Specifically, ion etching is performed from above with a hydrogen bromide-chlorine mixed gas. FIG. 6 shows a state in which this etching is performed until the aluminum thin film in the portion without the resist mask disappears, and the resist mask is removed.

In the formation of the source / drain electrodes 21 and 21, the material of the source / drain electrodes 21 and 21 may be any material other than aluminum, as long as it can be formed and etched and has conductivity. , Tungsten, chromium, tantalum, iron, ITO, etc. can be used. Further, the film forming method is not limited to the sputtering method, but C
A film that can be formed by the VD method may be formed by the CVD method.
When other materials are used in this way, the etching conditions are also adapted accordingly.

Next, a protective film is formed to cover the entire surface. The protective film is formed by plasma CVD using 1 μm of silicon nitride.
m film is formed. FIG. 7 shows a state in which the protective film 22 is formed. The material of this protective film may be silicon oxide, polyimide or the like in addition to silicon nitride, and the film formation method is plasma C
A CVD method other than VD or a sputtering method may be used. Alternatively, an SOG film formed by a spin coater may be used.

The thin film transistor thus manufactured is
As shown in FIG. 7, the gate electrode 13 and the gate insulating film 1
Channel part 17 insulated from the gate electrode 13 by 5
And source / drain portions 20 and 20 provided in contact with both the immediate walls of the channel portion 17, and these are arranged in the concave portion formed by the glass substrate 50 and the base insulating film 12. ing.

In this thin film transistor, the channel portion 1
7 has no impurities introduced or has a low impurity concentration of half
Source / drain part 2 because it is a conductor and has high resistance
Normal conduction between 0 and 20 is off. others
Source / drain electrodes 21, 21
No current flows even if a voltage is applied between the rain sections 20, 20.
No. However, the voltage V_g Is applied,
Due to the electric field effect, the carrier concentration of the channel portion 17 is increased.
Ascends and its resistance decreases. And the gate voltage V_g But
Predetermined threshold voltage V_thReaches the source / drain section 2
The conduction between 0 and 20 is turned on. In this state the source
The source / drain portion 2 is formed by the drain electrodes 21 and 21.
When a voltage is applied between 0 and 20, a current flows. That is,
Voltage V _g By controlling the source
The current between the drain parts 20, 20 can be controlled
You. Therefore, it is used as a switching element for liquid crystal display devices.
Can be used.

In this thin film transistor,
The source / drain portions 20 and 20 are formed by self-alignment based on the channel stopper 18 and the channel portion 17, so that the source / drain portions 20 and 20 are surely in contact with the side wall surface of the channel portion 17, Even if the source / drain portions 20 and 20 are small in size, the contact resistance between the channel portion 17 and the source / drain portions 20 and 20 is small. Further, since the gate electrode 13 is formed over the entire width in the recess and the channel portion 17 is formed in the center of the recess by self-alignment based on the base insulating film 12, the field effect of the gate voltage V _g extends over the entire channel portion 17. . Therefore, the channel resistance when turned on is small.

Next, a modification of the present embodiment will be described. In this modification, the base insulating film 1 is formed on the glass substrate 50.
It is characterized in that a recess is formed by directly etching without forming 2, and a thin film transistor is formed in this recess by the same procedure as described above. As a result, a thin film transistor having a structure as shown in FIG. 8 is obtained. In the case of FIG. 8, the glass substrate 50 itself has a recess formed therein and the thin film transistor is arranged therein, and the thin film transistor itself is no different from that of FIG. 7.

As described in detail above, according to the present embodiment and its modification, a recess is formed in the base insulating film 12 formed on the glass substrate 50 or the glass substrate 50 itself, and the recess is formed in this recess. Since the thin-film transistor is manufactured by laminating the respective constituent parts of the thin-film transistor, the vertical unevenness due to the thin-film transistor is alleviated by the depth of the concave portion, and the entire substrate is flattened. Therefore, when used in a liquid crystal display device, the gap between the counter electrode and the counter electrode can be adjusted with high accuracy, and the counter electrode is not attached incorrectly.

When the concave portion is formed, the gate electrode 13, the gate insulating film 15, the channel portion 17, and the channel stopper 18 are self-aligned based on the shape of the concave portion.
Processing is performed, and the source / drain portions 20 and 20 are processed by self-alignment based on the shapes of the channel portion 17 and the channel stopper 18. Therefore, the photomask is used for processing the concave portion and the source / drain electrode 2.
Only 2 sheets, 1 and 21 for processing are required. Therefore, the photo process is very simple and the process cost is low.

Further, since each layer of the thin film transistor is processed by self-alignment without using a photomask in this way, the contact between the channel portion 17 and the source / drain portions 20 and 20 can be surely made on the side wall of the channel portion 17. The channel portion 17 is formed at the center of the gate electrode 13. Therefore, it is not necessary to take an extra margin for superimposing the respective layers, and a thin film transistor having a size about 20% smaller than the conventional one can be manufactured.

Although the embodiments have been described above, the present invention is not limited to the embodiments and the modifications thereof, and it goes without saying that various design changes can be made without departing from the spirit of the present invention. There is no such thing.

For example, in the above-described embodiment, the depth of the recess is set to the gate electrode 13, the gate insulating film 15, the channel portion 1.
7, 800n, which is the total thickness of the channel stopper 18
Although the thin film transistor main body portion excluding the source / drain electrodes 21 and 21 is set to be within the depth of the recess, the depth of the recess is set to be m.
1, 21 may also be accommodated within the depth of the recess. In this case, the planarization, which is the main object of the present invention, is more thorough.
On the other hand, it is possible to make the recess shallow so that only a part of the thin film transistor (for example, only the gate electrode 13, only the gate electrode 13 and the gate insulating film 15) fits within the depth of the recess. Even in this case, a flatter product is produced as compared with the conventional production method in which no recess is formed.

The base insulating film 12 is formed on the glass substrate 50.
In the case of forming a concave portion in the concave portion by forming the concave portion 1 in the description of FIG.
However, the underlying insulating film 12 may be left in the recess 11 as well. Further, a quartz or sapphire substrate may be used instead of the glass substrate.

[0057]

As described above, according to the method of manufacturing a thin film transistor according to the present invention, since the substrate is provided with a concave portion for forming an element and at least a part of the thin film transistor is formed in the concave portion, unevenness is relaxed and flatness is improved. Can be improved,
The gap between the thin film transistor and the counter electrode can be easily adjusted.

[Brief description of the drawings]

FIG. 1 is a diagram showing a state in which a recess is formed in a base insulating film on a substrate.

FIG. 2 is a diagram illustrating formation of a gate electrode in a recess.

FIG. 3 is a diagram illustrating formation of a gate insulating film on a gate electrode.

FIG. 4 is a diagram illustrating formation of a channel portion on a gate insulating film.

FIG. 5 is a diagram illustrating formation of source / drain portions in contact with both side surfaces of a channel portion.

FIG. 6 is a diagram showing a state where source / drain electrodes are formed.

FIG. 7 is a diagram showing a state in which a protective film is formed.

FIG. 8 is a diagram showing a state where a recess is formed in the substrate itself to manufacture a thin film transistor.

FIG. 9 is a diagram showing a schematic procedure of a method of manufacturing the thin film transistor according to the embodiment.

FIG. 10 is a diagram showing a schematic procedure of a conventional method of manufacturing a thin film transistor.

FIG. 11 is a diagram showing a schematic configuration of a conventional thin film transistor.

[Explanation of symbols]

 Reference Signs List 11 recess 12 base insulating film 13 gate electrode 13a gate electrode film 14 whole surface resist layer 15 gate insulating film 17 channel part 20 source / drain part 50 substrate

Claims (2)

[Claims] 1. A method of manufacturing a thin film transistor, comprising: a step of forming a recess having a depth of at least a gate electrode in a substrate; a step of forming a gate electrode and a gate insulating film covering the recess; And a channel structure forming step of forming a channel portion, a source portion and a drain portion on an insulating film, wherein at least the gate electrode is formed in the recess. 2. The method of manufacturing a thin film transistor according to claim 1, wherein in the step of forming the gate structure, a gate electrode film is formed, a resist layer is entirely formed on the gate electrode film, and the gate electrode film is formed by etching back. A method of manufacturing a thin film transistor, which comprises processing to form a gate electrode.