JP4392471B2 - Field effect transistor and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a field effect transistor such as a high electron mobility transistor (hereinafter referred to as “HEMT”) used for a high frequency device or the like, and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, in order to obtain a semiconductor element that operates in a millimeter wave band (30 to 300 GHz) or a sub millimeter wave band (300 GHz to 3 THz), research on miniaturization of HEMT has been actively conducted. In particular, the HEMT in which an electron supply layer made of InAlAs and a channel layer made of InGaAs are lattice-matched on an InP substrate has a large energy gap of the conduction band of InAlAs and InGaAs of 0.53 eV, and the channel layer is made of InGaAs. It is considered promising because of its high electron mobility and saturation rate at room temperature, and is the main research target.
[0003]
In HEMTs made of these materials, attempts have been made to increase the mobility and saturation speed of electrons by increasing the In composition ratio of the channel layer to about 0.7. Until now, in HEMTs made of these materials, the gate length has been reduced to about 25 nm, and the distance between the gate electrode and the channel layer has been shortened to obtain a characteristic with a cutoff frequency of 500 GHz or more.
[0004]
Japanese Patent Laid-Open No. 2002-184786 discloses an asymmetric recess type HEMT in which the distance between the gate and the drain is made larger than the distance between the source and the gate in order to improve the withstand voltage between the source and the drain, and a method for manufacturing the same. Is described.
[0005]
[Patent Document 1]
JP 2002-184786 A
[0006]
[Problems to be solved by the invention]
However, it is difficult to further improve the high-frequency characteristics only by reducing the gate length, shortening the distance between the gate electrode and the channel layer, and changing the material composition. For example, a new MTMT having a cutoff frequency exceeding 1 THz is required. It is necessary to introduce a new concept. As one of them, it has been proposed to increase the electron moving speed by quantum thinning the channel to several tens of nm or less. However, a practical method for quantum thinning the channel has not been developed.
[0007]
In view of the above, an object of the present invention is to provide a field effect transistor having a quantum thinned channel.
[0008]
Another object of the present invention is to provide a method of manufacturing a field effect transistor that can relatively easily manufacture a field effect transistor having a quantum thinned channel.
[0009]
[Means for Solving the Problems]
  The above-described problems are formed on a compound semiconductor substrate, a channel layer, a carrier supply layer, an etching stopper layer, and a cap layer made of a compound semiconductor formed on the compound semiconductor substrate, and the cap layer. Removing the insulating film and the semiconductor from the opening provided in the insulating film to the etching stopper layer;, When viewed from above, wide and narrow parts are alternately continuous along a straight lineThe formed recess,Below the recessA depletion layer formed in the channel layer;In the narrow part of the recessA gate electrode Schottky connected to the etching stopper layer;A shot of the gate electrode is formed at a position sandwiching the depletion layer below the narrow portion of the recess and linearly defined by the depletion layer below the wide portion of the recess. A source and drain with a two-dimensional electron presence region extending towards the key connection,The field effect transistor is characterized in that the shape of the source and the drain is the same as the shape of the cap layer.
[0010]
  The above-described problems include a step of sequentially forming a channel layer, a carrier supply layer, an etching stopper layer, and a cap layer made of a compound semiconductor on a compound semiconductor substrate, a step of forming an insulating film on the cap layer, and the insulation A resist film forming step of forming a first photoresist film on the film;A plurality of first slits arranged in the vertical direction are formed in the first photoresist film, and at a position sandwiching the first slit from the vertical direction, the first slit is more longitudinal than the first slit. Forming one or a plurality of second slits having a small length in a wider range in the lateral direction than the first slit;Then, recess etching is performed from the upper surface of the insulating film to the etching stopper layer through the first slit and the second slit of the photoresist film.The portion having a small length in the horizontal direction and a portion having a large length in the horizontal direction are alternately connected in the vertical direction to the channel layer below and around the first and second slits. A step of forming a depletion layer, and depositing metal on the wall surface of the second slit in a state where the substrate is tilted with respect to the direction in which the metal atoms fly, and then closing the second slit. Arranged perpendicular to the direction in which the metal atoms flyThis is solved by a method of manufacturing a field effect transistor, comprising: a gate electrode forming step of depositing only metal atoms passing through the first slit on the etching stopper layer to form a gate electrode.
[0011]
In the present invention, a channel layer, a carrier supply layer, an etching stopper layer, and a cap layer made of a compound semiconductor are formed on a compound semiconductor substrate. In such a laminated structure, two-dimensional electrons (2 DEG: 2 Dimensional Electron Gas) are generated above the channel layer. Thereafter, when the semiconductor above the etching stopper layer is removed by etching, the two-dimensional electrons below the part from which the semiconductor has been removed disappears to form a depletion layer, and both sides of the depletion layer are regions where two-dimensional electrons exist, That is, it becomes a source / drain.
[0012]
  In this case, a slit is not formed on both sides of the first slit in the source / drain direction, but a second slit is formed in a direction intersecting the source / drain direction, thereby forming a linear two-dimensional shape on the source / drain. An electron presence region can be provided.Gate electrodeWhen a predetermined voltage is applied between the source and the drain, a quantum thinned channel is formed between these two-dimensional electron existence regions.
[0013]
As described above, in the present invention, a linear two-dimensional electron existence region can be formed without etching the channel layer, and a field effect transistor having excellent high frequency characteristics can be manufactured relatively easily. it can. In the present invention, the gate electrode is formed using the slit of the resist film used for forming the recess. Thereby, a manufacturing process is simplified.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[0015]
In general, in the HEMT, a cap layer made of an n-type semiconductor is used to obtain an ohmic junction with a source electrode and a drain electrode. The n-type semiconductor cap layer is removed from the Schottky junction portion of the gate electrode. A portion from which the n-type semiconductor cap layer is removed is called a recess. In the present invention, the channel of the HEMT is quantum thinned by devising the shape of the recess. In the present invention, the recess is formed by applying the method for manufacturing an asymmetric recess type HEMT described in JP-A-2002-184786.
[0016]
1 is a top view showing the entire structure of a field effect transistor according to an embodiment of the present invention, FIG. 2 (a) is a cross-sectional view taken along line AA of FIG. 1, and FIG. 2 (b) is BB of FIG. It is sectional drawing by a line.
[0017]
The field effect transistor according to the present embodiment includes an InP substrate 1, an i-type (intrinsic) InAlAs buffer layer 2, an i-type InGaAs channel layer 3, an i-type InAlAs spacer layer 4, a δ-doped sheet (carrier) formed thereon. Supply layer) 5, i-type InAlAs layer 6, i-type InP layer (etching stopper layer) 7, i-type InAlAs layer 8, n-type InGaAs cap layer 9, SiO₂The insulating film 10 is composed of a drain electrode 11, a source electrode 12, and a gate electrode 13. Reference numeral 51 denotes a region (two-dimensional electron existence region) where two-dimensional electrons exist in the surface layer portion of the channel layer 3. The gate electrode 13 is connected to a wiring 14 that intersects the gate electrode 13 at a right angle.
[0018]
As shown in FIGS. 2A and 2B, in the present embodiment, an i-type InAlAs layer 8 is formed under an n-type InGaAs cap layer 9, and an i-type InP layer 7 is further formed thereunder. Has been. When the distance from the i-type InP layer 7 to the channel layer 3 is sufficiently small, if the n-type InGaAs cap layer 9 and the i-type InAlAs layer 8 are removed by recess etching, the portion below these layers 8 and 9 is removed. Then, two-dimensional electrons disappear. In the present invention, such a phenomenon is utilized to form a quantum thinned channel.
[0019]
Hereinafter, an outline of a method for manufacturing the field effect transistor of the present embodiment will be described.
[0020]
In the present embodiment, slits (openings) P1 and P2 as shown in FIG. 3 are formed in the resist film used in the recess etching, and the n-type InGaAs cap layer 9 and the i-type InAlAs layer are formed from these slits P1 and P2. 8 is etched. As an etchant, H₃PO₄And H₂O₂And H₂Liquid mixture with O (H₃PO₄: H₂O₂: H₂When O = 1: 1: 38), the etching rate of the n-type InGaAs cap layer 9 and the i-type InAlAs layer 8 is about 100 nm / min when the temperature is 20 ° C. On the other hand, since the i-type InP layer 7 is hardly etched by the above etching solution, the etching in the thickness direction substantially stops when the i-type InP layer 7 is exposed.
[0021]
If the etching is further continued after the i-type InP layer 7 is exposed, the n-type InGaAs cap layer 9 and the i-type InAlAs layer 8 are etched in the lateral direction, and a two-dimensional electron existence region (as shown in FIG. 1) ( A hatched portion in the drawing) and a depletion layer (a white portion in the drawing) can be formed. In other words, in the present embodiment, a two-dimensional electron having a very narrow width is obtained by devising a resist film pattern when the n-type InGaAs cap layer 9 and the i-type InAlAs layer 8 above the channel layer 3 are recess-etched. The existence region 55 is formed. When a predetermined voltage is applied to the HEMT having such a configuration, the width is several tens of nanometers or less between the pair of two-dimensional electron existence regions 55 sandwiching the gate electrode 13, and the moving direction of electrons is limited to one dimension. A quantum wire channel is formed.
[0022]
The resist film pattern (slit pattern) used in the recess etching will be further described with reference to FIG. In the resist film, a slit P2 having a horizontal length of a and a vertical length of b and a slit P1 having a horizontal length of Lg and a vertical length of Wg are formed on the center line 50 of the gate electrode formation region. And a constant pitch c. The slit P1 is formed only on the center line 50, and two slits P2 are arranged between the adjacent slits P1. In addition, slits P2 are also formed at positions separated from the slit P2 on the center line 50 by Ls on the source electrode side and at positions separated by Ld on the drain electrode side.
[0023]
Here, Wg> b, Ls <2c-b, and Ld <2c-b. Usually, since the recess is formed symmetrically with respect to the center line 50 of the gate electrode formation region, Ls = Ld. When the n-type InGaAs cap layer 4 and the i-type InAlAs layer 8 are etched in the lateral direction until reaching the maximum size among Ls / 2, Ld / 2, and (c−b) / 2, FIG. A depletion layer as shown, and a linear two-dimensional electron existence region 55 extending from the source electrode 12 side and the drain electrode 11 side toward the center line 50 of the gate electrode formation region are obtained.
[0024]
After forming the two-dimensional electron existence region 55 having a narrow width in this way, the gate electrode 13 that is electrically connected to the i-type InP layer 7 is formed by metal vacuum deposition (or sputtering). In the present embodiment, the gate electrode 13 is formed by vacuum-depositing a metal on the i-type InP layer 7 through the slit P1. At this time, it is necessary to prevent metal atoms from reaching the i-type InP layer 7 through the slit P2. Therefore, in the present embodiment, the deposition is performed with the substrate 1 inclined with respect to the direction in which the metal atoms fly. That is, the substrate 1 is tilted by an angle α with respect to the direction of metal atom irradiation as shown in FIG. 4 with the direction orthogonal to the center line 50 of the gate electrode formation region as the axis. Here, the resist film 21 and SiO₂The total film thickness with the insulating film 10 is d, and the thickness of the recessed semiconductor layer (n-type InGaAs cap layer 9 + i-type InAlAs layer 8) is dr. The angle α needs to be set so as to satisfy the following expression (1).
[0025]
tan^-1(B / d) <α <tan^-1(Wg / (d + dr)) (1)
When the angle α is set so as to satisfy the equation (1), metal atoms pass through the slit P1 and are deposited on the i-type InP layer 7, but cannot pass through the slit P2. Further, metal is deposited on the side wall surfaces of the slits P1 and P2, and the opening area is reduced.
[0026]
When the opening area of the slit P2 is halved by the metal deposited on the side wall surface, the vacuum deposition is temporarily stopped, and the substrate 1 is tilted in the opposite direction by an angle −α. Then, vapor deposition is performed again until the slit P2 is closed with metal.
[0027]
In this way, after the slit P2 is closed by the metal, the metal is vapor-deposited from the direction perpendicular to the substrate 1 to have a predetermined thickness. Thereafter, the gate electrode 13 is formed, and the resist films 21, 22, and 23 are removed. In this way, the two-dimensional electron existence region 55 extending linearly from the source electrode side and the drain electrode side, and the gate electrode 13 electrically connected to the i-type InP layer 7 between the two-dimensional electron existence region 55. And can be formed.
[0028]
5-11 is sectional drawing which shows the manufacturing method of HEMT of this Embodiment in order of a process. The manufacturing method of HEMT is concretely demonstrated using these figures. 9 to 11, (a) is a cross-sectional view taken along the line AA in FIG. 1, and (b) is a cross-sectional view taken along the line BB in FIG.
[0029]
  First, as shown in FIG. 5, on the compound semiconductor substrate 1 made of InP, the i-type InAlAs buffer layer 2 is 300 nm, the i-type InGaAs channel layer 3 is 15 nm by MOCVD (metal organic chemical vapor deposition). The i-type InAlAs spacer layer 4 is 3 nm, Si-δ doped sheet 5 (doping amount: 5 × 10¹²cm ^-2 ), The i-type InAlAs layer 6 is sequentially formed to a thickness of 1 nm, the i-type InP layer 7 is 2 nm, the i-type InAlAs layer 8 is 10 nm, and the n-type InGaAs cap layer 9 is sequentially formed to a thickness of 20 nm. Si is used as the n-type dopant of the cap layer, and the doping concentration is, for example, 1 × 10. ¹⁹ cm^-3And In such a laminated structure, two-dimensional electrons are generated over the entire upper portion of the channel layer 3, and a two-dimensional electron existence region 55 is formed. Thereafter, SiO 2 is deposited on the cap layer 9 by, eg, CVD.₂An insulating film 10 is formed to a thickness of 30 nm.
[0030]
Next, as shown in FIG. 6, the insulating film 10 is patterned into a predetermined shape by photolithography. Thereafter, a metal film made of Ti / Pt / Au is formed on the entire upper surface of the substrate 1 by vacuum vapor deposition, and the metal film is patterned and the source electrode 12 and the drain electrode electrically connected to the n-type InGaAs cap layer 9 11 are formed.
[0031]
Next, as shown in FIG. 7, a photoresist film (first photoresist film) 21 and a photoresist film (second photoresist film) 22 are formed on the source electrode 12, the drain electrode 11, and the insulating film 10. Then, a photoresist film (third photoresist film) 23 is laminated in this order from the lower side. Here, the photoresist film 22 is formed of a photoresist having higher exposure sensitivity than the photoresist film 21 and the photoresist film 23. For example, the lower photoresist film 21 and the upper photoresist film 23 are formed by ZEP manufactured by Nippon Zeon Co., Ltd., and the intermediate photoresist film 22 is formed by PMGI manufactured by MCC (Microlithography Cheminal Corporation). The thickness of the photoresist film 21 is 170 nm, the thickness of the photoresist film 22 is 450 nm, and the thickness of the photoresist film 23 is 240 nm.
[0032]
Next, an electron beam is irradiated onto the photoresist films 22 and 23 above the gate electrode forming portion using an electron beam exposure apparatus. At this time, if the electron beam irradiation conditions are an acceleration voltage of 50 kV and an irradiation amount of 100 μC / cm, the lowermost photoresist film 21 is hardly exposed, and only the intermediate and uppermost photoresist films 22 and 23 are exposed. Can be exposed.
[0033]
Thereafter, a mixed solution (high-sensitivity developer) of methyl isobutyl ketone and methyl ethyl ketone is used for developing the photoresist film 23, and SD1 manufactured by Shipley Co. is used for developing the photoresist film 22. 23 is developed sequentially. Thereby, as shown in FIG. 8, the resist films 22 and 23 on the gate electrode formation region are removed. At this time, as described above, since the photoresist film 22 has higher sensitivity than the photoresist film 23, the opening width of the intermediate photoresist film 22 is larger than the opening width of the upper photoresist film 23.
[0034]
Next, as shown in FIGS. 9A and 9B, the above-described slits P1 and P2 are formed in the underlying photoresist film 21. Next, as shown in FIG. That is, the slit forming portion is exposed using the same electron beam exposure apparatus as described above under the conditions of an acceleration voltage of 50 kV and an irradiation amount of 1 nC / cm. Thereafter, the photoresist film 21 is developed using a mixed solution of methyl isobutyl ketone and isopropyl alcohol (low sensitivity developer) to form slits P1 and P2 as shown in FIG.
[0035]
In this example, the slit P1 is 50 nm (Lg) × 30 nm (Wg), the slit P2 is 50 nm (a) × 15 nm (b), the interval Ls between the slit P2 on the center line 50 and the source side slit P2 is 50 nm, The distance Ld between the slit P2 on the center line 50 and the drain side slit P2 is 50 nm, and the pitch c between the slits P1 and P2 is 50 nm.
[0036]
Next, using the photoresist film 21 as a mask, SiO 2₂Insulating film 10 is CF₄Etching is performed by a reactive ion etching method using a gas to partially expose the n-type InGaAs layer 9.
[0037]
Next, as shown in FIGS. 10A and 10B, the cap layer 9 and the i-type InAlAs layer 8 are wet-etched (recessed) using the photoresist film 21 and the insulating film 10 as a mask. At this time, the etching solution is H₃PO₄: H₂: H₂A solution having a mixing ratio of O = 1: 1: 38 is used and the temperature is 20 ° C. Further, the etching is finished when 25 nm is etched laterally from the slits P1 and P2.
[0038]
Thereby, the n-type InGaAs cap layer 9 and the i-type InAlAs layer 8 shown in white in FIG. 1 are removed. In addition, two-dimensional electrons disappear under the portion where the n-type InGaAs cap layer 9 and the i-type InAlAs layer 8 are removed.
[0039]
In the present embodiment, no other slits are provided on the left and right sides of the slit P1, and as shown in FIG. 1, two-dimensional electrons having a narrow width extending from the source electrode 12 side and the drain electrode 11 side toward the slit P1, respectively. A presence region 55 is formed. When the size and arrangement of the slits P1 and P2 are as described above, the width of the two-dimensional electron existence region 55 is 35 nm, and the distance between the two-dimensional electron existence region 55 and the slit P1 is 25 nm.
[0040]
Next, the gate electrode 13 is formed using a vacuum deposition method and a lift-off method. That is, as shown in FIG. 4, vacuum deposition is performed by tilting the substrate 1 by 5 ° (α = 5 °) with respect to the direction in which the metal atoms fly. Then, when the opening area of the slit P2 is halved by the metal deposited on the side wall surface, the vacuum deposition is temporarily stopped, and the substrate 1 is tilted by −5 ° (α = −5 °) in the opposite direction. And vacuum deposition is performed until the slit P2 is obstruct | occluded with the metal.
[0041]
In this way, after the slit P2 is closed by the metal, the metal is deposited from the direction perpendicular to the substrate 1. As a result, as shown in FIGS. 11A and 11B, the gate electrode 13 that is electrically connected to the i-type InP layer 7 through the slit P1 is formed.
[0042]
Thereafter, the resist films 22 and 23 are removed together with the metal film (not shown) thereon, and then the resist film 21 is further removed. Thereby, the field effect transistor (HEMT) of the present embodiment shown in FIGS. 1, 2A, and 2B is completed.
[0043]
In the present embodiment, a field effect transistor having a linear two-dimensional electron existence region 55 having a width of several tens of nanometers is compared without substantially changing a manufacturing apparatus and a manufacturing process used for manufacturing a conventional HEMT. Can be manufactured easily. In the present embodiment, no pattern is directly formed on the channel layer 3, so that no impurity contamination or lattice defects occur in the channel layer 3. Therefore, a field effect transistor having good electrical characteristics can be manufactured.
[0044]
In the present embodiment, the size and density (interval) of the quantum wire channel can be arbitrarily changed according to the size and arrangement of the slits P1 and P2. In the present embodiment, two slits P2 are arranged in two rows between the adjacent slits P1, but the number of slits P2 arranged between the slits P1 according to a desired recess length. May be changed.
[0045]
Next, the operation of the field effect transistor of the present invention will be described with reference to FIGS. 2 (a) and 2 (b) and FIGS. 12 (a) and 12 (b).
[0046]
When no voltage is applied to the gate electrode 13 or when a negative voltage is applied, the shape of the region 51 where the two-dimensional electrons exist is as shown in FIGS. 2A and 2B. And the same as the i-type InAlAs layer 8. That is, there are no two-dimensional electrons below the gate electrode 13.
[0047]
When a predetermined positive voltage is applied to the gate electrode 13, electrons are induced below the gate electrode 13 by an electric field generated from the gate electrode 13, and as shown in FIGS. The electron existence layer and the two-dimensional electron existence layer extending from the drain side are connected, and the quantum wire channel 56 is formed. A current flows between the source and the drain through the quantum wire channel 56.
[0048]
As described above, according to the present embodiment, a very narrow channel (quantum wire channel) can be formed between the source and the drain, so that a field effect transistor having a high electron moving speed and excellent high-frequency characteristics can be obtained. It is done.
[0049]
(Supplementary note 1) Compound semiconductor substrate, channel layer, carrier supply layer, etching stopper layer and cap layer made of a compound semiconductor layered on the compound semiconductor substrate, and insulation formed on the cap layer A recess formed by removing a film from the opening provided in the insulating film to the etching stopper layer, a depletion layer formed in the channel layer, and the portion above the depletion layer A gate electrode that is Schottky connected to the etching stopper layer and a two-dimensional electron existence region that is formed at a position sandwiching the depletion layer of the channel layer and extends linearly toward the Schottky connection portion of the gate electrode A field effect transistor having a source and a drain, wherein the shape of the source and the drain is the same as the shape of the cap layer. Njisuta.
[0050]
(Supplementary note 2) The field effect transistor according to supplementary note 1, wherein a width of the linear two-dimensional electron existence region of the source and the drain is a width capable of obtaining a quantum wire channel.
[0051]
(Appendix 3) A step of sequentially forming a channel layer, a carrier supply layer, an etching stopper layer and a cap layer made of a compound semiconductor on a compound semiconductor substrate, a step of forming an insulating film on the cap layer, and the insulating film A resist film forming step for forming a first photoresist film thereon, a first slit formed in the first photoresist film, and a position sandwiching the first slit from the first slit, respectively A step of forming a second slit having a small slit width and recess etching from the upper surface of the insulating film to the etching stopper layer through the first slit and the second slit of the photoresist film. A depletion layer in which two-dimensional electrons do not exist in the channel layer and both sides of the depletion layer and facing the first slit Forming a gate electrode by depositing only metal atoms passing through the first slit on the etching stopper layer, forming a source and a drain having a linear two-dimensional electron existence region extending; And a step of forming the field effect transistor.
[0052]
(Supplementary note 4) The method of manufacturing a field effect transistor according to supplementary note 3, wherein a plurality of the second slits are arranged in rows and columns on both sides of the first slit.
[0053]
(Supplementary note 5) The method of manufacturing a field effect transistor according to supplementary note 3, wherein a length of the second slit in a source / drain direction is longer than a length in a direction orthogonal to the source / drain direction.
[0054]
(Supplementary note 6) The field effect transistor according to Supplementary note 3, wherein the first slit and the second slit are formed at a constant pitch in a direction orthogonal to the source / drain direction. Method.
[0055]
(Appendix 7) In the resist film forming step, a second photoresist film having higher sensitivity than the first photoresist film is formed on the first photoresist film, and the second photoresist film is formed on the second photoresist film. A third photoresist film having a lower sensitivity than the second photoresist film is formed, and the first photoresist film and the second photoresist film are exposed and then subjected to a development process, and then the second photoresist film is exposed. An opening larger than the opening of the third photoresist film is formed in the photoresist film, and the first photoresist film exposed inside the opening of the second photoresist film is exposed and developed. The method for manufacturing a field effect transistor according to appendix 3, wherein the first slit and the second slit are formed.
[0056]
(Additional remark 8) The manufacturing method of the field effect transistor of Additional remark 3 or 7 characterized by forming the said gate electrode with the metal deposited on the said 1st photoresist film.
[0057]
(Supplementary note 9) In the gate electrode forming step, metal is deposited on the wall surface of the second slit in a state where the substrate is tilted with respect to the direction in which the metal atoms fly, and then the second slit is closed. 4. The method of manufacturing a field effect transistor according to appendix 3, wherein a metal is deposited on the etching stopper layer by arranging a substrate perpendicular to a direction in which metal atoms fly.
[0058]
(Supplementary Note 10) The first slit and the second slit have the same length in the source / drain direction, and the length of the first slit and the second slit in the direction perpendicular to the source / drain , Wg, b, respectively, d is the total thickness of the insulating film and the first photoresist film, dr is the thickness of the recessed semiconductor layer, and the direction in which metal atoms fly when forming the gate electrode Where tan is the angle at which the substrate is tilted with respect to^-1(B / d) <α <tan^-1The method of manufacturing a field effect transistor according to appendix 9, wherein the inequality (Wg / (d + dr)) is satisfied.
[0059]
(Supplementary note 11) The field effect transistor manufacturing method according to supplementary note 3, wherein the plurality of second slits are formed symmetrically with respect to a center line of a gate electrode formation region.
[0060]
(Supplementary note 12) The method of manufacturing a field effect transistor according to supplementary note 3, wherein a width of the linear two-dimensional electron existence region of the source and the drain is set to a width at which a quantum wire channel is obtained.
[0061]
【The invention's effect】
As described above, according to the present invention, after forming a channel layer, a carrier supply layer, an etching stopper layer, and a cap layer made of a compound semiconductor on a compound semiconductor substrate, the semiconductor on the etching stopper layer is removed. Thus, a source / drain having a linear two-dimensional electron existence region is formed. Therefore, in the present invention, a linear two-dimensional electron existence region can be formed without etching the channel layer, and a field effect transistor having excellent high frequency characteristics can be manufactured relatively easily. In the present invention, the gate electrode is formed using the slit of the resist film used for forming the recess. Thereby, a manufacturing process is simplified.
[Brief description of the drawings]
FIG. 1 is a top view showing an entire structure of a field effect transistor according to an embodiment of the present invention.
2A is a cross-sectional view taken along line AA in FIG. 1, and FIG. 2B is a cross-sectional view taken along line BB in FIG.
FIG. 3 is a schematic diagram showing the shape and arrangement of slits provided in a resist film used during recess etching.
FIG. 4 is a schematic diagram showing a tilt angle of a substrate with respect to a direction in which metal atoms fly.
FIG. 5 is a cross-sectional view (No. 1) showing the method for manufacturing the HEMT according to the embodiment of the present invention.
FIG. 6 is a sectional view (No. 2) showing the method for manufacturing the HEMT according to the embodiment of the present invention.
FIG. 7 is a sectional view (No. 3) showing the method for manufacturing the HEMT according to the embodiment of the present invention.
FIG. 8 is a sectional view (No. 4) showing the method for manufacturing the HEMT according to the embodiment of the present invention.
9 is a sectional view (No. 5) showing the method for manufacturing the HEMT according to the embodiment of the present invention; FIG. 9 (a) is a sectional view taken along the line AA in FIG. b) shows a cross section at the position of line BB in FIG.
10 is a cross-sectional view (No. 6) showing the method of manufacturing the HEMT according to the embodiment of the present invention; FIG. 10 (a) is a cross-sectional view taken along the line AA in FIG. b) shows a cross section at the position of line BB in FIG.
11 is a sectional view (No. 7) showing the method for manufacturing the HEMT according to the embodiment of the present invention; FIG. 11 (a) is a sectional view taken along the line AA in FIG. b) shows a cross section at the position of line BB in FIG.
FIGS. 12A and 12B are schematic views showing the operation of the field effect transistor of the present invention.
[Explanation of symbols]
1 ... InP substrate,
2 ... i-type InAlAs buffer layer,
3 ... i-type InGaAs channel layer,
4 ... i-type InAlAs spacer layer,
5 ... delta dope sheet (carrier supply layer),
6 ... i-type InAlAs layer,
7 ... i-type InP layer (etching stopper layer),
8 ... i-type InAlAs layer,
9: n-type InGaAs cap layer,
10: Insulating film,
11 ... drain electrode,
12 ... Source electrode,
13 ... Gate electrode,
14 ... wiring,
21, 22, 23 ... Photoresist film,
51, 55 ... two-dimensional electron existence region,
56 ... Quantum wire channel.

Claims (4)

A compound semiconductor substrate;
A channel layer made of a compound semiconductor formed on the compound semiconductor substrate, a carrier supply layer, an etching stopper layer, and a cap layer;
An insulating film formed on the cap layer;
The semiconductor from the opening provided in the insulating film to the etching stopper layer was removed, and when viewed from above, a wide portion and a narrow portion were alternately formed along a straight line. Recess and
A depletion layer formed in the channel layer below the recess;
A gate electrode Schottky connected to the etching stopper layer in a narrow portion of the recess;
A shot of the gate electrode is formed at a position sandwiching the depletion layer below the narrow portion of the recess and linearly defined by the depletion layer below the wide portion of the recess. A source and drain with a two-dimensional electron presence region extending towards the key connection,
A field effect transistor, wherein the source and the drain have the same shape as the cap layer. A step of sequentially forming a channel layer, a carrier supply layer, an etching stopper layer, and a cap layer made of a compound semiconductor on a compound semiconductor substrate;
Forming an insulating film on the cap layer;
A resist film forming step of forming a first photoresist film on the insulating film;
A plurality of first slits arranged in the vertical direction are formed in the first photoresist film, and at a position sandwiching the first slit from the vertical direction, the first slit is more longitudinal than the first slit. Forming one or a plurality of second slits having a small length in a lateral direction wider than the first slit ;
Recess etching is performed from the upper surface of the insulating film to the etching stopper layer through the first slit and the second slit of the photoresist film, and the channel layer below and around the first and second slits. Forming a depletion layer having a shape in which a portion having a small length in the horizontal direction and a portion having a large length in the horizontal direction are alternately connected in the vertical direction;
The metal is deposited on the wall surface of the second slit in a state where the substrate is tilted with respect to the direction in which the metal atoms come in to close the second slit, and then the substrate in the direction in which the metal atoms come in A gate electrode forming step of forming a gate electrode by depositing only metal atoms arranged vertically and passing through the first slit on the etching stopper layer;
A method for producing a field effect transistor, comprising: In the resist film forming step,
Forming a second photoresist film having higher sensitivity than the first photoresist film on the first photoresist film;
Forming a third photoresist film having a lower sensitivity than the second photoresist film on the second photoresist film;
A development process is performed after exposing the third photoresist film and the second photoresist film to form an opening larger than the opening of the third photoresist film in the second photoresist film. And
The first slit and the second slit are formed by exposing and developing the first photoresist film exposed inside the opening of the second photoresist film. Item 3. A method for producing a field effect transistor according to Item 2.   4. The method of manufacturing a field effect transistor according to claim 2, wherein the gate electrode is formed of a metal deposited on the first photoresist film.

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