JP2004281926A - Field-effect transistor and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a field-effect transistor having quantum wire channels, which can be relatively easily manufactured, and a method for manufacturing the transistor. <P>SOLUTION: In the field-effect transistor, the shape and array of the slits provided to a photoresist film for use in formation of a recess are devised. Thereby a two-dimensional electron presence layer extended as thin lines from the source and drain of an i type InGaAs channel layer 3 to the Schottky junction of the gate electrode 13 is formed. In the transistor, a metal is deposited on an i type InP etching stop layer 7 only via a predetermined slit provided in the photoresist film to form the gate electrode 13 Schottky connected to the etching stop layer 7. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a field-effect transistor such as a high electron mobility transistor (hereinafter, referred to as “HEMT”) used for a high-frequency device or the like, and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, in order to obtain a semiconductor device operating in a millimeter wave band (30 to 300 GHz) or a submillimeter wave band (300 GHz to 3 THz), research on miniaturization of HEMTs has been actively conducted. In particular, the HEMT in which an electron supply layer made of InAlAs and a channel layer made of InGaAs are lattice-matched on an InP substrate has a large energy gap of 0.53 eV in the conduction band between InAlAs and InGaAs, and has a large energy gap of InGaAs as a channel layer. Promising due to the high electron mobility and saturation velocity at room temperature, it has been the main research target.
[0003]
In HEMTs made of these materials, attempts have been made to increase the In composition ratio of the channel layer to about 0.7 to increase electron mobility and saturation speed. Heretofore, in HEMTs made of these materials, a cutoff frequency of 500 GHz or more has been obtained by reducing the gate length to about 25 nm and further reducing the distance between the gate electrode and the channel layer.
[0004]
Japanese Patent Application Laid-Open No. 2002-184786 discloses an asymmetric recess type HEMT in which the distance between the gate and the drain is made larger than the distance between the source and the gate in order to improve the withstand voltage between the source and the drain, and a method of manufacturing the same. Is described.
[0005]
[Patent Document 1]
JP 2002-184786 A
[0006]
[Problems to be solved by the invention]
However, it is difficult to further improve the high-frequency characteristics only by reducing the gate length, shortening the distance between the gate electrode and the channel layer, and changing the material composition. For example, a new HEMT having a cutoff frequency exceeding 1 THz is required. It is necessary to introduce a new concept. As one of them, it has been proposed to increase the electron moving speed by making the channel into a quantum wire of several tens nm or less. However, no practical method has been developed for quantum thinning the channel.
[0007]
As described above, an object of the present invention is to provide a field-effect transistor having a channel with a quantum wire.
[0008]
Another object of the present invention is to provide a method for manufacturing a field-effect transistor that can relatively easily manufacture a field-effect transistor having a quantum-wired channel.
[0009]
[Means for Solving the Problems]
The above-mentioned problems are formed on a compound semiconductor substrate, a channel layer, a carrier supply layer, an etching stopper layer and a cap layer made of a compound semiconductor formed by being laminated on the compound semiconductor substrate, and on the cap layer. An insulating film, a recess formed by removing a semiconductor from an opening provided in the insulating film to the etching stopper layer, a depletion layer formed in the channel layer, and a portion above the depletion layer. A gate electrode that is Schottky-connected to the etching stopper layer; and a two-dimensional electron existence region that is formed at a position sandwiching the depletion layer of the channel layer and extends linearly toward the Schottky connection of the gate electrode. A source and a drain, wherein the shape of the source and the drain is the same as the shape of the cap layer. It is solved by fruit transistor.
[0010]
The above-described problem is that a channel layer, a carrier supply layer, an etching stopper layer, and a cap layer made of a compound semiconductor are sequentially formed on a compound semiconductor substrate; a step of forming an insulating film on the cap layer; A resist film forming step of forming a first photoresist film on the film, forming a first slit in the first photoresist film, and forming the first slit at a position sandwiching the first slit. Forming a second slit having a smaller slit width than the above, and recess etching from the upper surface of the insulating film to the etching stopper layer through the first slit and the second slit of the photoresist film. A depletion layer in which two-dimensional electrons do not exist in the channel layer and the first slit disposed on both sides of the depletion layer Forming a source and a drain having a linear two-dimensional electron existence region extending toward the gate; and forming a gate electrode by depositing only metal atoms passing through the first slit on the etching stopper layer. And a step of forming a gate electrode.
[0011]
In the present invention, a channel layer, a carrier supply layer, an etching stopper layer, and a cap layer made of a compound semiconductor are formed on a compound semiconductor substrate. In such a laminated structure, two-dimensional electrons (2DEG: 2 Dimensional Electron Gas) are generated above the channel layer. Thereafter, when the semiconductor above the etching stopper layer is removed by etching, two-dimensional electrons below the portion from which the semiconductor has been removed disappear and a depletion layer is formed, and a region where two-dimensional electrons exist on both sides of the depletion layer, That is, it becomes a source / drain.
[0012]
In this case, by forming no slit on both sides of the first slit in the source / drain direction and forming the second slit in a direction intersecting the source / drain direction, a linear two-dimensional An electron presence area can be provided. When a predetermined voltage is applied between the date electrode and the source / drain, a channel having a quantum wire is formed between these two-dimensional electron existence regions.
[0013]
As described above, in the present invention, it is possible to form a linear two-dimensional electron existence region without etching the channel layer, and it is possible to relatively easily manufacture a field-effect transistor having excellent high-frequency characteristics. it can. Further, in the present invention, a gate electrode is formed using a slit of a resist film used for forming a recess. This simplifies the manufacturing process.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
[0015]
Generally, in the HEMT, a cap layer made of an n-type semiconductor is used to obtain an ohmic junction with a source electrode and a drain electrode. In addition, the n-type semiconductor cap layer is removed from the Schottky junction of the gate electrode. The portion from which the n-type semiconductor cap layer is removed is called a recess. In the present invention, the channel of the HEMT is made into a quantum wire by devising the shape of the recess. In the present invention, the recess is formed by applying the method of manufacturing an asymmetric recess type HEMT described in JP-A-2002-184786.
[0016]
FIG. 1 is a top view showing the overall structure of a field effect transistor according to an embodiment of the present invention, FIG. 2A is a cross-sectional view taken along line AA in FIG. 1, and FIG. 2B is BB in FIG. It is sectional drawing by a line.
[0017]
The field-effect transistor of the present embodiment includes an InP substrate 1, an i-type (intrinsic) InAlAs buffer layer 2, an i-type InGaAs channel layer 3, an i-type InAlAs spacer layer 4, and a δ-doped sheet (carrier). Supply layer) 5, i-type InAlAs layer 6, i-type InP layer (etching stopper layer) 7, i-type InAlAs layer 8, n-type InGaAs cap layer 9, SiO ₂ , A drain electrode 11, a source electrode 12, and a gate electrode 13. Reference numeral 51 denotes a region of the surface layer of the channel layer 3 where two-dimensional electrons exist (two-dimensional electron existence region). The gate electrode 13 is connected to a wiring 14 that intersects the gate electrode 13 at right angles.
[0018]
As shown in FIGS. 2A and 2B, in the present embodiment, an i-type InAlAs layer 8 is formed below an n-type InGaAs cap layer 9, and an i-type InP layer 7 is further formed thereunder. Have been. When the distance from the i-type InP layer 7 to the channel layer 3 is sufficiently small, the n-type InGaAs cap layer 9 and the i-type InAlAs layer 8 are removed by recess etching. Then, two-dimensional electrons disappear. In the present invention, a quantum-wired channel is formed using such a phenomenon.
[0019]
Hereinafter, an outline of a method for manufacturing the field-effect transistor of the present embodiment will be described.
[0020]
In this embodiment, slits (openings) P1 and P2 as shown in FIG. 3 are formed in a resist film used at the time of recess etching, and n-type InGaAs cap layer 9 and i-type InAlAs layer are formed from these slits P1 and P2. 8 is etched. H as an etchant ₃ PO ₄ And H ₂ O ₂ And H ₂ Liquid mixture with O (H ₃ PO ₄ : H ₂ O ₂ : H ₂ When (O = 1: 1: 38) is used, the etching rate of the n-type InGaAs cap layer 9 and the i-type InAlAs layer 8 is about 100 nm / min when the temperature is 20 ° C. On the other hand, since the i-type InP layer 7 is hardly etched by the above-mentioned etching solution, the etching in the thickness direction is substantially stopped when the i-type InP layer 7 is exposed.
[0021]
If the etching is further continued after the i-type InP layer 7 is exposed, the n-type InGaAs cap layer 9 and the i-type InAlAs layer 8 are etched in the lateral direction, and the two-dimensional electron existence region ( A hatched portion in the drawing) and a depletion layer (opened portion in the drawing) can be formed. That is, in the present embodiment, the two-dimensional electron having a very narrow width is devised by devising the pattern of the resist film when recess etching the n-type InGaAs cap layer 9 and the i-type InAlAs layer 8 above the channel layer 3. An existence region 55 is formed. When a predetermined voltage is applied to the HEMT having such a configuration, the width between the pair of two-dimensional electron existing regions 55 sandwiching the gate electrode 13 is not more than several tens nm, and the electron movement direction is restricted to one dimension. A quantum wire channel is formed.
[0022]
The pattern (slit pattern) of the resist film used during the recess etching will be further described with reference to FIG. In the resist film, a slit P2 having a horizontal length of a and a vertical length of b, and a slit P1 having a horizontal length of Lg and a vertical length of Wg are formed on the center line 50 of the gate electrode formation region. Along with a constant pitch c. The slit P1 is formed only on the center line 50, and two slits P2 are arranged between the adjacent slits P1. Slits P2 are also formed at positions separated from the slit P2 on the center line 50 by Ls toward the source electrode and at positions separated by Ld toward the drain electrode.
[0023]
Here, it is assumed that Wg> b, Ls <2c-b, and Ld <2c-b. Usually, since the recess is formed symmetrically with respect to the center line 50 of the gate electrode formation region, Ls = Ld. FIG. 1 shows that the n-type InGaAs cap layer 4 and the i-type InAlAs layer 8 are laterally etched to reach the largest of Ls / 2, Ld / 2 and (c−b) / 2. As shown, a depletion layer and a linear two-dimensional electron existence region 55 extending from the source electrode 12 side and the drain electrode 11 side toward the center line 50 of the gate electrode formation region are obtained.
[0024]
After forming the narrow two-dimensional electron existence region 55 in this manner, the gate electrode 13 electrically connected to the i-type InP layer 7 is formed by vacuum evaporation (or sputtering) of metal. In the present embodiment, the gate electrode 13 is formed by vacuum-depositing a metal on the i-type InP layer 7 through the slit P1. At this time, it is necessary to prevent metal atoms from reaching the i-type InP layer 7 through the slit P2. For this purpose, in the present embodiment, the evaporation is performed by tilting the substrate 1 with respect to the direction in which the metal atoms fly. That is, as shown in FIG. 4, the substrate 1 is inclined by an angle α with respect to the irradiation direction of the metal atoms, with the direction perpendicular to the center line 50 of the gate electrode formation region as the axis. Here, the resist film 21 and SiO ₂ The total film thickness with the insulating film 10 is d, and the thickness of the recessed semiconductor layer (n-type InGaAs cap layer 9 + i-type InAlAs layer 8) is dr. The angle α needs to be set so as to satisfy the following equation (1).
[0025]
tan ^-1 (B / d) <α <tan ^-1 (Wg / (d + dr)) (1)
If the angle α is set so as to satisfy the equation (1), metal atoms pass through the slit P1 and deposit on the i-type InP layer 7, but cannot pass through the slit P2. Further, metal is deposited on the side wall surfaces of the slits P1 and P2, and the opening area decreases.
[0026]
When the opening area of the slit P2 becomes half by the metal deposited on the side wall surface, the vacuum deposition is temporarily stopped, and the substrate 1 is tilted in the opposite direction by the angle -α. Then, vapor deposition is performed again until the slit P2 is closed by the metal.
[0027]
After the slit P2 is closed by the metal in this manner, a metal is vapor-deposited on the substrate 1 in a direction perpendicular to the substrate 1 to have a predetermined thickness. Thereafter, a gate electrode 13 is formed, and the resist films 21, 22, and 23 are removed. Thus, the two-dimensional electron existence region 55 linearly extending from the source electrode side and the drain electrode side, and the gate electrode 13 electrically connected to the i-type InP layer 7 between the two-dimensional electron existence region 55 And can be formed.
[0028]
5 to 11 are cross-sectional views illustrating a method of manufacturing the HEMT according to the present embodiment in the order of steps. The manufacturing method of the HEMT will be specifically described with reference to these drawings. 9A to 11, (a) is a cross-sectional view taken along a line AA in FIG. 1, and (b) is a cross-sectional view taken along a line BB in FIG. 1.
[0029]
First, as shown in FIG. 5, an i-type InAlAs buffer layer 2 of 300 nm and an i-type InGaAs channel layer 3 of 15 nm are formed on a compound semiconductor substrate 1 of InP by MOCVD (metal organic chemical vapor deposition). The i-type InAlAs spacer layer 4 is 3 nm thick, and the Si-δ doped sheet 5 (doping amount: 5 × 10 ¹² cm ⁻ 2) The i-type InAlAs layer 6 is formed to a thickness of 1 nm, the i-type InP layer 7 is formed to a thickness of 2 nm, the i-type InAlAs layer 8 is formed to a thickness of 10 nm, and the n-type InGaAs cap layer 9 is formed to a thickness of 20 nm. Si is used as the n-type dopant of the cap layer, and the doping concentration is, for example, 1 × 10 ¹ 9cm ^-3 And In such a laminated structure, two-dimensional electrons are generated in the entire upper region of the channel layer 3, and the two-dimensional electron existence region 55 is formed. Thereafter, for example, by a CVD method, ₂ The insulating film 10 is formed to a thickness of 30 nm.
[0030]
Next, as shown in FIG. 6, the insulating film 10 is patterned into a predetermined shape by a photolithography method. Thereafter, a metal film made of Ti / Pt / Au is formed on the entire upper surface of the substrate 1 by vacuum evaporation, and the metal film is patterned to form a source electrode 12 and a drain electrode electrically connected to the n-type InGaAs cap layer 9. 11 are formed.
[0031]
Next, as shown in FIG. 7, a photoresist film (first photoresist film) 21 and a photoresist film (second photoresist film) 22 are formed on the source electrode 12, the drain electrode 11, and the insulating film 10. Then, a photoresist film (third photoresist film) 23 is laminated in this order from below. Here, the photoresist film 22 is formed of a photoresist having a higher exposure sensitivity than the photoresist films 21 and 23. For example, the lower photoresist film 21 and the upper photoresist film 23 are formed by ZEP manufactured by Zeon Corporation, and the intermediate photoresist film 22 is formed by PMGI manufactured by MCC (Microlithography Chemical Corporation). The thickness of the photoresist film 21 is 170 nm, the thickness of the photoresist film 22 is 450 nm, and the thickness of the photoresist film 23 is 240 nm.
[0032]
Next, an electron beam is applied to the photoresist films 22 and 23 above the gate electrode forming portion using an electron beam exposure apparatus. At this time, if the irradiation conditions of the electron beam are an acceleration voltage of 50 kV and an irradiation amount of 100 μC / cm, the lowermost photoresist film 21 is hardly exposed, and only the intermediate and uppermost photoresist films 22 and 23 are exposed. Can be exposed.
[0033]
Thereafter, a mixed solution of methyl isobutyl ketone and methyl ethyl ketone (high-sensitivity developer) is used for developing the photoresist film 23, and SD1 manufactured by Shipley Co., Ltd. is used for developing the photoresist film 22. 23 are sequentially developed. Thus, as shown in FIG. 8, the resist films 22 and 23 on the gate electrode formation region are removed. At this time, as described above, since the photoresist film 22 has higher sensitivity than the photoresist film 23, the opening width of the intermediate photoresist film 22 is larger than the opening width of the upper photoresist film 23.
[0034]
Next, as shown in FIGS. 9A and 9B, the slits P1 and P2 described above are formed in the lower photoresist film 21. That is, the slit forming portion is exposed under the conditions of an acceleration voltage of 50 kV and a dose of 1 nC / cm using the same electron beam exposure apparatus as described above. Thereafter, the photoresist film 21 is developed using a mixed solution of methyl isobutyl ketone and isopropyl alcohol (a low-sensitivity developer) to form slits P1 and P2 as shown in FIG.
[0035]
In this example, the slit P1 is 50 nm (Lg) × 30 nm (Wg), the slit P2 is 50 nm (a) × 15 nm (b), the distance Ls between the slit P2 on the center line 50 and the slit P2 on the source side is 50 nm, The distance Ld between the slit P2 on the center line 50 and the slit P2 on the drain side is 50 nm, and the pitch c between the slits P1 and P2 is 50 nm.
[0036]
Next, using the photoresist film 21 as a mask, SiO 2 ₂ The insulating film 10 is CF ₄ The n-type InGaAs layer 9 is partially exposed by etching by a reactive ion etching method using a gas.
[0037]
Next, as shown in FIGS. 10A and 10B, the cap layer 9 and the i-type InAlAs layer 8 are subjected to wet etching (recess etching) using the photoresist film 21 and the insulating film 10 as a mask. At this time, the etching solution contains H ₃ PO ₄ : H ₂ : H ₂ The reaction is performed at a temperature of 20 ° C. using a solution having a mixing ratio of O = 1: 1: 38. Further, the etching is terminated at the time when the film is etched by 25 nm in the horizontal direction from the slits P1 and P2.
[0038]
As a result, the portions of the n-type InGaAs cap layer 9 and the i-type InAlAs layer 8 shown in white in FIG. 1 are removed. Further, below the portion where the n-type InGaAs cap layer 9 and the i-type InAlAs layer 8 are removed, two-dimensional electrons disappear.
[0039]
In the present embodiment, since no other slits are provided on the left and right of the slit P1, as shown in FIG. 1, the two-dimensional electron having a narrow width extending from the source electrode 12 side and the drain electrode 11 side toward the slit P1 is small. The existence area 55 is formed. When the size and arrangement of the slits P1 and P2 are as described above, the width of the two-dimensional electron existence region 55 is 35 nm, and the distance between the two-dimensional electron existence region 55 and the slit P1 is 25 nm.
[0040]
Next, the gate electrode 13 is formed using a vacuum deposition method and a lift-off method. That is, as shown in FIG. 4, vacuum evaporation is performed by inclining the substrate 1 at 5 ° (α = 5 °) with respect to the direction in which metal atoms fly. Then, when the opening area of the slit P2 is reduced to half by the metal deposited on the side wall surface, the vacuum deposition is temporarily stopped, and the substrate 1 is tilted by −5 ° (α = −5 °) in the opposite direction. Then, vacuum evaporation is performed until the slit P2 is closed by the metal.
[0041]
In this way, after the slit P2 is closed by the metal, the metal is vapor-deposited on the substrate 1 from the vertical direction. Thereby, as shown in FIGS. 11A and 11B, the gate electrode 13 electrically connected to the i-type InP layer 7 via the slit P1 is formed.
[0042]
Then, after removing the resist films 22 and 23 together with the metal film (not shown) thereon, the resist film 21 is further removed. Thereby, the field effect transistor (HEMT) of the present embodiment shown in FIGS. 1, 2A and 2B is completed.
[0043]
In the present embodiment, a field effect transistor having a linear two-dimensional electron existence region 55 having a width of several tens nm is compared with a manufacturing apparatus and a manufacturing process used for manufacturing a conventional HEMT with almost no change. It can be easily manufactured. Further, in the present embodiment, since no pattern is directly formed on the channel layer 3, there is no occurrence of impurity contamination or lattice defects in the channel layer 3. Therefore, a field effect transistor having good electric characteristics can be manufactured.
[0044]
In the present embodiment, the size and density (interval) of the quantum wire channel can be arbitrarily changed depending on the size and arrangement of the slits P1 and P2. Further, in this embodiment, two slits P2 are arranged in two rows between mutually adjacent slits P1, but the number of slits P2 arranged between slits P1 according to a desired recess length is set. May be changed.
[0045]
Next, the operation of the field effect transistor of the present invention will be described with reference to FIGS. 2 (a) and 2 (b) and FIGS. 12 (a) and 12 (b).
[0046]
When a voltage is not applied to the gate electrode 13 or when a negative voltage is applied, as shown in FIGS. 2A and 2B, the shape of the region 51 in which the two-dimensional electrons exist is determined by the upper cap layer 9. And the same as the i-type InAlAs layer 8. That is, no two-dimensional electron exists below the gate electrode 13.
[0047]
When a predetermined positive voltage is applied to the gate electrode 13, electrons are induced below the gate electrode 13 by an electric field generated by the gate electrode 13, and as shown in FIGS. The electron existence layer and the two-dimensional electron existence layer extending from the drain side are connected to form the quantum wire channel 56. A current flows between the source and the drain via the quantum wire channel 56.
[0048]
As described above, according to the present embodiment, a very narrow channel (quantum wire channel) can be formed between the source and the drain, so that a field-effect transistor having a high electron moving speed and excellent high-frequency characteristics can be obtained. Can be
[0049]
(Supplementary Note 1) A compound semiconductor substrate, a channel layer, a carrier supply layer, an etching stopper layer, and a cap layer made of a compound semiconductor formed by being laminated on the compound semiconductor substrate, and an insulating layer formed on the cap layer A film, a recess formed by removing a semiconductor from an opening provided in the insulating film to the etching stopper layer, a depletion layer formed in the channel layer, and a portion above the depletion layer. A gate electrode that is Schottky-connected to the etching stopper layer; and a two-dimensional electron existence region that is formed at a position sandwiching the depletion layer of the channel layer and extends linearly toward the Schottky connection of the gate electrode. A field effect transistor having a source and a drain, wherein the shape of the source and the drain is the same as the shape of the cap layer. Njisuta.
[0050]
(Supplementary note 2) The field-effect transistor according to supplementary note 1, wherein the width of the linear two-dimensional electron existence region of the source and the drain is a width from which a quantum wire channel can be obtained.
[0051]
(Supplementary Note 3) a step of sequentially forming a channel layer, a carrier supply layer, an etching stopper layer, and a cap layer made of a compound semiconductor on a compound semiconductor substrate; a step of forming an insulating film on the cap layer; A resist film forming step of forming a first photoresist film thereon, forming a first slit in the first photoresist film, and positioning the first slit at a position sandwiching the first slit from the first slit. Forming a second slit having a small slit width, and recess etching from the upper surface of the insulating film to the etching stopper layer through the first slit and the second slit of the photoresist film. A depletion layer in which two-dimensional electrons do not exist in the channel layer, and a depletion layer disposed on both sides of the depletion layer and facing the first slit. Forming a source and a drain having an extended linear two-dimensional electron existence region; and forming a gate electrode by depositing only metal atoms passing through the first slit on the etching stopper layer. Forming a field effect transistor.
[0052]
(Supplementary Note 4) The method for manufacturing a field-effect transistor according to Supplementary Note 3, wherein a plurality of the second slits are arranged in a matrix on both sides of the first slit.
[0053]
(Supplementary note 5) The method for manufacturing a field-effect transistor according to supplementary note 3, wherein the length of the second slit in the source / drain direction is larger than the length in the direction orthogonal to the source / drain direction.
[0054]
(Supplementary Note 6) The manufacturing of the field-effect transistor according to Supplementary Note 3, wherein the first slit and the second slit are arranged at a constant pitch in a direction orthogonal to the source / drain direction. Method.
[0055]
(Supplementary Note 7) In the resist film forming step, a second photoresist film having higher sensitivity than the first photoresist film is formed on the first photoresist film, and the second photoresist film is formed on the second photoresist film. Forming a third photoresist film having a lower sensitivity than the second photoresist film, performing a developing process after exposing the first photoresist film and the second photoresist film, and An opening larger than the opening of the third photoresist film is formed in the photoresist film, and the first photoresist film exposed inside the opening of the second photoresist film is exposed and developed. The method for manufacturing a field-effect transistor according to claim 3, wherein the first slit and the second slit are formed.
[0056]
(Supplementary note 8) The method for manufacturing a field-effect transistor according to supplementary note 3 or 7, wherein the gate electrode is formed of a metal deposited on the first photoresist film.
[0057]
(Supplementary Note 9) In the gate electrode forming step, a metal is deposited on a wall surface of the second slit to close the second slit while the substrate is inclined with respect to a direction in which metal atoms fly, and then the second slit is closed. 4. The method for manufacturing a field-effect transistor according to claim 3, wherein a substrate is arranged perpendicular to a direction in which metal atoms fly, and a metal is deposited on the etching stopper layer.
[0058]
(Supplementary Note 10) The length of the first slit and the second slit in the source / drain direction is the same, and the length of the first slit and the second slit in the direction orthogonal to the source / drain Are respectively Wg and b, the total thickness of the insulating film and the first photoresist film is d, the thickness of the recessed semiconductor layer is dr, and the direction in which metal atoms fly when the gate electrode is formed. When the angle of tilting the substrate with respect to ^-1 (B / d) <α <tan ^-1 The method for manufacturing a field effect transistor according to claim 9, wherein the inequality (Wg / (d + dr)) is satisfied.
[0059]
(Supplementary note 11) The method for manufacturing a field-effect transistor according to supplementary note 3, wherein the plurality of second slits are formed symmetrically with respect to a center line of the gate electrode formation region.
[0060]
(Supplementary note 12) The method for manufacturing a field-effect transistor according to supplementary note 3, wherein a width of the linear two-dimensional electron existence region of the source and the drain is set to a width at which a quantum wire channel is obtained.
[0061]
【The invention's effect】
As described above, according to the present invention, after forming a channel layer, a carrier supply layer, an etching stopper layer, and a cap layer made of a compound semiconductor on a compound semiconductor substrate, the semiconductor on the etching stopper layer is removed. As a result, a source / drain having a linear two-dimensional electron existence region is formed. Therefore, in the present invention, a linear two-dimensional electron existence region can be formed without etching the channel layer, and a field effect transistor having excellent high-frequency characteristics can be relatively easily manufactured. Further, in the present invention, a gate electrode is formed using a slit of a resist film used for forming a recess. This simplifies the manufacturing process.
[Brief description of the drawings]
FIG. 1 is a top view showing the overall structure of a field effect transistor according to an embodiment of the present invention.
2A is a cross-sectional view taken along line AA of FIG. 1, and FIG. 2B is a cross-sectional view taken along line BB of FIG.
FIG. 3 is a schematic view showing the shape and arrangement of slits provided in a resist film used during recess etching.
FIG. 4 is a schematic diagram illustrating a tilt angle of a substrate with respect to a direction in which metal atoms fly.
FIG. 5 is a sectional view (part 1) illustrating the method of manufacturing the HEMT according to the embodiment of the present invention;
FIG. 6 is a sectional view (part 2) illustrating the method of manufacturing the HEMT according to the embodiment of the present invention.
FIG. 7 is a sectional view (part 3) illustrating the method of manufacturing the HEMT according to the embodiment of the present invention;
FIG. 8 is a sectional view (part 4) illustrating the method of manufacturing the HEMT according to the embodiment of the present invention;
FIG. 9 is a cross-sectional view (part 5) illustrating the method of manufacturing the HEMT according to the embodiment of the present invention; FIG. 9 (a) is a cross-sectional view taken along the line AA of FIG. 1; b) shows a cross section at the position of line BB in FIG.
FIG. 10 is a sectional view (part 6) illustrating the method of manufacturing the HEMT according to the embodiment of the present invention; FIG. 10 (a) is a sectional view taken along the line AA in FIG. 1; b) shows a cross section at the position of line BB in FIG.
FIG. 11 is a sectional view (part 7) showing the method for manufacturing the HEMT according to the embodiment of the present invention; FIG. 11 (a) is a sectional view taken along line AA of FIG. 1; b) shows a cross section at the position of line BB in FIG.
FIGS. 12A and 12B are schematic diagrams showing the operation of the field-effect transistor of the present invention.
[Explanation of symbols]
1. InP substrate,
2 ... i-type InAlAs buffer layer,
3 ... i-type InGaAs channel layer,
4 ... i-type InAlAs spacer layer,
5 ... δ-doped sheet (carrier supply layer),
6 ... i-type InAlAs layer,
7 ... i-type InP layer (etching stopper layer),
8 ... i-type InAlAs layer,
9 ... n-type InGaAs cap layer,
10 ... insulating film,
11 ... Drain electrode,
12 ... source electrode,
13 ... gate electrode,
14. Wiring,
21, 22, 23 ... photoresist film,
51, 55 ... two-dimensional electron existence region,
56 ... Quantum wire channel.

Claims (5)

A compound semiconductor substrate;
A channel layer, a carrier supply layer, an etching stopper layer, and a cap layer made of a compound semiconductor formed by being stacked on the compound semiconductor substrate,
An insulating film formed on the cap layer,
A recess formed by removing the semiconductor from the opening provided in the insulating film to the etching stopper layer,
A depletion layer formed in the channel layer;
A gate electrode Schottky-connected to the etching stopper layer in a portion above the depletion layer;
A source and a drain each formed at a position sandwiching the depletion layer of the channel layer and having a two-dimensional electron existence region linearly extending toward a Schottky connection portion of the gate electrode;
A field effect transistor, wherein the shape of the source and the drain is the same as the shape of the cap layer. A step of sequentially forming a channel layer made of a compound semiconductor, a carrier supply layer, an etching stopper layer and a cap layer on a compound semiconductor substrate,
Forming an insulating film on the cap layer;
A resist film forming step of forming a first photoresist film on the insulating film;
Forming a first slit in the first photoresist film and forming a second slit having a smaller slit width than the first slit at a position sandwiching the first slit,
By performing recess etching from the upper surface of the insulating film to the etching stopper layer through the first slit and the second slit of the photoresist film, a depletion layer in which two-dimensional electrons do not exist in the channel layer, Forming a source and a drain having a linear two-dimensional electron existence region disposed on both sides of the depletion layer and extending toward the first slit;
Forming a gate electrode by depositing only metal atoms passing through the first slit on the etching stopper layer, thereby forming a gate electrode. In the resist film forming step,
Forming a second photoresist film having a higher sensitivity than the first photoresist film on the first photoresist film;
Forming a third photoresist film having lower sensitivity than the second photoresist film on the second photoresist film;
After the first photoresist film and the second photoresist film are exposed, a development process is performed to form an opening in the second photoresist film larger than the opening of the third photoresist film. And
The first photoresist film exposed inside the opening of the second photoresist film is exposed and developed to form the first slit and the second slit. Item 3. A method for manufacturing a field-effect transistor according to Item 2. 4. The method according to claim 2, wherein the gate electrode is formed of a metal deposited on the first photoresist film. 5. In the gate electrode forming step, a metal is deposited on a wall surface of the second slit to close the second slit in a state where the substrate is tilted with respect to a direction in which the metal atoms fly. 3. The method according to claim 2, wherein a metal is deposited on the etching stopper layer so as to be perpendicular to a direction in which the semiconductor device comes.

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