JP2002198516A - Hemt - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize easily an HEMT having the structure whereby the HEMT can be made fine regardless of conventional scaling rules. SOLUTION: The HEMT has vertical thin-line semiconductor channel layers 12 extending vertically to its substrate surface 10, a carrier feeding layer 13, source and drain electrodes 21, 22, and a gate electrode 23. The vertical thin-line semiconductor channel layer 12 is formed out of the semiconductor of InAs. The carrier feeding layer 13 surrounding the vertical thin-line semiconductor channel layers 12 is formed out of an n-type doped GaAs of the semiconductor doped with an impurity, and the energy bottom of whose conduction band is high in comparison with InAs. The source and drain electrodes 21, 22 are so formed respectively on one-ends side of the vertical thin-line semiconductor channel layers 12 and on their other-ends side that carriers flow through the layers 12. The gate electrode 23 is so formed on the carrier feeding layer 13 surrounding the vertical thin-line semiconductor channel layers 12 so to control the amount of the carriers flowing in the vertical thin-line semiconductor channel layers 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a HEMT (high-level
ctron mobility transisto
r).

[0002]

2. Description of the Related Art At present, a millimeter wave frequency region (30 [GH]
z] to 300 [GHz]), or for the purpose of operating in the sub-millimeter wave frequency range (300 [GHz] to 3 [THz]), studies for further miniaturizing the HEMT have been actively conducted.

[0003] As a material for an ultra-fine HEMT, InAlAs / InGa formed by lattice matching on an InP substrate is used.
The use of As has become mainstream.

The reason is that the electron supply layer InAlA
the discontinuity in the conduction band between Ins as the channel layer and InGaAs is as large as 0.53 [eV];
At high room temperature and high electron saturation speed.

FIG. 11 is a cutaway side view of a main part for explaining a conventional standard HEMT. In FIG.
i-InP substrate on which nAlAs buffer layer is formed, 2
Is i-InGaAs channel layer, 3 is i-InAlAs
The spacer layer, 4 is an n-InAlAs electron supply layer, 5 is a source electrode that is in contact with the channel layer by alloying, 6 is a drain electrode that is in contact with the channel layer by alloying, and 7 is a gate electrode. As shown, a two-dimensional electron gas layer is generated on the channel layer 2 side at the interface between the channel layer 2 and the spacer layer 3.

Conventionally, the high-frequency characteristics of an InAlAs / InGaAs material-based HEMT have a cut-off frequency of 360 [GHz] to 3 [GHz] by employing means for reducing the gate length.
It is reported that 70 [GHz] was obtained.

As described above, although the cutoff frequency has already reached the sub-millimeter wave frequency range, it has been recognized that the improvement in high frequency performance due to miniaturization is reaching a plateau.

One of the reasons is that a scaling rule for avoiding the short channel effect (if necessary, “A
wano et al. , IEEE Trans. ED
-36,2260 (1989)), that is, the ratio (L / d) of the gate length L to the gate-channel distance d.
The gate length is being reduced beyond the range of miniaturization to satisfy the condition of L / d> 5.

In such a case, as the gate length is shortened, the threshold voltage of the element, that is, the gate voltage required to cut off the drain current shifts to the negative side, and the transconductance decreases. Problem arises.

[0010]

SUMMARY OF THE INVENTION The present invention makes it possible to easily realize a HEMT having a structure that can be miniaturized regardless of the conventional scaling law.

[0011]

SUMMARY OF THE INVENTION HEMs according to the prior art
In T, that is, in the HEMT shown in FIG. 11, the gate electrode is formed planarly above the two-dimensional electron layer generated in the channel layer.

On the other hand, in the HEMT of the present invention, a cylindrical gate electrode covering two-dimensional electrons in a channel or two-dimensional electrons in a channel is sandwiched from two directions. It has a gate electrode configured as described above, and is characterized in that controllability of electron flow by the gate electrode is remarkably improved.

In the conventional HEMT, electrons flowing through the channel are two-dimensional.
In the MT, since the channel has a fine line shape, electrons flowing through the channel are one-dimensional, and the electron mobility can be improved.

The channel in the HEMT according to the present invention is not a conventional flat well-shaped channel, but a vertical thin wire channel. Or a sandwich structure from two directions.

By adopting these structures, it is possible to increase the electron mobility and to improve the gate controllability. Further, as compared with the conventional HEMT, the transconductance g _m and the cutoff can be improved. it is possible to improve the performance such as the frequency f _t, furthermore, the area per transistor since it is vertical is reduced, it is possible to increase the integration degree.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view showing a HEMT according to a first embodiment of the present invention. FIG. 1 (A) is a sectional side view of a main part, and FIG. The main part cut planes cut along the -X and viewed from above are shown.

In the figure, 10 is a substrate, 11 is an electrode contact / buffer layer, 12 is a channel layer, 13 is a carrier supply layer (in this case, an electron supply layer), 21 is a source electrode, 22 is a drain electrode, 23 Indicates gate electrodes, respectively.

As is apparent from FIG.
In the EMT, the channel layer 12 is formed in a vertical thin line shape, and the gate electrode 23 is formed so as to surround the thin line channel layer 12 and the carrier supply layer 13.

FIG. 2 shows an HEM according to a second embodiment of the present invention.
It is explanatory drawing showing T, (A) is a principal part cutting side surface,
(B) shows a main part cut-away plane cut down along the line XX seen in (A), and the same symbols and symbols used in FIG. 1 represent the same parts or have the same meanings Have

The difference between the HEMT of the second embodiment and the HEMT of the first embodiment is that the HEMT of the first embodiment is different from the first embodiment.
Then, as can be seen in FIG.
2 is arranged on the circumference, and as a result,
The carrier supply layer 13 has a columnar shape. However, in the HEMT according to the second embodiment, as shown in FIG. 2 (B), the fine channel layer 12 has a form arranged in a straight line. As a result, the carrier supply layer 13 has a plate shape.

Therefore, in the HEMT according to the second embodiment, the gate electrode 23 is provided so as to sandwich the carrier supply layer 13 having a plate shape from two directions.

FIG. 3 shows an HEM according to a third embodiment of the present invention.
It is a principal part cut-away plan view showing T, in which 32 denotes a channel layer, 33 denotes a carrier supply layer, and 43 denotes a gate electrode.

The HEMT according to the third embodiment has a structure in which each thin linear channel layer 32 is surrounded by a gate electrode 43. In such a case, the structure is compared with the first and second embodiments. As a result, the controllability of the current flowing through the fine channel layer 32 by the gate electrode 43 is improved.

FIGS. 4 to 10 show the first embodiment described with reference to FIG. 1 as an example, and show the HEM in a process step for explaining a case of manufacturing the HEMT of the embodiment.
It is a principal part cut side view showing T (only FIG. 5 contains the principal part cut-away plan view), and it demonstrates below, referring these figures.

4 (A) and 4 (B) (1) MBE (Molecular Beam Epi)
By applying the (taxy) method, GaAs (10
0) An n-type doped GaAs electrode contact / buffer layer 11 having a thickness of 200 [nm] is formed on the substrate 10. In this case, Si is used as the n-type dopant, and the doping concentration is, for example, about 5 × 10 ¹⁸ [cm ⁻³ ].
Note that in all the steps described here, the semiconductor growth is not limited to the MBE method, but may be metal organic chemical vapor deposition (meta-metal).
logical chemical vapor
A deposition (MOCVD) method can be applied.

5 (A) and 5 (B) (2) The wafer is taken out of the growth chamber, and an electron beam (el
By applying an electron beam (EB) exposure method, marking is performed by irradiating an electron beam on a portion where a fine line channel layer is to be formed.

As a result, a mark 11A as a trace of electron beam exposure is formed on the surface of the n-type doped GaAs drain electrode contact / buffer layer 11. As a technique for performing marking, in addition to the EB exposure method, for example, a focused ion beam (focused ion beam) is used.
m: FIB) An exposure method may be applied.

Referring to FIG. 6A, (3) The wafer is returned to the growth chamber and InAs is grown on the n-type doped GaAs electrode contact / buffer layer 11 by applying the MBE method. The InAs dots 12A are formed by growing only on 11A. Regarding the growth of the dot 12A on the mark 11A, if necessary, "S. Kohmoto,
T. Ishikawa and K.K. Asakawa,
“InAs-Dot / GaAs Structures
Site-Controlled by in si
tu Electron-Beam Lithograph
phyand Self-Organizing Mo
rectangular Beam Epitaxy Grow
th ", Jpn. J. Appl. Phys. 38, p.
p. 1075-1077 (1999) ".

FIG. 6B (4) Subsequently, by applying the MBE method, the n-type doped GaAs carrier supply layer 13 is formed of InAs dots 1.
Grow to approximately the same height as 2A.

In this case, Si is used as the n-type dopant, and the doping concentration is about 1 × 10 ¹⁸ [cm ⁻³ ].

FIG. 7 (A) (5) By continuing to apply the MBE method, InA
n-type doped GaAs with s dots 12A embedded
InAs is grown on the s carrier supply layer 13.

In this case, although the growth is two-dimensional at first, the height of the InAs dots 12A increases because the InAs further grows three-dimensionally as dots on the InAs dots 12A in the middle.

(6) By continuously applying the MBE method, the n-type doped GaAs carrier supply layer 13 has an increased height of In.
The As dots 12A are grown to the same height as the height of the As dots 12A.

FIG. 8 (7) As described above, formation of the InAs dots 12A,
By repeatedly filling the InAs dots 12A with the n-type doped GaAs carrier supply layer 13, the n-type doped GaAs carrier supply layer 1 as shown in FIG.
A vertical thin linear channel layer 12 surrounded by 3 is realized.

FIG. 9 (8) Chemical vapor deposition (chemical vapor deposition)
A mask made of, for example, SiO ₂ is formed by applying a deposition (CVD) method or a lithography technique.

(9) Reactive ion etching (rea
By applying the active ion etching (RIE) method, the upper surface of the n-type doped GaAs carrier supply layer 13 exposed outside the mask formed in the step (8) is formed. Cut out until you reach.

FIG. 10 (10) AuG having a thickness of 30 [nm] / 300 [nm] by applying a resist process, a vacuum deposition method, and a lift-off method in the lithography technique.
e / Au source electrode 21 and drain electrode 22
To form

(11) A gate electrode 23 made of Al having a thickness of 300 [nm] is formed by applying a resist process, a vacuum deposition method, and a lift-off method in a lithography technique, and is completed. I do.

[0039]

According to the HEMT of the present invention, the vertical thin linear semiconductor channel layer (for example, the vertical thin channel layer 12) extending in the vertical direction with respect to the surface of the substrate (for example, the substrate 10); The semiconductor (for example, I
a carrier supply layer (for example, an n-type doped GaAs carrier supply layer 13) which is composed of a semiconductor having a higher conduction band energy than that of nAs and which is doped with impurities and surrounding the vertical thin semiconductor channel layer. A source electrode (for example, a source electrode 21) and a drain electrode (for example, a drain electrode 22) formed on one end side and the other end side of the vertical thin linear semiconductor channel layer to flow carriers, and the vertical thin linear semiconductor channel layer And a gate electrode (for example, gate electrode 23) formed on a carrier supply layer surrounding and controlling the amount of carriers flowing through the vertical thin linear semiconductor channel layer.

By adopting the above configuration, it is possible to increase the electron mobility and improve the gate controllability, and to improve the performance as a whole as compared with the conventional HEMT. In addition, the area per transistor is small because of the vertical type,
It is possible to increase the degree of integration.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram illustrating a HEMT according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a HEMT according to a second embodiment of the present invention.

FIG. 3 is a fragmentary plan view showing a HEMT according to a third embodiment of the present invention;

FIG. 4 is a fragmentary side view showing the HEMT at a key step in the process for explaining the case where the HEMT of the embodiment is manufactured.

5A and 5B are a main part cut-away side view and a main part cut-away plan view showing the HEMT at a key point in the process for explaining a case where the HEMT of the embodiment is manufactured.

FIG. 6 is a fragmentary side view showing the HEMT at a key point in the process for explaining a case where the HEMT of the embodiment is manufactured.

FIG. 7 is an essential part cutaway side view showing the HEMT at a key step in the process for explaining the case where the HEMT of the embodiment is manufactured.

FIG. 8 is a fragmentary side elevational view showing the HEMT at a key step in the process for explaining the case where the HEMT of the embodiment is manufactured.

FIG. 9 is a fragmentary side view showing the HEMT at a key step in the process for explaining the case where the HEMT of the embodiment is manufactured.

FIG. 10 is a fragmentary side view showing the HEMT at a key point in the process for explaining a case where the HEMT of the embodiment is manufactured.

FIG. 11 is a cutaway side view of a main part for explaining a conventional standard HEMT.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Substrate 11 Electrode contact / buffer layer 11A mark 12 Channel layer 12A InAs dot 13 Carrier supply layer (electron supply layer in this case) 21 Source electrode 22 Drain electrode 23 Gate electrode 32 Channel layer 33 Carrier supply layer 43 Gate electrode

Claims (5)

[Claims] 1. A vertical thin linear semiconductor channel layer extending in a vertical direction with respect to a substrate surface, and an energy bottom of a conduction band is higher than that of a semiconductor constituting the vertical thin linear semiconductor channel layer and impurities are contained. A carrier supply layer composed of a doped semiconductor and surrounding the vertical thin semiconductor channel layer; a source electrode and a drain electrode formed at one end and the other end of the vertical thin semiconductor channel layer to flow carriers. And a gate electrode formed on a carrier supply layer surrounding the vertical thin linear semiconductor channel layer and controlling the amount of carriers flowing through the vertical thin linear semiconductor channel layer. 2. The HEMT according to claim 1, wherein the gate electrode has a cylindrical shape surrounding the vertical thin linear semiconductor channel layer. 3. The HEMT according to claim 1, wherein the gate electrode is formed so as to sandwich the vertical thin semiconductor channel layer from two directions. 4. The HE according to claim 1, wherein the number of the vertical thin semiconductor channel layers in which the amount of carriers flowing by the gate electrode is controlled is one or more.
MT. 5. The HEMT according to claim 1, wherein each of the vertical thin linear gate electrodes is surrounded by a gate electrode.