JP2000012563A - Field effect semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect semiconductor device wherein a threshold voltage varies little even if the thickness of metal constituting a gate electrode disperses, in a device of a constitution wherein metal constituting a gate electrode diffuses to a barrier layer. SOLUTION: In the semiconductor device, an n-type GaAs layer 3 and a barrier layer are formed on a GaAs board 1 one by one, a gate electrode 10 is formed on the barrier layer, and Pt constituting the gate electrode 10 diffuses to a barrier layer. The barrier layer is formed of a first AlGaAs layer 4 and a second AlGaAs layer 5, and the first AlGaAs layer 4 is a semiconductor material wherein Pt is hard to diffuse when compared to the second AlGaAs layer 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a field effect type semiconductor device having a gate electrode.

[0002]

2. Description of the Related Art In a field effect type semiconductor device such as a MESFET (metal-semiconductor field effect transistor) or a HEMT (high electron mobility transistor) made of a III-V compound semiconductor such as GaAs, an operation layer made of a semiconductor is used. A gate electrode that makes a Schottky junction is used.

FIG. 14 is a schematic sectional view showing an example of a conventional field effect transistor. This field effect transistor has a structure in which a gate electrode is embedded in a semiconductor layer.

In FIG. 14, a GaAs buffer layer 102, a GaAs channel layer 103 doped with Si, an AlGaAs layer 105,
A GaAs layer 106 is formed in order. First and second high-concentration regions 107a and 107b made of n + layers are formed at predetermined intervals in each layer. The source electrode 10 is formed on the first and second high-concentration regions 107a and 107b, respectively.
8. A drain electrode 109 is formed. Between the source electrode 108 and the drain electrode 109, the gate electrode 1
10 are formed.

The gate electrode 110 has a Pt layer 110a and another metal layer 110b laminated on a GaAs layer 106, and a Pt diffusion layer 110c formed by diffusing the Pt layer 110a below the Pt layer 110a. Is formed. Pt
The diffusion layer 110c is formed by heat treatment, and the GaAs layer 1
06 and reaches halfway through the AlGaAs layer 105.

The gate electrode 11 having such a diffusion layer
Field effect transistor using the source electrode 8a.
It is known that the parasitic resistance between the gate electrode 10 and the gate electrode 10 decreases, the transconductance gm increases, and the current cutoff frequency, that is, the usable frequency increases.

On the other hand, controlling the threshold voltage of a transistor is one of the most important items in configuring a microwave circuit or a digital circuit. In controlling such a threshold voltage, the gate electrode and the channel layer are controlled. It is necessary to keep a constant distance from the vehicle.

In the gate electrode 110 described above, it is known that Pt diffuses to a depth of about twice the thickness of the Pt layer 110a reacting with the semiconductor to form a Pt diffusion layer 110c. Therefore, there is a problem that the depth of the Pt diffusion layer 110c also varies according to the variation of the thickness of the Pt layer 110a, and as a result, the threshold voltage of the transistor varies.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned drawbacks of the prior art, and has been made in consideration of the above-described drawbacks. It is an object to provide a semiconductor device.

[0010]

According to the field effect type semiconductor device of the present invention, a channel layer and a barrier layer are sequentially formed on a semiconductor substrate, and a gate electrode is formed on the semiconductor layer to form the gate electrode. In a field-effect type semiconductor device in which metal is diffused to the barrier layer, the barrier layer includes a first barrier layer and a second barrier layer, and the first barrier layer connects the gate electrode to the second barrier layer. It is characterized in that the constituent metal is made of a semiconductor material that is difficult to diffuse.

In the field-effect semiconductor device having such a configuration, the metal constituting the gate electrode is suppressed from diffusing in the second barrier layer. Variations in the diffusion amount of the metal in the second barrier layer are reduced.

Further, the field-effect semiconductor device of the present invention
The second barrier layer is formed of a semiconductor layer having a lower resistance than the first barrier layer.

Thus, even if the thickness of the barrier layer is increased, the barrier layer is prevented from increasing in resistance.

Further, the field-effect semiconductor device of the present invention
The first barrier layer is formed closer to the channel layer than the second barrier layer.

In this case, the diffusion of the metal constituting the gate electrode is suppressed in the first barrier layer.
The setting of the layer thickness and the doping concentration of the semiconductor layer including the channel layer located closer to the substrate than the barrier layer becomes easy.

In the field effect type semiconductor device of the present invention, Pt is suitable as a metal constituting the gate electrode and diffusing to the barrier layer.

Further, in the field-effect semiconductor device according to the present invention, the first and second barrier layers are made of AlGaAs, and the first barrier layer has a higher Al ratio (ratio) than the second barrier layer. It is characterized by.

In this case, compared to the second barrier layer, the first barrier layer is less likely to diffuse the metal constituting the gate electrode such as Pt, and the variation in the distance between the gate electrode and the channel layer is reduced.

Also, the field effect type semiconductor device of the present invention
The first and second barrier layers are made of InAlAs, and the first barrier layer has a smaller In ratio (ratio) than the second barrier layer.

Also in this case, compared to the second barrier layer, the first barrier layer is less likely to diffuse the metal constituting the gate electrode such as Pt, and the variation in the distance between the gate electrode and the channel layer is reduced.

Further, the field-effect semiconductor device of the present invention
The first and second barrier layers are made of InGaP;
The barrier layer is characterized in that the ratio (ratio) of In is smaller than that of the second barrier layer.

Also in this case, compared to the second barrier layer, the metal constituting the gate electrode such as Pt is less likely to diffuse in the first barrier layer, and the variation in the distance between the gate electrode and the channel layer is reduced.

Also, the field effect type semiconductor device of the present invention
A first operation unit in which a channel layer and a barrier layer are sequentially formed on a semiconductor substrate, a first gate electrode is formed on the barrier layer, and a metal forming the first gate electrode is diffused to the barrier layer; A second operation unit in which a channel layer and a barrier layer are sequentially formed on the semiconductor substrate, the barrier layer has a second gate electrode, and a metal forming the second gate electrode is not diffused to the barrier layer; In the field effect type semiconductor device, the barrier layer on the first operation unit side includes a first barrier layer and a second barrier layer, and the first barrier layer is formed of the first gate electrode as compared with the second barrier layer. It is characterized by being made of a semiconductor material in which metal is difficult to diffuse.

The field effect type semiconductor device having such a configuration has the first operating section and the second operating section having different threshold voltages from each other, and furthermore, the distance between the gate electrode and the channel layer in the first operating section. Is small, the variation of the threshold voltage in the first operating section is small, and the distance between the gate electrode and the channel layer in the second operating section is
Since the threshold voltage is determined by the thickness of the layer between the gate electrode and the channel layer, the threshold voltage in the second operation section can be set accurately.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing the structure of a field effect type semiconductor device according to a first embodiment of the present invention.
The field effect type semiconductor device of the first embodiment is a field effect transistor using a GaAs substrate.
Above is undoped GaAs functioning as a buffer layer.
A layer 2 is formed, an n-type GaAs layer 3 functioning as a channel layer is formed on the GaAs layer 2, and a first AlGaAs layer 4 functioning as a barrier layer is formed on the n-type GaAs layer 3.
Is formed, a second AlGaAs layer 5 functioning as a barrier layer is formed on the first AlGaAs layer 4, and an undoped GaAs layer for improving the breakdown voltage of the gate electrode is formed on the second AlGaAs layer 5. 6 are formed, and these layers constitute a semiconductor wafer. The thickness of each layer is 800 nm for the GaAs layer 2 and n-type GaAs.
Layer 3 is 25 nm, first AlGaAs layer 4 is 15 nm,
The second AlGaAs layer 5 has a thickness of 15 nm, and the GaAs layer 6 has a thickness of 1 nm.
0 nm. Further, the n-type GaAs layer 3 contains 2.5% Si.
It is formed by doping at × 10 ¹⁸ cm ⁻³ . Further, the composition ratio of the first AlGaAs layer 4 is Al _{0 .4} G
a _0.6 As, the composition ratio of the second AlGaAs layer 5 is Al _0.2
Ga _0.8 As, and the first AlGaAs layer
The ratio of Al is higher than that of the lGaAs layer 5.

The first and second AlGaAs layers 4 and 5 have a much larger potential barrier than the n-type GaAs layer 3 and function as barrier layers. Also, the second AlGaAs
The layer 5 has a lower resistance than the first AlGaAs layer 4 and suppresses the increase in resistance of the barrier layer.

In each of the layers 2, 3, 4, 5, and 6, high concentration regions 7a and 7b made of n ⁺ layers are formed at predetermined intervals. The high concentration regions 7a and 7b are regions where Si is ion-implanted and activated to reduce the parasitic resistance. A source electrode 8 is formed on the high concentration region 7a, and a drain electrode 9 is formed on the high concentration region 7b.

A gate electrode 10 made of Pt is formed between the source electrode 8 and the drain electrode 9.

The gate electrode 10 is composed of a Pt layer 10a, a Ti layer 10b, a Pt layer 10c,
An Au layer 10d is laminated, and the Pt layer
A Pt diffusion layer 10e formed by diffusing the t layer 10a is formed. The Pt diffusion layer 10e is formed by a heat treatment,
It passes through the GaAs layer 6 and the second AlGaAs layer 5 and reaches halfway through the first AlGaAs layer 4. The thickness of each layer of the gate electrode 10 is 20 nm for the Pt layer 10a and T
i-layer 10b is 10 nm, Pt layer 10c is 20 nm, Au
The layer 10d is 400 nm, and the Pt diffusion layer 10e is Ga
It diffuses from the surface of the As layer 6 to a depth of about 27 nm. In FIG. 1, 11 is a SiN film and 12 is SiO
_Two films.

Next, a method of manufacturing the field effect type semiconductor device of the first embodiment shown in FIG. 1 will be described.

First, as shown in FIG.
GaAs layer 2, n-type GaAs layer 3, first AlG
After sequentially forming the aAs layer 4, the second AlGaAs layer 5, and the GaAs layer 6, a SiN film 11 is formed to a thickness of about 50 nm, and then a resist 13 is formed at a predetermined position.
Ion implantation is performed to form high concentration regions 7a and 7b.

Next, as shown in FIG. 3, after the resist 13 is etched by oxygen plasma to make the resist 13 thin, an SiO ₂ film 12 is formed by plasma CVD.

Next, as shown in FIG. 4, after removing the SiO ₂ film 12 deposited on the side wall of the resist 13 by HF, the resist 13 is removed by a lift-off method.

Next, as shown in FIG. 5, after the SiO ₂ film 12 and the SiN film 11 on the high concentration regions 7a and 7b are removed by etching using a resist pattern, an AuGe layer, a Ni layer, and an Au After forming the source electrode 8 and the drain electrode 9 formed by stacking the layers, the source electrode 8 and the drain electrode 9 are patterned by a lift-off method, and then heat treatment is performed.

Next, as shown in FIG. 6, the SiO ₂ film 12 and the Si
After the N film 11 is removed by etching, a gate electrode 10 formed by stacking a Pt layer 10a, a Ti layer 10b, a Pt layer 10c, and an Au layer 10d in this order from below is formed by vapor deposition and lift-off. Thereafter, by performing a heat treatment at 380 ° C. for 3 minutes, the lowermost Pt layer is diffused and the Pt diffusion layer 10 is formed.
is formed, and the above-described field-effect semiconductor device shown in FIG. 1 is completed.

FIG. 7 is a diagram showing the result of examining the diffusion state of the Pt layer with respect to the Al _x Ga _{1 -x} As layer at 380 ° C. where Pt reacts with the AlGaAs layer. 7, the vertical axis represents the Pt diffusion concentration obtained from the Auger signal, and the horizontal axis represents the depth from the surface of the AlGaAs layer. At this time, the thickness of the Pt layer is 100 nm.

As can be seen from FIG. 7, Al _x Ga _{1 -x} As
The diffusion depth becomes shallower as the value of x becomes larger. That is, the content of Al increases and the forbidden band width is large.
It can be seen that the diffusion of Pt is smaller in the lGaAs layer.
Here, Pt reacts with the AlGaAs layer in a range of 300 to 450.
At other temperatures in ° C., similar results as described above were obtained.

Therefore, in the field effect type semiconductor device of the first embodiment, even if the thickness of the Pt layer 10a in the gate electrode 10 varies, the diffusion of the Pt diffusion layer 10e has a large Al content. It is suppressed by the AlGaAs layer 4. Therefore, even if the thickness of the Pt layer 10a in the gate electrode 10 varies, the diffusion amount of the Pt diffusion layer 10e in the first AlGaAs layer 4 has little variation, and the gate electrode 10 and n-type GaAs serving as a channel layer are formed. The change in the distance from the layer 3 is also small, and variation in the threshold voltage can be suppressed.

Next, the field effect type semiconductor device according to the first embodiment and the field effect type semiconductor device having the conventional structure as a comparative example are respectively manufactured by ten each. For the device, the average value of the transconductance, the average value of the gate breakdown voltage, the average value of the threshold voltage, and the standard deviation of the threshold voltage were examined, and the results are shown in Table 1.

The field effect type semiconductor device having the conventional structure has a structure as shown in FIG. 8, and is different from the first semiconductor device in that the first AlGaAs layer 4 is not interposed on the n-type GaAs layer 3. In the conventional structure, the thickness of the second AlGaAs layer 5 was set to 30 nm.

[0042]

[Table 1]

As can be seen from Table 1, the average value of the mutual conductance, the average value of the gate breakdown voltage, and the average value of the threshold voltage of the field effect type semiconductor device of the first embodiment are substantially the same as those of the conventional structure. However, the standard deviation of the threshold voltage is much smaller, the variation of the threshold voltage is small,
Are better. This is because, as described above, in the field effect type semiconductor device of the first embodiment, the diffusion of the Pt diffusion layer 10e is A
The first AlGaAs layer 4 in which the proportion of Al in lGa is large is suppressed, and the gate electrode 10 and n serving as a channel layer are suppressed.
This is because variation in the distance from the GaAs layer 3 is suppressed.

Next, a description will be given of a field-effect semiconductor device according to a second embodiment of the present invention.

FIG. 9 shows a field-effect type half of a second embodiment of the present invention.
It is sectional drawing which shows the structure of a conductor device. In the second embodiment,
A field effect semiconductor device is a field effect transistor using an InP substrate.
And a buffer layer on the InP substrate 21.
Undoped InAlAs layer 22 which functions as
And functions as a channel layer on the InAlAs layer 22.
N-type InGaAs layer 23 is formed, and n-type InGaAs
A first InAlAs layer 24 is formed on the s layer 23,
On the first InAlAs layer 24, a second InAlAs layer
25 is formed on the second InAlAs layer 25.
Undoped InP layer to improve breakdown voltage of gate electrode
26, and the semiconductor wafer is formed by these layers.
Is configured. The thickness of each of the layers is an InAlAs layer.
22 is 800 nm, n-type InGaAs layer 23 is 12 n
m, the first InAlAs layer 24 has a thickness of 12 nm,
The AlAs layer 25 has a thickness of 18 nm, and the InP layer 6 has a thickness of 10 nm.
You. Further, the n-type InGaAs layer 23 is made of 5 × 10¹⁸
cm^-3It is formed by doping. Ma
The composition ratio of the first InAlAs layer 24 is In_0.35Al
_0.65As, the composition ratio of the second InAlAs layer 25 is In.
_0.52Al_0.48As, and the first InAlAs layer 24 is
The ratio of In is smaller than that of the second InAlAs layer 25.

The first and second InAlAs layers 24 and 25 have a much higher potential barrier than the n-type InGaAs layer 23 and function as barrier layers. Also, the second InA
The lAs layer 25 has a lower resistance than the first InAlAs layer 24 and suppresses the increase in resistance of the barrier layer.

Each of the layers 22, 23, 24, 25 and 26 has a high-concentration region 27 made of an n ⁺ layer at a predetermined interval.
a and 27b are formed. High concentration regions 27a, 27
b is a region where Si is ion-implanted and activated to reduce the parasitic resistance. The source electrode 28 is on the high concentration region 27a, and the drain electrode 2 is on the high concentration region 27b.
9 are formed respectively.

The source electrode 28 and the drain electrode 29
Between them, a gate electrode 30 is formed.

The gate electrode 30 includes a Pt layer 30a, a Ti layer 30b, a Pt layer 30c,
An Au layer 30d is laminated, and the P layer is formed below the Pt layer 30a.
A Pt diffusion layer 30e formed by diffusing the t layer 30a is formed. The Pt diffusion layer 30e is formed by heat treatment,
Passing through the InP layer 26 and the second InAlAs layer 25,
The first InAlAs layer 24 reaches halfway. The thickness of each layer of the gate electrode 30 is 20 nm for the Pt layer 30a,
Ti layer 30b is 10 nm, Pt layer 30c is 20 nm, A
u layer 30d is 400 nm, and Pt diffusion layer 30e is I
It diffuses from the surface of the nP layer 26 to a depth of about 27 nm. In FIG. 9, reference numeral 31 denotes a SiN film, and 32 denotes a SiN film.
O ₂ film.

The method of manufacturing the field-effect semiconductor device of the second embodiment is almost the same as that of the first embodiment except that the semiconductor material is different, and the description is omitted here.

Next, ten each of the field effect type semiconductor device of the second embodiment and the field effect type semiconductor device of the conventional structure as a comparative example were prepared. For the device, the average value of the transconductance, the average value of the gate breakdown voltage, the average value of the threshold voltage, and the standard deviation of the threshold voltage were examined. The results are shown in Table 2.

The field effect type semiconductor device having the conventional structure has a structure as shown in FIG. 10, and the difference from the semiconductor device of the second embodiment is that the first InA layer is formed on the n-type InGaAs layer 23.
The point is that the second InAlAs layer 25 is formed without the interposition of the lAs layer 24. In the conventional semiconductor device, the second
The thickness of the InAlAs layer 25 was 30 nm.

[0053]

[Table 2]

As can be seen from Table 2, the average value of the mutual conductance, the average value of the gate breakdown voltage, and the average value of the threshold voltage of the field effect type semiconductor device of the second embodiment are substantially the same as those of the conventional structure. However, the standard deviation of the threshold voltage is much smaller, the variation of the threshold voltage is small,
Are better. This is because, in the field-effect semiconductor device of the second embodiment, the diffusion of the Pt diffusion layer
The first InAlAs layer 24 in which the ratio of n is small is suppressed, and the gate electrode 30 and n-type InGa to be a channel layer are suppressed.
This is because variation in the distance from the As layer 23 was suppressed.

Next, a description will be given of a field effect type semiconductor device according to a third embodiment of the present invention.

FIG. 11 is a sectional view showing the structure of a field-effect semiconductor device according to a third embodiment of the present invention. The field effect type semiconductor device according to the third embodiment is a field effect transistor using a GaAs substrate. An undoped GaAs layer 42 functioning as a buffer layer is formed on a GaAs substrate 41, and a channel is formed on the GaAs layer 42. An n-type GaAs layer 43 functioning as a layer is formed, a first InGaP layer 44 is formed on the n-type GaAs layer 43, and a first InG
A second InGaP layer 45 is formed on the aP layer 44,
An undoped GaAs layer 46 for improving the breakdown voltage of the gate electrode is formed on the second InGaP layer 45, and these layers constitute a semiconductor wafer. The GaAs layer 42 has a thickness of 800 nm,
The n-type GaAs layer 43 has a thickness of 25 nm, and the first InGaP layer 4 has a thickness of 25 nm.
4 is 12 nm, the second InGaP layer 45 is 18 nm,
The thickness of the aAs layer 46 is 10 nm.

Further, the n-type GaAs layer 43 contains 2.5% of Si.
It is formed by doping at × 10 ¹⁸ cm ⁻³ . The composition ratio of the first InGaP layer 44 is In _0.35
Ga _{0 .65} P, the composition ratio of the second InGaP layer 45 is In
_0.49 Ga _0.51 P, and the first InGaP layer 44 is
Is smaller than that of the InGaP layer 45.

The first and second InGaP layers 44 and 45 have n
The potential barrier is much larger than that of the GaAs layer 43 and functions as a barrier layer. Also, the second InGaP
The layer 45 has a lower resistance than the first InGaP layer 44,
High resistance of the barrier layer is suppressed.

Each of the layers 42, 43, 44, 45 and 46 has a high-concentration region 47 made of an n ⁺ layer at a predetermined interval.
a, 47b are formed. High concentration areas 47a, 47
b is a region where Si is ion-implanted and activated to reduce the parasitic resistance. The source electrode 48 is formed on the high concentration region 47a, and the drain electrode 4 is formed on the high concentration region 47b.
9 are formed respectively. A gate electrode 50 is formed between the source electrode 48 and the drain electrode 49.

The gate electrode 50 includes a Pt layer 50a, a Ti layer 50b, and a Pt layer 50
c, an Au layer 50d is laminated, and a Pt diffusion layer 50e formed by diffusing the Pt layer 50a is formed below the Pt layer 50a. The Pt diffusion layer 50e is formed by a heat treatment, passes through the GaAs layer 46 and the second InGaP layer 45, and reaches halfway through the first InGaP layer 44. The thickness of each layer of the gate electrode 50 is 20 nm for the Pt layer 50a,
Ti layer 50b is 10 nm, Pt layer 50c is 20 nm, A
The u layer 50d is 400 nm, and the Pt diffusion layer 50e is G
It diffuses from the surface of the aAs layer 46 to a depth of about 27 nm. In FIG. 11, reference numeral 31 denotes a SiN film, and 32 denotes a SiO ₂ film.

The method of manufacturing the field-effect semiconductor device of the third embodiment is almost the same as that of the first embodiment except that the semiconductor material is different, and the description is omitted here.

Next, ten each of the field effect type semiconductor device of the third embodiment and the field effect type semiconductor device of the conventional structure as a comparative example were prepared. For the device, the average value of the transconductance, the average value of the gate breakdown voltage, the average value of the threshold voltage, and the standard deviation of the threshold voltage are examined, and the results are shown in Table 3.

The field effect type semiconductor device of the conventional structure has a structure as shown in FIG. 12, and the difference from the semiconductor device of the third embodiment is that the first InGaP layer is formed on the n-type GaAs layer 43.
The point is that the second InGaP layer 45 is formed without the layer 44 interposed therebetween. In the conventional semiconductor device, the second InG
The layer thickness of the aP layer 45 was 30 nm.

[0064]

[Table 3]

As can be seen from Table 3, the average value of the mutual conductance, the average value of the gate breakdown voltage, and the average value of the threshold voltage of the field effect type semiconductor device of the third embodiment are substantially the same as those of the conventional structure. However, the standard deviation of the threshold voltage is much smaller, the variation of the threshold voltage is small,
Are better. This is because in the field-effect semiconductor device of the third embodiment, the diffusion of the Pt diffusion layer
The gate electrode 50 and the n-type GaAs layer 43 serving as a channel layer are suppressed by the first InGaP layer 44 having a small n ratio.
This is because variation in the distance between them is suppressed.

Next, a description will be given of a field-effect type semiconductor device according to a fourth embodiment of the present invention.

FIG. 13 is a sectional view showing the structure of a field-effect semiconductor device according to a fourth embodiment of the present invention. The field-effect semiconductor device of the fourth embodiment is a field-effect transistor having a first operation unit and a second operation unit having different threshold voltages on a common GaAs substrate.

In this field effect type semiconductor device, the common G
An undoped GaAs layer 62 functioning as a buffer layer is formed on an aAs substrate 61, and an n-type GaAs functioning as a channel layer of a first operation unit is formed on the GaAs layer 62.
A layer 63A and an n-type GaAs layer 63B functioning as a channel layer of the second operation section are formed. n-type GaAs layer 6
3A and the n-type GaAs layer 63B are separated via a separation groove 73 formed on the GaAs layer 62.

On one n-type GaAs layer 63A, a first AlGaAs layer 64A is formed.
A second AlGaAs layer 65A is formed on the layer 64A, and an undoped GaAs layer 66A for improving the breakdown voltage of the gate electrode is formed on the second AlGaAs layer 65A. A semiconductor wafer on the operation section side is configured.

A first AlGaAs layer 64B is formed on the other n-type GaAs layer 63B.
A second AlGaAs layer 65B is formed on the aAs layer 64B, and an undoped GaAs layer 66 for improving the breakdown voltage of the gate electrode is formed on the second AlGaAs layer 65B.
B are formed, and these layers constitute a semiconductor wafer on the second operation unit side.

The thickness of each layer, the n-type GaAs layer 63A,
The doping amount of 63B is the same as in the first embodiment.

Each layer 62, 63A, 64 on the first operation section side
In A, 65A and 66A, high concentration regions 67Aa and 67Ab made of an n ⁺ layer are formed at predetermined intervals.
The high-concentration regions 67Aa and 67Ab are regions where Si is ion-implanted and activated to reduce the parasitic resistance.
A source electrode 68A is formed on the high concentration region 67Aa, and a drain electrode 69A is formed on the high concentration region 67Ab.

The source electrode 68A and the drain electrode 6
9A, a gate electrode (first gate electrode) 70A
Are formed.

The gate electrode 70A is formed on the GaAs layer 66 from the bottom in the order of a Pt layer 70a, a Ti layer 70b, and a Pt layer 70.
c, an Au layer 70d is laminated, and a Pt diffusion layer 70e formed by diffusing the Pt layer 70a is formed below the Pt layer 70a. The Pt diffusion layer 70e is formed by a heat treatment, passes through the GaAs layer 66A, the second AlGaAs layer 65A, and reaches halfway through the first AlGaAs layer 64A. The thickness of each layer of the gate electrode 70 is the Pt layer 70a.
Is 20 nm, the Ti layer 70b is 10 nm, the Pt layer 70c is 20 nm, the Au layer 70d is 40 nm, and the Pt diffusion layer 70e is diffused from the surface of the GaAs layer 76 to a depth of about 27 nm.

Each of the layers 62 and 63B on the side of the second operation section,
In 64B, 65B, and 66B, high-concentration regions 67Ba and 67Bb made of an n ⁺ layer are formed at predetermined intervals. The high-concentration regions 67Ba and 67Bb are regions where Si is ion-implanted and activated to reduce the parasitic resistance. A source electrode 68B is formed on the high concentration region 67Ba, and a drain electrode 69B is formed on the high concentration region 67Bb.

The source electrode 68B and the drain electrode 6
9B, a gate electrode (second gate electrode) 70B
Are formed.

The gate electrode 70B is formed on the GaAs layer 66 in this order from the bottom to the Ti layer 70f, the Pt layer 70g, and the Au layer 70.
h are stacked. Note that no diffusion layer is formed below the Ti layer 70f. In FIG. 13, reference numeral 71 denotes S
The iN film 72 is a SiO ₂ film.

Next, ten field-effect semiconductor devices according to the above-described fourth embodiment were manufactured, and the average value of the mutual conductance, the average value of the gate breakdown voltage, and The average value of the threshold voltage is checked, and the result is shown in Table 4.
Shown in

[0079]

[Table 4]

As can be seen from Table 4, in the field effect type semiconductor device of the fourth embodiment, the threshold voltages of the first operating section and the second operating section are different. That is, the field effect semiconductor device of the fourth embodiment functions as a semiconductor device having two types of threshold voltages.

In the above embodiment, the barrier layer is composed of two semiconductor layers, but may be composed of three or more semiconductor layers.

The present invention also relates to the MESFET of the above embodiment.
H having an electron supply layer and a channel layer
The present invention is also applicable to a field effect type semiconductor device having an EMT structure.

[0083]

According to the present invention, it is possible to provide a field effect type semiconductor device in which the variation in threshold voltage is small and the threshold voltage can be easily and accurately set.

Further, according to the present invention, it is possible to provide a field effect type semiconductor device having a plurality of gate electrodes having different threshold voltages and being set with high accuracy.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a field-effect semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a method of manufacturing the field-effect semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating a method of manufacturing the field-effect semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a method of manufacturing the field-effect semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a view illustrating a method of manufacturing the field-effect semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a diagram illustrating a method of manufacturing the field-effect semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a diagram showing a state of diffusion of Pt into an AlGaAs layer.

FIG. 8 is a cross-sectional view illustrating a configuration of a field-effect semiconductor device of a comparative example with respect to the first embodiment.

FIG. 9 is a cross-sectional view illustrating a configuration of a field-effect semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a cross-sectional view illustrating a configuration of a field-effect semiconductor device of a comparative example with respect to the second embodiment.

FIG. 11 is a sectional view showing a configuration of a field-effect semiconductor device according to a third embodiment of the present invention.

FIG. 12 is a sectional view showing a configuration of a field-effect semiconductor device of a comparative example with respect to the third embodiment.

FIG. 13 is a sectional view showing a configuration of a field-effect semiconductor device according to a fourth embodiment of the present invention.

FIG. 14 is a cross-sectional view illustrating a configuration of a conventional field-effect semiconductor device.

[Explanation of symbols]

 Reference Signs List 1 GaAs substrate (semiconductor substrate) 3 GaAs layer (channel layer) 4 First AlGaAs layer (first barrier layer) 5 Second AlGaAs layer (second barrier layer) 10 Gate electrode 10a Pt layer (constituting gate electrode) Metal) 10 e Pt diffusion layer 21 InP substrate (semiconductor substrate) 23 InGaAs layer (channel layer) 24 first InAlAs layer (first barrier layer) 25 second InAlAs layer (second barrier layer) 30 gate electrode 30 a Pt layer (Metal constituting gate electrode) 30e Pt diffusion layer 41 GaAs substrate (semiconductor substrate) 43 GaAs layer (channel layer) 44 First InGaP layer (first barrier layer) 45 Second InGaP layer (second barrier layer) Reference Signs List 50 gate electrode 50a Pt layer (metal constituting gate electrode) 50e Pt diffusion layer 61 GaAs substrate (semiconductor substrate) 63 GaAs layer (channel layer) 63B GaAs layer (channel layer) 64A First AlGaAs layer (first barrier layer) 64B First AlGaAs layer (first barrier layer) 65A Second AlGaAs layer (second barrier layer) 65B Second AlGaAs layer (second barrier layer) 70A Gate electrode (first gate electrode) 70a Pt layer (metal constituting gate electrode) 70e Pt diffusion layer 70B Gate electrode (second gate electrode) 70f Pt layer (gate electrode) Make up the metal)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Shigeyuki Murai 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd. (72) Inventor Hisaaki Tominaga 2-5-5 Keihanhondori, Moriguchi-shi, Osaka No. 5 Sanyo Electric Co., Ltd. F term (reference) 4M104 AA05 BB05 BB06 BB09 BB10 BB14 CC01 CC03 DD16 DD17 DD34 DD68 FF07 GG12 5F102 GB01 GC01 GD01 GJ05 GJ06 GK04 GK05 GL04 GL04 GL05 GM04 GM05 G04 G09 G04 G09 HC07 HC15 HC19

Claims (8)

[Claims] 1. A field effect semiconductor in which a channel layer and a barrier layer are sequentially formed on a semiconductor substrate, a gate electrode is formed on the barrier layer, and a metal forming the gate electrode is diffused to the barrier layer. In the device, the barrier layer includes a first barrier layer and a second barrier layer, and the first barrier layer is made of a semiconductor material in which a metal forming the gate electrode is less likely to diffuse than the second barrier layer. Field-effect type semiconductor device. 2. The semiconductor device according to claim 1, wherein the second barrier layer is made of a semiconductor material having a lower resistance than the first barrier layer.
The field-effect-type semiconductor device according to the above. 3. The field effect semiconductor device according to claim 1, wherein said first barrier layer is formed closer to said channel layer than said second barrier layer. 4. The field-effect semiconductor device according to claim 1, wherein the metal constituting said gate electrode is Pt. 5. The semiconductor device according to claim 1, wherein the first and second barrier layers are made of AlGaAs, and the first barrier layer has a higher Al content than the second barrier layer.
The field-effect-type semiconductor device according to the above. 6. The method according to claim 1, wherein the first and second barrier layers are made of InAlAs, and the first barrier layer has a smaller proportion of In than the second barrier layer.
The field-effect-type semiconductor device according to the above. 7. The method according to claim 1, wherein the first and second barrier layers are made of InGaP, and the first barrier layer has a smaller proportion of In than the second barrier layer. The field-effect-type semiconductor device according to the above. 8. A semiconductor device comprising: a channel layer and a barrier layer formed in this order on a semiconductor substrate; a first gate electrode formed on the barrier layer; and a metal forming the first gate electrode diffused to the barrier layer. 1 operation part, a channel layer on the semiconductor substrate,
A field effect type semiconductor device comprising: a barrier layer formed in order; a second gate electrode formed on the barrier layer; and a second operating portion in which a metal forming the second gate electrode is not diffused to the barrier layer. , The barrier layer on the first operation unit side is a first barrier.
A field effect type semiconductor device comprising a barrier layer and a second barrier layer, wherein the first barrier layer is made of a semiconductor material in which the metal of the first gate electrode is less likely to diffuse than the second barrier layer.