JP2003059943A - Semiconductor device and production method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a production method therefor with which the processes of high productivity can be provided, controllability in gate length line width is improved and an effective gate length is extremely fine. SOLUTION: A gate formation layer (undoped GaAs) having a step 15 is formed on a channel layer (n-type GaAs) 13, the step 15 is positioned between a source electrode 21 and a drain electrode 22, a channel layer 13 and an opposite conductivity type diffusion region (p-type GaAs) 17a are formed on a sidewall 15a of the step 15, and a gate electrode 20 is connected to that diffusion region 17a.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more specifically, to a junction type field effect transistor (FET) having a pn junction interposed between a channel layer and a gate electrode. Regarding gate length reduction technology.

[0002]

2. Description of the Related Art FETs that are finer, operate at high speed, and have low noise
To realize the above, it is required to shorten the gate length. However, in patterning by a light exposure technique generally used for pattern formation, for example, 0.15 μm
There is a limit to forming the following gate length. Therefore,
Conventionally, the following three methods have been mainly used as a method for forming a finer gate length.

(Conventional Example 1) This is a so-called direct writing method. A gate pattern is directly drawn on an electron beam resist by an electron beam to form a fine width opening, and the resist having the fine width opening is formed. A gate pattern is formed by using.

(Conventional Example 2) As shown in FIG. 11D,
A side wall 4a made of an insulator is formed in the opening 3 formed in the SiN layer 2 which is an insulating layer by an optical exposure technique to narrow the opening width, and the narrowed opening 3a is filled with a metal 5 to be a gate electrode. To form.

First, as shown in FIG. 11A, for example, a SiN layer 2 is formed on a GaAs layer 1 as a channel layer, and an opening 3 is formed in the SiN layer 2 by a light exposure technique and etching. Then, as shown in FIG. 11B, Si
The SiN layer 4 is formed on the N layer 2 by the CVD method. At this time, the SiN layer 4 is also formed on the bottom and side walls of the opening 3. Then, as shown in FIG. 11C, RIE (Reactive
The SiN layer 4 is anisotropically etched by the Ion Etching method so that only the sidewall 4a remains. As a result, the opening 3a having a minute width is obtained. Then, as shown in FIG. 11D, the opening 3a having a minute width is filled with a metal layer 5 to be a gate electrode. In this case, the width between the sidewalls 4a becomes the gate length.

(Conventional Example 3) As shown in FIG. 12C,
A metal sidewall 8a deposited on the stepped sidewall 7a of the SiN layer 7 is used as a gate. (For example, Japanese Patent Laid-Open No. 4-2
No. 12428. )

First, as shown in FIG. 12A, for example, a SiN layer 7 having a step portion is formed on a GaAs layer 6 as a channel layer. Next, as shown in FIG. 12B, a metal layer 8 is deposited on the SiN layer 7 and the GaAs layer 6 so as to cover the side wall 7a of the step portion. And FIG. 12C
As shown in, the metal layer 8 is anisotropically etched by the RIE method. As a result, only the side wall 8a of the side wall 7a of the step portion remains, which becomes the gate.

[0008]

The above-mentioned conventional examples have the following problems.

(Conventional Example 1) Since a gate pattern is drawn one by one with an electron beam, throughput is low and productivity is poor. Further, the electron beam drawing apparatus is expensive.

(Prior art example 2) The controllability of the opening size when forming the opening 3 in the SiN layer 2 and the shape and thickness when forming the sidewalls 4a is poor, and the size tends to vary, and these variations easily occur. The desired gate length cannot be obtained with good reproducibility because it is reflected in the width between the sidewalls 4a.

(Prior art example 3) Similar to the prior art example 2, even in the step of the prior art example 3, variations in the shape and thickness of the side wall 8a are likely to occur, so that the gate length also varies.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor device having a very fine gate length and line width controllability and an effective gate length, and a manufacturing method thereof. And

[0013]

According to a first aspect of the present invention, there is provided a semiconductor device according to claim 1, wherein a gate forming layer having a step portion is formed on the channel layer or with at least one semiconductor layer interposed. The portion is located between the source electrode and the drain electrode, a diffusion region having a conductivity type opposite to that of the channel layer is formed on the sidewall of the step portion, and the gate electrode is connected to the diffusion region.

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises a step of forming a gate formation layer on a channel layer or with at least one semiconductor layer interposed, and a step of selectively forming the gate formation layer. A step of forming a step portion by etching, a step of diffusing impurities on a side wall of the step portion to form a diffusion region having a conductivity type opposite to that of the channel layer, a step of connecting a gate electrode to the diffusion region, a channel layer And forming a source electrode and a drain electrode which make ohmic contact with each other so as to sandwich the gate electrode.

That is, in the present invention, the lateral thickness (width) of the diffusion region formed on the side wall of the step portion acts as an effective gate length. Further, in the impurity diffusion to the side wall of the step portion, the width of the diffusion region to be formed can be made extremely thin and can be easily controlled to a desired width by temperature and time, so that a desired short gate length can be formed with good reproducibility. it can.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

1 to 3 are sectional views showing a manufacturing process of a junction type FET as a semiconductor device according to the first embodiment.

First, as shown in FIG. 1A, semi-insulating GaAs is used.
On the substrate 11, a buffer layer 12, a channel layer 13,
The barrier layer 14 as the gate forming layer according to the present invention is sequentially epitaxially grown.

The buffer layer 12 is a non-doped GaAs layer to which no impurities are added, and its thickness is about 500 nm. The channel layer 13 has an impurity concentration of, for example, Si of 2
It is an n-type GaAs layer added at × 10 ¹⁷ cm ⁻³ , and its thickness is about 20 nm. Barrier layer 14 is undoped GaAs
A layer, the thickness of which is about 500 nm.

Next, the barrier layer 14 is etched by the RIE method using the resist mask which is selectively opened,
As shown in FIG. 1B, a step portion 15 having a rectangular cross-section with a width of about 1 μm is formed substantially perpendicular to the channel layer 13.
The step portion 15 extends in a direction penetrating the paper surface. After this,
A SiN film (about 100 nm thick) 16 is formed as an insulating film on the channel layer 13 so as to cover the step portion 15.
Although the barrier layer 14 other than the step portion 15 is etched until the surface of the channel layer 13 is exposed in the drawing, the etching may be performed at any depth, or may be performed halfway through the barrier layer 14. Alternatively, a part of the channel layer 13 may be etched. The depth of such etching is controlled according to the desired gate threshold voltage of the FET, the thickness of the channel layer 13 and the impurity concentration, the thickness of the barrier layer 14, the depth of the diffusion region 17 in the step described later, and the like.

Then, as shown in FIG. 1C, the SiN film 1
An opening 16a having a width of, for example, about 1 .mu.m is formed in 6 to expose one side wall 15a of the step portion 15.

Then, for example, in a diethyl Zn atmosphere, 6
A thermal diffusion process at 00 ° C. is performed. As a result, as shown in FIG. 2D, Zn (or Mg) as an impurity diffuses into the exposed portion of the step portion 15 and the channel layer 13 through the opening 16a to form the p-type diffusion region 17. The diffusion depth (thickness) is, for example, 100 nm.

Next, after removing the SiN film 16, RI
The entire surface is anisotropically etched back by the E method. This allows
As shown in FIG. 2E, the diffusion region 17b other than the step portion side wall 15a is removed. Due to the anisotropic etching, the side wall 15a of the step portion and the diffusion region 17a immediately below the side wall 15a remain without being etched.

Next, as shown in FIG. 2F, for example, a SiN film (thickness: about 300 nm) 18 is again formed on the entire surface as an insulating film.
Deposit. Next, a resist is applied on the SiN film 18, and the resist is etched back by the RIE method as shown by the dotted line to expose the upper portion of the SiN film 18 on the step portion 15, and then the SiN film 18 is etched. Figure 3
As shown in G, the upper portion of the step portion 15 including the diffusion region 17a of the side wall 15a is exposed.

Then, as shown in FIG. 3H, a gate electrode (for example, Ti) is formed so as to cover the exposed diffusion region 17a.
/ Pt / Au = 50 nm / 30 nm / 300 nm) 20
To form. The forming method is lift-off method, milling or RI
An existing process such as etching by the E method is used. In addition, before forming the gate electrode 20, the step portion 1 is formed of the insulating film.
5 is covered, then only the gate electrode formation portion including the diffusion region 17a is opened, and the gate electrode 20 is formed in this opening.
May be formed.

Next, as shown in FIG. 3I, an ohmic metal (for example, AuGe / Ni = 170 nm / 30 nm) to be the source electrode 21 and the drain electrode 22 is formed on the SiN layer 1.
8 is opened and formed on the channel layer 13, for example, 400
An ohmic contact is made with the channel layer 13 by performing a heat treatment at 1 ° C. for about 1 minute. Further, the resistance of the conductive layer other than the operating region of the FET is increased by ion implantation of, for example, B ⁺ or O ⁺ , and the element isolation region 23 is formed to perform element isolation. Alternatively, the elements may be separated by performing etching for forming the mesa portion first in FIG. 1A.

As described above, the junction type FET 10 according to the first embodiment is obtained. 4 shows a schematic plan view of the junction type FET 10. One end of the gate electrode 20 is connected to the external connection terminal 20a. The channel layer 13 is an n-type in which electrons are carriers of current as carriers, and by controlling the voltage applied to the gate electrode 20 having a pn junction between the channel layer 13 and the channel layer 13, the current between the source and drain is Controlled.

In the junction type FET 10 formed as described above, the lateral thickness (width) of the p-type diffusion region 17a acts as an effective gate length, and the diffusion thickness is extremely thin. Therefore, an extremely short gate length (for example, 0.15 μm or less) can be realized. Further, at the contact portion of the diffusion region 17a with the channel layer 13, as shown in an enlarged view in FIG. 5, due to the nature of diffusion in which the impurities are isotropically diffused, the shape becomes an arc shape, so that the most gate is formed. It is considered that the strong action is concentrated near the thinnest point P where the channel layer 13 is thin, and the effective gate length is further shortened.

Further, the width of the diffusion region 17a can be easily controlled by the diffusion time and the temperature, so that a desired gate length can be formed with high accuracy and reproducibility. In addition, the gate electrode 2
0 can be widely formed by supporting the step portion 15 and the SiN layer 18, and the contact with the diffusion region 17a can be obtained from the side surface, so that the gate series resistance can be suppressed low. Further, since the step portion 15 is non-doped, the gate capacitance can be reduced.

Further, in forming the gate, the step which requires alignment of the mask is the opening 16a in FIG. 1C.
2 at the time of forming the gate electrode and at the time of forming the gate electrode 20 in FIG. 3H.
With only the steps, the other steps only perform CVD, RIE, and diffusion over the entire surface, so that the productivity is good and the manufacturing cost can be kept low.

Next, a second embodiment of the present invention will be described. The same components as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

In the second embodiment, an etching stopper layer (for example, a non-doped AlGaAs layer) 25 as shown in FIG. 6 is used in the step corresponding to FIG. 1A in the first embodiment.
Is interposed between the channel layer 13 and the barrier layer 14.
That is, the etching stopper layer 25 is epitaxially grown subsequent to the channel layer 13. The etching stopper layer 25 is a non-doped AlGaAs layer, and includes the barrier layer (non-doped GaAs) 14 and the channel layer (n
Type GaAs) 13 and the material is different. Therefore, by appropriately selecting the etching conditions such as the type of etching gas, it is possible to give the etching selectivity to the barrier layer 14 and the channel layer 13.

Therefore, etching can be controlled for each layer of the barrier layer 14, the etching stopper layer 25, and the channel layer 13, and in the step of forming the step portion 15, the etching of the barrier layer 14 is continued after the etching of the barrier layer 14. It is possible to prevent 13 from being over-etched. As a result, the film thickness of the channel layer 13 immediately below the gate can be controlled to a desired thickness, and the gate threshold voltage determined by the film thickness directly below the gate can be controlled to a desired value.

The etching stopper layer 25 may be placed in the channel layer 13 or the barrier layer 14 depending on the desired thickness of the channel layer 13 immediately below the gate.

Next, a third embodiment of the present invention will be described. It should be noted that the same components as those in each of the above-described embodiments are designated by the same reference numerals and detailed description thereof will be omitted.

In the third embodiment, the present invention is not a simple junction type FET but a high electron mobility transistor H.
It is applied to EMT (High Electron Mobility Transistor).

FIG. 7 shows FIG. 1A in the first embodiment.
The buffer layer (non-doped GaAs layer) 31, channel layer (non-doped GaAs layer) 32, spacer layer (non-doped AlGaAs layer) 3 on the semi-insulating GaAs substrate 30
3, electron supply layer (n-type AlGaAs layer) 34, barrier layer (non-doped AlGaAs layer) 3 as a gate forming layer according to the present invention 3.
5 are sequentially laminated by epitaxial growth. The buffer layer 31 is made of non-doped AlGaAs, the channel layer 3
2 is non-doped InGaAs, barrier layer 35 is non-doped GaAs
May be

Then, the HEMT 37 shown in FIG. 8 is obtained through the same steps as those in the first embodiment. This HEM
At T37, the step portion 35a is formed in the barrier layer 35, and the p-type diffusion region 36 is formed on the side wall of the step portion 35a. The gate electrode 20 is connected to the p-type diffusion region 36.

In the HEMT 37 having the above structure, the channel layer 32 has a higher electron affinity than the electron supply layer 34, and thus the electrons emitted from the impurities added to the electron supply layer 34 are emitted from the channel layer 32. And two-dimensionally gather on the surface of the channel layer 32 at a high density. The electrons move on the surface of the channel layer 32, but since the channel layer 32 is a high-purity crystal containing no impurities, the electrons are less scattered and the electron mobility is higher. Also, since the electron density is high, a high speed operation transistor is realized. As described above, the channel layer 32 is an n-type in which electrons serve as carriers for the current, and the source-drain is controlled by controlling the voltage applied to the gate electrode 20 in which the pn junction is interposed between the channel layer 32 and the channel layer 32. The current in between is controlled.

In this embodiment, the same effect as that of the first embodiment can be obtained, and the lateral thickness (width) of the p-type diffusion region 36 acts as an effective gate length, so that the diffusion thickness is increased. Since it can be formed to be extremely thin, an extremely short gate length (for example, 0.15 μm or less) can be realized. Further, the width of the diffusion region 36 can be easily controlled by the diffusion time and the temperature, so that a desired gate length can be formed with high accuracy and reproducibility.

Next, a fourth embodiment of the present invention will be described. It should be noted that the same components as those in each of the above-described embodiments are designated by the same reference numerals, and detailed description thereof will be omitted.

In the fourth embodiment, the present invention is applied to a HEMT having a double hetero structure in which an electron supply layer is stacked above and below the channel layer so as to sandwich the channel layer.

FIG. 9 shows FIG. 1A in the first embodiment.
Corresponding to the above process, a buffer layer (non-doped GaAs layer) 41, a buffer layer (non-doped AlGaAs layer) 42, an electron supply layer (n-type AlGaAs layer) 43, on a semi-insulating GaAs substrate 40.
Spacer layer (non-doped AlGaAs layer) 44, channel layer (non-doped GaAs layer) 45, spacer layer (non-doped Al)
GaAs layer) 46, electron supply layer (n-type AlGaAs layer) 47, barrier layer (non-doped Al) as a gate formation layer according to the present invention.
GaAs layer) 48 is sequentially laminated by epitaxial growth.

Then, the HEMT 50 shown in FIG. 10 is obtained through the same steps as those in the first embodiment. This HE
In the MT 50, the step portion 48a is formed on the barrier layer 48, and the p-type diffusion region 49 is formed on the side wall of the step portion 48a. The gate electrode 20 is connected to the p-type diffusion region 49. In FIG. 10, the spacer layers 44 and 46 are not shown.

In the HEMT 50, electrons are supplied from the electron supply layers 47 and 43 to the upper and lower interfaces of the channel layer 45 to form channels. Channel layer 4
Reference numeral 5 denotes an n-type in which electrons are carriers of current as carriers, and the current between the source and drain is controlled by controlling the voltage applied to the gate electrode 20 having a pn junction between the channel layer 45 and the channel layer 45. It

In this embodiment, the same effect as that of the first embodiment can be obtained, and the lateral thickness (width) of the p-type diffusion region 49 acts as an effective gate length, resulting in the diffusion thickness. Since it can be formed to be extremely thin, an extremely short gate length (for example, 0.15 μm or less) can be realized. Then, the width of the diffusion region 49 can be easily controlled by the diffusion time and the temperature, so that a desired gate length can be formed with high accuracy and reproducibility.

The HEMT5 having this double hetero structure
0, the present invention can be applied to a so-called reverse HEMT structure in which the electron supply layer 47 above the channel layer 45 is deleted.

Although the respective embodiments of the present invention have been described above, of course, the present invention is not limited to these.
Various modifications are possible based on the technical idea of the present invention.

GaAs as in the third and fourth embodiments
The present invention is applicable not only to the HEMT of the system but also to the HEP of the InP system. In this case, the GaAs substrates 30, 40 → InP substrate buffer layers 31, 41 → non-doped InAlAs channel layers 32,45 → non-doped InGaAs spacer layers 33,44,46 → non-doped InAlAs electron supply layers 34,43,47 → n-type InAlAs barrier layers 35, 48, buffer layer 42 → non-doped InAl
Replaced by As.

Further, the HEMT structure may be provided with the etching stopper layer as shown in the second embodiment. For example, in the third embodiment, in the barrier layer 35,
In the fourth embodiment, it is placed in the barrier layer 48.

In each of the above embodiments, if the channel layer is p-type with holes as majority carriers, an n-type diffusion region is formed on the side wall of the step portion.

[0052]

According to the first and third aspects of the present invention, a short gate length can be realized with good controllability, and various characteristics (junction conductance, gain, noise figure, cutoff frequency, high frequency gain, etc.) of the junction FET can be obtained. improves.

According to the fifth aspect of the present invention, by providing the etching stopper layer at a desired position, the film thickness immediately below the gate is controlled to a desired thickness, and the gate threshold voltage is set to a desired value. Can be controlled.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram (1) of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a manufacturing process diagram (2) following FIG.

FIG. 3 is a manufacturing process diagram (3) following FIG. 2;

FIG. 4 is a schematic plan view of the semiconductor device according to the first embodiment.

FIG. 5 is an enlarged view of a main part in FIG. 3I.

FIG. 6 is a diagram corresponding to FIG. 1A, according to a second embodiment of the present invention.

FIG. 7 is a diagram corresponding to FIG. 1A, according to a third embodiment of the present invention.

FIG. 8 is a sectional view of a semiconductor device according to a third embodiment.

FIG. 9 is a diagram corresponding to FIG. 1A, according to a fourth embodiment of the present invention.

FIG. 10 is a sectional view of a semiconductor device according to a fourth embodiment.

FIG. 11 is a process diagram of a gate forming method according to Conventional Example 2.

FIG. 12 is a process diagram of a gate forming method according to Conventional Example 3.

[Explanation of symbols]

10 ... Junction type FET, 11 ... Semi-insulating substrate, 12 ...
... buffer layer, 13 ... channel layer, 14 ... gate formation layer (barrier layer), 15 ... step portion, 15a ... side wall,
17, 17a, 17b ... Diffusion region, 20 ... Gate electrode, 21 ... Source electrode, 22 ... Drain electrode, 25
...... Etching stopper layer, 30 …… Semi-insulating substrate, 3
1 ... Buffer layer, 32 ... Channel layer, 34 ... Electron supply layer, 35 ... Gate formation layer (barrier layer), 35a ...
... step portion, 36 ... diffusion area, 37 ... HEMT, 40
...... Semi-insulating substrate, 41 …… Buffer layer, 42 …… Buffer layer, 43 …… Electron supply layer, 45 …… Channel layer, 4
7 ... Electron supply layer, 48 ... Gate formation layer (barrier layer), 48a ... Step portion, 49 ... Diffusion region, 50 ...
Double hetero HEMT.

Claims (5)

[Claims] 1. A semiconductor device in which a pn junction is interposed between a gate electrode and a channel layer connecting a source electrode and a drain electrode, wherein at least one semiconductor layer is interposed on the channel layer. A gate forming layer having a step portion is formed, the step portion is located between the source electrode and the drain electrode, and a diffusion region having a conductivity type opposite to that of the channel layer is formed on a sidewall of the step portion. A semiconductor device, wherein the gate electrode is connected to the diffusion region. 2. The channel layer is n-type, the gate formation layer is made of III-V group compound semiconductor, and the diffusion region is p-type in which Zn is diffused in the III-V group compound semiconductor. The semiconductor device according to claim 1, wherein: 3. A step of forming a gate formation layer on a channel layer or with at least one semiconductor layer interposed, a step of selectively etching the gate formation layer to form a step portion, A step of diffusing impurities on the side wall of the step portion to form a diffusion region having a conductivity type opposite to that of the channel layer; a step of connecting a gate electrode to the diffusion region; and a source electrode having ohmic contact with the channel layer. A method of manufacturing a semiconductor device, comprising: forming a drain electrode so as to sandwich the gate electrode. 4. The channel layer is n-type, the gate formation layer is made of III-V group compound semiconductor, and the diffusion region is p-type in which Zn is diffused in the III-V group compound semiconductor. The method for manufacturing a semiconductor device according to claim 3, wherein 5. An etching stopper having etching selectivity between a layer in contact with the channel layer and the gate formation layer, in the channel layer, in the gate formation layer, or in the semiconductor layer. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising a step of forming a layer, wherein during the etching, overetching of a lower layer of the etching stopper layer is prevented.