JP2008141040A - Field effect transistor and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an enhancement (normally-off) type field effect transistor using a nitride semiconductor which has a structure to obtain a low ON resistance, and to provide a method of manufacturing the same. <P>SOLUTION: A contact layer 105 which consists of AlGaN whose Al composition is equal or larger than that of an AlGaN electron supply layer 104, is doped with n-type impurities at 2×10<SP>19</SP>cm<SP>-3</SP>or more and is thick in the range of 2 to 10 nm is provided on an AlGaN electron supply layer 104. The transistor has: a first recess 110 formed by removing the contact layer 105 by etching in a part between a source electrode 106 and a drain electrode 107; and a second recess 112 formed by thinning the electron supply layer 104 in a part inside the first recess. A gate insulating film 113 and a T-type gate electrode 108 are put inside of the second recess while leaving no space, and an ohmic auxiliary electrode 114 is formed on the contact layer 105 adjacent to the T-type gate electrode 108 to self-align by using a step formed by the insulating film 109 under an umbrella of the T-type gate electrode 108. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a field effect transistor using a nitride semiconductor and a method for manufacturing the same. In particular, the present invention relates to a field effect transistor having a configuration capable of realizing a low on-resistance in an enhancement (normally off) type field effect transistor, and a manufacturing method thereof.

  Nitride-based semiconductors such as GaN, AlGaN, InGaN, InAlN, and InAlGaN have the characteristics of having high dielectric breakdown strength, high thermal conductivity, and high electron saturation speed. Because of this feature, it is promising as a semiconductor material used in the production of high-power devices in the field of high-frequency devices or power supply devices. In recent years, field-effect transistors using nitride-based semiconductor materials have been actively developed and developed. It has been broken.

  For these applications, an enhancement (normally off) type that does not require a negative DC bias power supply to the gate electrode of the field effect transistor is required. FIG. 6 shows an example of a conventionally proposed structure as an enhancement (normally off) field effect transistor using a nitride-based semiconductor material (see Patent Document 1). A configuration of an enhancement type field effect transistor using a nitride semiconductor according to the prior art illustrated in FIG. 6 will be briefly described. The enhancement type field effect transistor shown in FIG. 6 has a so-called HEMT (High Electron Mobility Transistor) configuration.

Specifically, as a conventional field effect transistor having a HEMT structure shown in FIG. 6, the following structure is exemplified (see Patent Document 1). For example, a buffer layer 2 made of GaN having a thickness of 50 nm is formed on a high-resistance substrate 1 such as a sapphire substrate. On the buffer layer 2, an electron transit layer 3 made of GaN having a thickness of 400 nm, an intermediate layer 9 made of AlN having a thickness of 1 nm, and an electron supply layer 4 made of undoped Al _0.2 Ga _0.8 N having a thickness of 30 nm were sequentially laminated. A heterojunction structure is formed. A source electrode S, a gate electrode G, and a drain electrode D are arranged in a plane.

In the conventional HEMT structure field effect transistor shown in FIG. 6, a recess structure is provided in a portion 8 corresponding to a portion immediately below the gate electrode G. That is, except for the portion 8 where the recess structure is provided, the thickness of the undoped Al _0.2 Ga _0.8 N layer constituting the electron supply layer 4 is 30 nm, but in the portion 8, the thickness of the undoped Al _0.2 Ga _0.8 N layer. Is 5 nm. At this time, the electron supply layer 4 made of undoped Al _0.2 Ga _0.8 N is supplied to the heterojunction interface between the intermediate layer 9 made of AlN and the electron transit layer 3 made of GaN except for the portion 8 where the recess structure is provided. Electrons are accumulated. The electrons accumulated at the heterojunction interface between the intermediate layer 9 made of AlN and the electron transit layer 3 made of GaN constitute a two-dimensional electron gas 6. On the other hand, in the region 8, even when the bias of the gate electrode G is 0 V, the depletion layer resulting from the gate electrode G provided on the surface of the undoped Al _0.2 Ga _0.8 N layer reaches the electron transit layer 3 made of GaN. Yes. As a result, in the region of the portion 8 where the recess structure is provided, electrons are accumulated at least at the heterojunction interface between the intermediate layer 9 made of AlN and the electron transit layer 3 made of GaN, which is located immediately below the gate electrode G. Does not occur. That is, the two-dimensional electron gas 6 is not formed in the region of the portion 8 where the recess structure is provided, at least in the portion immediately below the gate electrode G when the bias of the gate electrode G is 0V. . Therefore, when the gate voltage V _G applied to the gate electrode G is 0 V, the drain current I _D does not flow even if the drain voltage V _D is applied between the source electrode S and the drain electrode D. Has been achieved. That is, the gate voltage V _G applied to the gate electrode G, and biased to a positive voltage higher than the threshold voltage, the drain current I _D flows out, the enhancement (normally off) type field effect transistor is realized.

Next, a process of manufacturing a conventional field effect transistor having a HEMT structure shown in FIG. 6 will be briefly introduced with reference to FIG. First, the sapphire substrate 1 is introduced into a MOCVD (Metal Organic Chemical Deposition) apparatus and evacuated with a turbo pump until the degree of vacuum in the MOCVD apparatus is 1 × 10 ⁻⁶ hPa or less. Thereafter, the degree of vacuum is set to 100 hPa, and the substrate is heated to 1100 ° C. When the temperature is stabilized, the substrate 1 is rotated at 900 rpm. The trimethylgallium (TMG) as a raw material is introduced into the surface of the substrate 1 at a flow rate of 100 cm ³ / min and ammonia is 12 liter / min, and the buffer layer 2 made of GaN is grown. The growth time is 4 min (240 sec), and the thickness of the buffer layer 2 is about 50 nm.

Thereafter, trimethylgallium (TMG) is introduced onto the buffer layer 2 at a flow rate of 100 cm ³ / min and ammonia (NH ₃ ) at a flow rate of 12 liter / min, and the electron transit layer 3 made of GaN is grown. The growth time is 1000 sec, and the film thickness of the electron transit layer 3 is 400 nm. Next, an intermediate layer 9 made of undoped AlN is grown by introducing trimethylaluminum (TMA) at a flow rate of 50 cm ³ / min and ammonia at 12 liters / min. Subsequently, trimethyl aluminum (TMA) of 50 cm ³ / min, trimethyl gallium (TMG) 100cm ³ / min, the ammonia was introduced at a flow rate 12 liter / min, the growth of the Al _0.2 Ga electron supply layer 4 made of _0.8 N I do. The growth time is 40 sec, and the thickness of the electron supply layer 4 is 20 nm. Through the above steps, the layer structure A ₀ shown in FIG. 7A is completed.

After the epitaxial growth of the layer structure A ₀ is completed, the SiO ₂ film 10 is formed on the entire surface of A ₀ . An opening of the SiO ₂ film 10 is provided in a partial region corresponding to the portion 8 corresponding to just below the gate, and the electron supply layer 4 in that portion is exposed. Then, under normal pressure, at an oxygen flow rate of 5 liters / min and at a temperature of 900 ° C., the electron supply layer 4 having a thickness of 30 nm is oxidized from its surface to a depth of 25 nm, and the oxide layer 11 is oxidized. (See the layer structure A ₁ in FIG. 7B).

By this oxidation treatment, the thickness of the semiconductor layer of the electron supply layer 4 in the portion 8 corresponding to the portion immediately below the gate becomes 5 nm, which is larger than the thickness of the semiconductor layer constituting the electron supply layer 4 other than the portion 8 corresponding to the portion immediately below the gate. getting thin. Subsequently, the oxide layer 11 and the SiO ₂ film 10 are sequentially removed by wet etching using a phosphoric acid based, hydrochloric acid based, hydrofluoric acid based or nitric acid based etchant. As a result, a recess 7 is formed in the electron supply layer 4. As shown in the layer structure A ₂ in FIG. 3C, even when the Schottky junction due to the gate electrode G is not formed on the surface of the electron supply layer 4, The two-dimensional electron gas layer 6 has disappeared. That is, even in a state where no Schottky junction is formed on the surface of the electron supply layer 4, the conduction of the electron transit layer 3 at the interface between the intermediate layer 9 and the electron transit layer 3 immediately below the recess 7. The belt end E _C is higher in energy than the Fermi level E _f .

After completion of the etching process, the source electrode S and the drain electrode D (both Al / Ti / Au, thickness is 100 nm / 100 nm / 200 nm) and the gate electrode G (Pt / Au, thickness in the recess 7 are formed by EB vapor deposition. Is 100 nm / 200 nm). Therefore, the enhancement (normally off) type using the nitride semiconductor according to the prior art as shown in FIG. 6, in which the two-dimensional electron gas layer 6 has disappeared in the electron transit layer 3 of the recess 7. A field effect transistor is obtained.
JP 2005-183733 A

On the other hand, in the enhancement (normally off) type field effect transistor having the configuration shown in FIG. 6, the gate electrode G is positively biased, the gate voltage V _G is set higher than the threshold bias V _th (V _G > V _th ), There is a problem that the power consumption is large because the resistance between the source and the drain at the time of being in the “on state”, that is, the so-called on-resistance is high. At the time when the gate voltage V _G > V _th , the reason for the high on-resistance is that a plurality of factors (causes) are involved.

The first factor (cause) is the existence of the following phenomenon. When the gate electrode V _G is set higher than the threshold bias V _th and becomes “on”, a two-dimensional electron gas layer is generated in the region immediately below the gate electrode V _G , but the electrons in the recess 7 A part of the traveling layer 3 is still in a state where the two-dimensional electron gas layer has disappeared.

In the enhancement (normally off) type field effect transistor according to the prior art having the configuration shown in FIG. 6, the gate electrode G is formed in the recess 7 where the two-dimensional electron gas 6 has disappeared. A gap is provided between the gate electrode G and the gate electrode G. The gate electrode G is positively biased, the gate electrode V _G reaches the threshold bias V _th, the 2-dimensional electron gas layer 6 generated in the electron transit layer 3 immediately below the gate electrode G. On the other hand, regarding the gap between the end of the recess 7 and the gate electrode G, the surface potential of the electron supply layer 4 is different from the surface potential of the electron supply layer 4 immediately below the gate electrode G. As a result, the on-resistance is increased due to the high resistance of this portion.

  For example, in the structure shown in FIG. 6, the sheet resistance of the portion where the two-dimensional electron gas 6 other than the recess 7 is generated is about 500Ω / □. Assume that the distance between each electrode is a typical value that is generally manufactured, for example, the distance between the source electrode S and the gate electrode G is 2 μm, and the distance between the gate electrode G and the drain electrode D is 4 μm. At that time, the resistance between the electrodes per 1 mm (= 1000 μm) of the gate width is 500 × 2/1000 = 1 Ωmm between the source electrode S and the gate electrode G, and 500 × between the gate electrode G and the drain electrode D. 4/1000 = 2Ωmm, which contributes to a total on-resistance of 3Ωmm.

Next, consider the gap between the recess 7 and the gate electrode G described above. In the recess 7, it is described that “the two-dimensional electron gas 6 has disappeared”, but this “disappearance” does not mean that the electron density is actually 0 cm ⁻² , and “cannot be measured. It is in a state where it has fallen to “a certain degree”. Specifically, it means that the two-dimensional electron gas 6 is reduced to at least 1/1000 or less compared to the portion other than the recess 7. Temporarily, the two-dimensional electron gas 6 in the gap portion between the recess 7 and the gate electrode G described above is 1/1000 compared to the portion other than the recess, that is, the sheet resistance of this portion is 500 times 500 kΩ. / It shall be about □. In the structure shown in FIG. 6, in order to form the gate electrode G in the recess 7, in consideration of alignment accuracy, at least a 0.2 μm gap must be provided between the gate electrode and the end of the recess 7. Don't be. Assuming that the gap between the gate electrode G and the end of the recess 7 is 0.2 μm, the resistance of this gap is 500000 × 0.2 / 1000 = 100 Ωmm per 1 mm (= 1000 μm) of the gate width. The resistance of the gap between the gate electrode G and the end of the concave portion 7 contributes to the on-resistance as much as 20 times as compared with the resistance in the portion other than the concave portion 7. In the recess 7, it can be seen that when “two-dimensional electron gas 6 has disappeared”, even if the gap between the gate electrode G and the end of the recess 7 is small, the on-resistance is remarkably increased. .

  The second factor (reason) for increasing the on-resistance is that the access resistance between the source electrode S or drain electrode D and the two-dimensional electron gas 6 is high.

In the structure shown in FIG. 6, the electron supply layer 4 on which the source electrode S and the drain electrode D are formed is composed of Al _0.2 Ga _0.8 N that is not subjected to n-type doping. Consider the case where Al / Ti / Au is used to manufacture the source electrode S and the drain electrode D provided on the surface of Al _0.2 Ga _0.8 N not subjected to n-type doping. Under this condition, in our study, the access resistance between the source electrode S or drain electrode D and the two-dimensional electron gas 6 is about 1 Ωmm, and a resistance lower than this cannot be obtained.

Further, there is a method of providing a highly doped contact layer between the source electrode S and drain electrode D and the electron supply layer 4 for the purpose of reducing the contact resistance when reducing the on-resistance during operation. Patent Document 1 also discloses a structure in which an n-GaN layer of a nitride semiconductor doped with an n-type impurity at a high concentration of about 1 × 10 ¹⁹ cm ⁻³ is used as a contact layer. However, this structure has an effect of reducing the contact resistance between the source electrode S or the drain electrode D and the contact layer, but between the source electrode S or the drain electrode D and the two-dimensional electron gas 6 for the following reason. Access resistance cannot be effectively reduced. When an n-GaN layer is provided as a contact layer, a piezoelectric field is generated in AlGaN as the electron supply layer 4 by a piezoelectric effect based on crystal distortion, and a negative polarization charge is generated at the interface between the electron supply layer 4 and the contact layer. Is equivalent to the occurrence of. Due to this negative polarization charge, the energy potential at the lower end of the conduction band is raised at the interface between AlGaN as the electron supply layer 4 and n-GaN as the contact layer, thereby forming a high potential barrier against electrons. Therefore, electrons hardly pass through the high potential barrier between the source electrode S or the drain electrode D and the two-dimensional electron gas 6, that is, increase the resistance. This increase in resistance cancels the effect of reducing the contact resistance with the source electrode S or the drain electrode D using the contact layer made of n-GaN. Actually, a structure in which a contact layer made of n-GaN is inserted between the source electrode S and the drain electrode D and the electron supply layer 4 not subjected to Al _0.2 Ga _0.8 Nn-type doping will be examined. In our study, in the above configuration, the access resistance between the source electrode S or drain electrode D and the two-dimensional electron gas 6 is 1.5 Ωmm, which is rather than the access resistance when the contact layer is not provided. Resistance has increased.

  The present invention solves the above problems. An object of the present invention relates to a field effect transistor using a nitride semiconductor, and a field effect transistor having a structure that has a low on-resistance and can reduce power consumption when an enhancement (normally off) type structure is used. Is to provide.

In the conventional enhancement (normally off) type field effect transistor having the configuration shown in FIG. 6, it has been found that the main factors that increase the “on resistance” are summarized in the following four points.
-During the recess, it is difficult to suppress the size (length) of the region remaining on both sides of the gate electrode formed in the recess to 0.2 μm or less, respectively;
-In the region remaining on both sides of the gate electrode, the thickness of the electron supply layer is thin, and immediately below it is in a state where "two-dimensional electron gas has disappeared";
When the source electrode and the drain electrode are formed on the electron supply layer made of undoped AlGaN, the contact resistance is increased;
In the configuration in which the n-GaN contact layer is provided on the electron supply layer made of undoped AlGaN, the contact resistance of the source electrode and the drain electrode formed on the n-GaN contact layer is reduced. As a result of the potential barrier at the interface between the GaN contact layer and the n-type undoped AlGaN layer, the access resistance between the source and drain electrodes and the two-dimensional electron gas layer is not reduced as a whole.

  As a means for solving these four problems, the inventors have found that it is effective to select the following structure, and have completed the present invention.

That is, in the field effect transistor according to the present invention, for example,
It has a structure in which an electron transit layer made of GaN or InGaN, an electron supply layer made of AlGaN, and a contact layer made of AlGaN are laminated in this order,
A source electrode and a drain electrode are formed on the contact layer;
A first recess in which the contact layer is etched away at a portion between the source electrode and the drain electrode;
A second recess in which the electron supply layer is thinned in a part of the first recess;
A T-type gate electrode embedded in the second recess without a gap;
The contact layer has an Al composition of AlGaN constituting the same as or larger than that of the AlGaN constituting the electron supply layer, and is doped with an n-type impurity of 2 × 10 ¹⁹ cm ⁻³ or more. And the thickness is comprised in the range of 2-10 nm.

In the field effect transistor according to the present invention having the above-described configuration,
A MIS gate structure in which a gate insulating film is formed between the second recess and the T-type gate electrode is preferable.

Furthermore, in the field effect transistor according to the present invention comprising a configuration employing the above-described MIS gate structure,
It is connected to the source electrode or the drain electrode and on the contact layer adjacent to the T-type gate electrode in a self-aligned manner using a step formed by an insulating film under the umbrella of the T-type gate electrode. More preferably, the structure includes an ohmic auxiliary electrode to be formed.

On the other hand, a method of manufacturing a field effect transistor according to the present invention includes:
Epitaxially growing at least the electron transit layer, the electron supply layer, and the contact layer;
Forming the source electrode and the drain electrode on the contact layer;
Etching the first insulating film at a portion between the source electrode and the drain electrode after forming the first insulating film;
Using the first insulating film as a mask, etching the contact layer to form the first recess;
Forming a side wall made of the second insulating film in the first recess by anisotropic etching after forming the second insulating film;
Etching the electron supply layer using the sidewall as a mask to form a second recess, and the T-type gate over the whole of the second recess, over the sidewall, and over a part of the first insulating film Forming an electrode.

Further, in a method for manufacturing a field effect transistor according to the present invention, comprising the above-described configuration,
After the step of forming the second recess, the gate insulating film is formed, and then the step of forming the T-type gate electrode is performed, thereby realizing a structure including the MIS gate structure.

Further, in a method of manufacturing a field effect transistor according to the present invention having the MIS gate structure described above,
After the step of forming the T-type gate electrode, using the umbrella of the T-type gate electrode as a mask, removing the first insulating film by anisotropic etching;
By performing the step of forming the ohmic auxiliary electrode, a structure including the ohmic auxiliary electrode can be realized.

  The field effect transistor using the nitride semiconductor according to the present invention has the following effects.

  A contact layer is provided on the electron supply layer, and a source electrode and a drain electrode are provided on the contact layer. A first recess formed by etching away the contact layer at a part between the source electrode and the drain electrode, and a second recess formed by thinning the electron supply layer at a part within the first recess. And have. Then, by embedding the T-type gate electrode in the second recess without a gap, even if it is an enhancement (normally off) type, there is a first effect that it becomes a field effect transistor that realizes a low on-resistance.

This contact layer is made of AlGaN having an Al composition equal to or larger than that of AlGaN constituting the electron supply layer, and is doped with n-type impurities of 2 × 10 ¹⁹ cm ⁻³ or more. And the thickness is in the range of 2 to 10 nm. By using this highly doped n-AlGaN contact layer, even if it is an enhancement (normally off) type, there is a second effect that it becomes a field effect transistor that realizes a low on-resistance.

  Further, the MIS gate structure in which the gate insulating film is formed between the second recess and the T-type gate electrode increases the two-dimensional electron gas concentration immediately below the T-type gate electrode when the transistor is turned on. As a result, even if it is an enhancement (normally off) type, it has the 3rd effect that it becomes a field effect transistor which implement | achieves low ON resistance.

  Further, an ohmic auxiliary electrode is formed on the contact layer adjacent to the T-type gate electrode in a self-aligning manner using a step formed by the insulating film under the umbrella of the T-type gate electrode, By having a structure in which each of the ohmic auxiliary electrodes is connected to the source electrode or the drain electrode, there is a fourth effect that it becomes a field effect transistor that realizes a low on-resistance even in the enhancement (normally off) type.

  The preferred embodiments of the field effect transistor using the nitride semiconductor according to the present invention can be classified into the following four types according to the configuration.

  First, a first embodiment of a field effect transistor using a nitride semiconductor according to the present invention has the following configuration.

That is, a field effect transistor using a nitride semiconductor,
The layered structure of the nitride semiconductor is
An electron transit layer made of GaN or InGaN;
An electron supply layer made of AlGaN;
Including a structure in which contact layers made of AlGaN are stacked in this order;
The field effect transistor is:
A source electrode and a drain electrode formed on the contact layer;
A T-type gate electrode provided between the source electrode and the drain electrode;
In the region where the T-type gate electrode is provided,
A first recess formed by etching away the contact layer at a portion between the source electrode and the drain electrode;
A first insulating film formed under the umbrella of the T-type gate electrode in a region other than the first recess on the contact layer;
A second recess formed by reducing the thickness of the electron supply layer in a part of the first recess;
A sidewall made of a second insulating film formed in a region other than the second recess in the first recess;
A gate insulating film formed in the second recess and on the side wall made of the second insulating film and on the first insulating film;
The T-type gate electrode is formed to be embedded on the gate insulating film without a gap;
On the contact layer excluding the region where the T-type gate electrode is provided, on the region where the first insulating film is not formed, on the source electrode and on the drain electrode, and on the T-type gate electrode A field effect transistor using a nitride semiconductor, characterized by comprising an ohmic auxiliary electrode formed.

  A method of manufacturing a field effect transistor using the nitride semiconductor of the first form has the following configuration.

That is, a method of manufacturing a field effect transistor using a nitride semiconductor,
Forming a layered structure of the nitride semiconductor including at least an electron transit layer made of a nitride semiconductor, an electron supply layer, and a contact layer by epitaxial growth; and
Forming a source electrode and a drain electrode on the contact layer;
Forming a first insulating film on the source and drain electrodes and the contact layer;
Etching away the first insulating film at a portion between the source electrode and the drain electrode;
Using the first insulating film as a mask, etching the contact layer to form a first recess;
Forming a second insulating film covering at least the first recess;
Performing anisotropic etching on the second insulating film to form a sidewall made of the second insulating film in the first recess;
Etching the electron supply layer using the sidewall as a mask to form a second recess;
Forming a gate insulating film;
Forming a T-type gate electrode on the gate insulating film in the second recess without a gap;
Removing the first insulating film by anisotropic etching using the umbrella of the T-type gate electrode as a mask;
And a step of forming an ohmic auxiliary electrode.

  A second embodiment of the field effect transistor using the nitride semiconductor according to the present invention has the following configuration.

That is, a field effect transistor using a nitride semiconductor,
The layered structure of the nitride semiconductor is
An electron transit layer made of GaN or InGaN;
An electron supply layer made of AlGaN;
Including a structure in which contact layers made of AlGaN are stacked in this order;
The field effect transistor is:
A source electrode and a drain electrode formed on the contact layer;
A T-type gate electrode provided between the source electrode and the drain electrode;
In the region where the T-type gate electrode is provided,
A first recess formed by etching away the contact layer at a portion between the source electrode and the drain electrode;
A first insulating film formed under the umbrella of the T-type gate electrode in a region other than the first recess on the contact layer;
A second recess formed by reducing the thickness of the electron supply layer in a part of the first recess;
A sidewall made of a second insulating film formed in a region other than the second recess in the first recess;
A gate insulating film formed in the second recess and on the side wall made of the second insulating film and on the first insulating film;
The T-type gate electrode is a field effect transistor using a nitride semiconductor, characterized in that the T-type gate electrode is formed so as to be embedded on the gate insulating film without a gap.

  A method of manufacturing a field effect transistor using the nitride semiconductor of the second form has the following configuration.

That is, a method of manufacturing a field effect transistor using a nitride semiconductor,
Forming a layered structure of the nitride semiconductor including at least an electron transit layer made of a nitride semiconductor, an electron supply layer, and a contact layer by epitaxial growth; and
Forming a source electrode and a drain electrode on the contact layer;
Forming a first insulating film on the source and drain electrodes and the contact layer;
Etching away the first insulating film at a portion between the source electrode and the drain electrode;
Using the first insulating film as a mask, etching the contact layer to form a first recess;
Forming a second insulating film covering at least the first recess;
Performing anisotropic etching on the second insulating film to form a sidewall made of the second insulating film in the first recess;
Etching the electron supply layer using the sidewall as a mask to form a second recess;
Forming a gate insulating film;
Forming a T-type gate electrode on the gate insulating film in the second recess without a gap;
It is a manufacturing method of the field effect transistor characterized by having.

  A third embodiment of the field effect transistor using the nitride semiconductor according to the present invention has the following configuration.

That is, a field effect transistor using a nitride semiconductor,
The layered structure of the nitride semiconductor is
An electron transit layer made of GaN or InGaN;
An electron supply layer made of AlGaN;
Including a structure in which contact layers made of AlGaN are stacked in this order;
The field effect transistor is:
A source electrode and a drain electrode formed on the contact layer;
A T-type gate electrode provided between the source electrode and the drain electrode;
In the region where the T-type gate electrode is provided,
A first recess formed by etching away the contact layer at a portion between the source electrode and the drain electrode;
A first insulating film formed under the umbrella of the T-type gate electrode in a region other than the first recess on the contact layer;
A second recess formed by reducing the thickness of the electron supply layer in a part of the first recess;
A sidewall made of a second insulating film formed in a region other than the second recess in the first recess;
The T-type gate electrode is a field effect transistor using a nitride semiconductor, wherein the T-type gate electrode is embedded in the second recess without any gap.

  The method of manufacturing a field effect transistor using the nitride semiconductor of the third form has the following configuration.

That is, a method of manufacturing a field effect transistor using a nitride semiconductor,
Forming a layered structure of the nitride semiconductor including at least an electron transit layer made of a nitride semiconductor, an electron supply layer, and a contact layer by epitaxial growth; and
Forming a source electrode and a drain electrode on the contact layer;
Forming a first insulating film on the source and drain electrodes and the contact layer;
Etching away the first insulating film at a portion between the source electrode and the drain electrode;
Using the first insulating film as a mask, etching the contact layer to form a first recess;
Forming a second insulating film covering at least the first recess;
Performing anisotropic etching on the second insulating film to form a sidewall made of the second insulating film in the first recess;
Etching the electron supply layer using the sidewall as a mask to form a second recess;
Forming a T-type gate electrode in the second recess without gaps;
It is a manufacturing method of the field effect transistor characterized by having.

  A fourth embodiment of the field effect transistor using the nitride semiconductor according to the present invention has the following configuration.

That is, a field effect transistor using a nitride semiconductor,
The layered structure of the nitride semiconductor is
An electron transit layer made of GaN or InGaN;
An electron supply layer made of AlGaN;
Including a structure in which contact layers made of AlGaN are stacked in this order;
The field effect transistor is:
A source electrode and a drain electrode formed on the contact layer;
A T-type gate electrode provided between the source electrode and the drain electrode;
In the region where the T-type gate electrode is provided,
A first recess formed by etching away the contact layer at a portion between the source electrode and the drain electrode;
A first insulating film formed under the umbrella of the T-type gate electrode in a region other than the first recess on the contact layer;
A second recess formed by reducing the thickness of the electron supply layer in a part of the first recess;
A sidewall made of a second insulating film formed in a region other than the second recess in the first recess;
The T-type gate electrode is embedded in the second recess without any gap;
On the contact layer excluding the region where the T-type gate electrode is provided, on the region where the first insulating film is not formed, on the source electrode and on the drain electrode, and on the T-type gate electrode A field effect transistor using a nitride semiconductor, characterized by comprising an ohmic auxiliary electrode formed.

  The method of manufacturing a field effect transistor using the nitride semiconductor of the fourth form has the following configuration.

That is, a method of manufacturing a field effect transistor using a nitride semiconductor,
Forming a layered structure of the nitride semiconductor including at least an electron transit layer made of a nitride semiconductor, an electron supply layer, and a contact layer by epitaxial growth; and
Forming a source electrode and a drain electrode on the contact layer;
Forming a first insulating film on the source and drain electrodes and the contact layer;
Etching away the first insulating film at a portion between the source electrode and the drain electrode;
Using the first insulating film as a mask, etching the contact layer to form a first recess;
Forming a second insulating film covering at least the first recess;
Performing anisotropic etching on the second insulating film to form a sidewall made of the second insulating film in the first recess;
Etching the electron supply layer using the sidewall as a mask to form a second recess;
Forming a T-type gate electrode in the second recess without gaps;
And a step of forming an ohmic auxiliary electrode.

  The present invention is further described below.

In the field effect transistor according to the present invention, when the gate voltage V _G applied to the gate electrode is V _G = 0V, the electron density existing in the electron transit layer immediately below the gate electrode is substantially “zero”, In order to achieve a so-called “normally off” state, the following recess structure is used. First, the gate electrode provided between the source electrode and the drain electrode is a second recess formed by etching an electron supply layer made of AlGaN formed on an electron transit layer made of GaN or InGaN. A T-type gate electrode manufactured to be embedded is used. At this time, the depth of the second recess formed by etching the electron supply layer made of AlGaN is controlled, and the film thickness (d _sp2 ) of the electron supply layer remaining immediately below the second recess is set as the gate electrode. The two-dimensional electron gas accumulated at the interface between the electron supply layer and the electron transit layer is selected so that the gate voltage V _G = 0 V is applied. By achieving this "normally off" state, when the gate voltage V _G applied to the gate electrode to be positive, directly under the gate electrode, the interface between the electron supply layer and the electron transit layer, the two-dimensional electron gas is induced -It will be in the state of being accumulated and will be in the “on state”. That is, an enhancement (normally off) type field effect transistor can be realized.

On the other hand, in the region other than the second recess portion, the film thickness (d _sp1 ) of the electron supply layer is significantly larger than the film thickness (d _sp2 ) of the electron supply layer remaining immediately below the second recess. For example, when a gate electrode is provided on the surface of the electron supply layer having a film thickness (d _sp1 ) and a gate voltage V _G = 0 V is applied, the electron supply layer and the electron transit layer having the film thickness (d _sp1 ) are The film thickness (d _sp1 ) of the electron supply layer in the region other than the second recess portion is selected so that the two-dimensional electron gas accumulated at the interface does not disappear.

For example, in order to satisfy the above requirement, the film thickness (d _sp2 ) of the electron supply layer remaining immediately below the second recess and the film thickness (d _sp1 ) of the electron supply layer in the region other than the second recess portion are set. select. In this configuration, the gate voltage V _G applied to the T-type gate electrode, which is embedded without gaps in the second recess, is positive, and a two-dimensional electron gas is induced and accumulated immediately below the second recess. In the “on state” stage, the two-dimensional electron gas is induced and accumulated at the interface between the electron supply layer and the electron transit layer in all regions. Therefore, when the field effect transistor is in the “on state”, there is no region in which the two-dimensional electron gas has disappeared, thereby eliminating the main factor that increases the “on resistance”.

Furthermore, in the field effect transistor according to the present invention, the region where the gate electrode is formed between the source electrode and the drain electrode is the first recess. On the other hand, in a region other than the first recess region, a contact layer made of AlGaN doped with n-type impurities of 2 × 10 ¹⁹ cm ⁻³ or more is provided on the electron supply layer made of AlGaN. In addition, the Al composition (x ₂ ) of AlGaN constituting the contact layer is selected to be equal to or higher than the Al composition (x ₁ ) of AlGaN constituting the electron supply layer (x ₂ ≧ x ₁ ). Yes. Then, the source electrode and the drain electrode are formed on the contact layer made of this highly doped AlGaN. Therefore, the contact resistance of the source electrode and the drain electrode formed on the contact layer made of highly doped AlGaN is compared with the case of forming the contact resistance directly on the electron supply layer made of undoped AlGaN, for example. Can be reduced.

  In addition, when considering the interface between the contact layer made of highly doped AlGaN / the electron supply layer made of undoped AlGaN, the difference between the conduction band edge energies Ec (band offset), ΔEc is zero, or the contact layer side is It is higher than the electron supply layer side. The lattice constant of AlGaN constituting the contact layer is equal to or smaller than the lattice constant of AlGaN constituting the electron supply layer. Therefore, even if the polarization charge is induced by the piezoelectric effect due to the strain due to the difference in lattice constant, there is no induction of the negative polarization charge at the interface between the contact layer and the electron supply layer. There is no potential barrier due to. On the other hand, when highly doped GaN is employed as the contact layer, the difference (band offset) between the conduction band edge energies Ec and ΔEc are higher on the electron supply layer side than on the contact layer side. This band offset ΔEc functions as a potential barrier when electrons move from the contact layer side to the electron supply layer side through the interface between the contact layer made of highly doped GaN / electron supply layer made of undoped AlGaN. Further, the lattice constant of GaN constituting the contact layer is larger than the lattice constant of AlGaN constituting the electron supply layer. Therefore, the polarization charge is induced by the piezoelectric effect due to the strain resulting from the difference in lattice constant, and a negative polarization charge is induced at the interface between the contact layer and the electron supply layer. Therefore, a potential barrier due to the induced negative polarization charge is formed at the interface between the contact layer and the electron supply layer. That is, the potential barrier is formed by the two mechanisms described above, both of which function as a resistance component when electrons move from the contact layer side to the electron supply layer side.

  On the other hand, when electrons move from the contact layer side to the electron supply layer side at the interface of the contact layer made of highly doped AlGaN / electron supply layer made of undoped AlGaN, the band offset ΔEc is of course the potential. Does not function as a barrier. Further, even if polarization charge is induced by the piezoelectric effect, no negative polarization charge is induced at the interface between the contact layer and the electron supply layer, and it does not become a potential barrier due to the induced polarization charge. Therefore, by selecting the configuration of the contact layer made of highly doped AlGaN / electron supply layer made of undoped AlGaN, the resistance component present at the interface between the contact layer made of highly doped GaN / the electron supply layer made of undoped AlGaN can be reduced. Can be eliminated.

  Further, when a contact layer made of highly doped AlGaN is provided, the current flowing in (outflowing) from the source electrode or the drain electrode can cause current diffusion in the contact layer having a small resistivity. Therefore, the surface density of the current passing through the interface between the contact layer made of highly doped AlGaN / electron supply layer made of undoped AlGaN is lowered by the effect of the current diffusion. Thereafter, the potential difference generated while passing through the electron supply layer made of undoped AlGaN and reaching the electron transit layer made of GaN or InGaN is reduced in proportion to the reduction of the current density. In other words, the path through which the current flowing in (outflowing) from the source electrode or the drain electrode reaches the two-dimensional electron gas layer formed at the interface between the electron supply layer made of undoped AlGaN and the electron transit layer made of GaN or InGaN. The resistance value of is effectively reduced.

Therefore, in the region other than the first recess region, a configuration in which a contact layer made of AlGaN doped with n-type impurities of 2 × 10 ¹⁹ cm ⁻³ or more is selected on the electron supply layer made of AlGaN is selected. Thus, the effect of reducing the access resistance between the source or drain electrode and the two-dimensional electron gas layer can be obtained by the above three mechanisms.

The field effect transistor according to the present invention employs a configuration in which an electron supply layer made of AlGaN and a contact layer made of AlGaN are stacked on an electron transit layer made of GaN or InGaN. Therefore, due to lattice mismatch existing between GaN or InGaN used for the electron transit layer and AlGaN used for the electron supply layer and contact layer, the total film thickness of AlGaN used for the electron supply layer and contact layer Must not exceed the critical film thickness defined by the lattice mismatch. As described above, the film thickness (d _sp1 ) of the electron supply layer made of AlGaN must be selected to be not less than a predetermined value, usually 20 nm or more. The film thickness (d _c ) is selected to be 10 nm or less, preferably in the range of 2 to 10 nm. At this time, in order to avoid an increase in the spreading resistance of the entire contact layer, it is preferable to reduce the thickness (d _c ) of the contact layer and increase the n-type impurity concentration (N _D ) to be doped. That is, the contact layer thickness (d _c ) and the doped n-type impurity concentration (N _D ) so that the product {d _c × N _D } is equal to or greater than {10 nm × 1 × 10 ¹⁹ cm ⁻³ }. Is more preferable.

On the other hand, the thickness (d _sp1 ) of the electron supply layer made of AlGaN is at least 20 nm or more, preferably 30 nm or less, preferably 20 nm or more. In the first recess where the contact layer is not formed, in the region excluding the second recess portion, electrons supplied from the electron supply layer made of AlGaN having a film thickness (d _sp1 ) Accumulated at the interface with the electron transit layer made of InGaN to form a two-dimensional electron gas layer. During the first recess, the two-dimensional electron gas concentration (n _2D1 ) in the region excluding the second recess portion increases as the thickness (d _sp1 ) of the electron supply layer made of AlGaN in the region increases.

In a region other than the first recess, a contact layer made of AlGaN having a film thickness (d _c ) is provided on an electron supply layer made of AlGaN having a film thickness (d _sp1 ). Therefore, the two-dimensional electron gas concentration (n _2D0 ) in this region is the contribution of the contact layer made of AlGaN having the film thickness (d _c ) in addition to the contribution of the electron supply layer made of AlGaN having the film thickness (d _sp1 ). There is also. Accordingly, the two-dimensional electron gas concentration (n _2D0 ) in the region other than the first recess is higher than the two-dimensional electron gas concentration (n _2D1 ) in the region excluding the second recess portion during the first recess. It has become.

In the field effect transistor according to the present invention, the length of the region excluding the second recess portion during the first recess depends on the size of the side wall made of the second insulating film provided on both sides of the first recess. Has been decided. In other words, the length is the length of the portion of the electron supply layer made of AlGaN, which is covered by the side wall made of the second insulating film, which is provided on both sides of the first recess. The second insulating film is formed to cover the side surface of the first recess and is covered with the side wall made of the second insulating film, which is used for manufacturing the side wall made of the second insulating film. The lengths of the electron supply layers made of AlGaN are approximately the same. When the film thickness (t ₂ ) of the second insulating film is 0.1 μm or less, the length of the portion of the electron supply layer made of AlGaN covered by the side wall made of the second insulating film is also 0.1 μm or less. It can be.

  The step of forming the side wall made of the second insulating film is performed according to the following procedure.

A source electrode and a drain electrode are formed on a contact layer made of highly doped AlGaN, and then a first insulating film is formed to cover the entire surface. The first insulating film is etched in accordance with the planar shape of the region where the first recess is to be formed, thereby forming an opening. Using the first insulating film provided with the opening as a mask, the contact layer made of highly doped AlGaN is removed by etching to form a first recess. On the bottom surface of the first recess, an electron supply layer made of AlGaN is exposed. Thereafter, the film thickness (so as to cover the surface of the electron supply layer made of AlGaN exposed on the upper surface of the first insulating film, the side surfaces of the first insulating film and the first recess, and the bottom surface of the first recess) A _second insulating film of t ₂ ) is formed. Then, the formed second insulating film is subjected to anisotropic etching treatment from the upper surface, and the second insulating film covering the upper surface of the first insulating film and the bottom surface of the first recess is removed. In this anisotropic etching process, the first insulating film and the second insulating film covering the side surface portion of the first recess are left without being removed. The first insulating film and the second insulating film left on the side surface of the first recess are used as side walls made of the second insulating film. That is, the size (length) of the side wall made of the second insulating film, which remains in the state of covering the surface of the electron supply layer made of AlGaN during the first recess, is the second insulation formed on the side surface portion. It is substantially equal to the film thickness (t ₂ ).

  Thereafter, the etching process is performed on the electron supply layer made of AlGaN exposed on the bottom surface of the first recess by using the side wall made of the first insulating film and the second insulating film as a mask, so that the second recess is formed. Forming.

During the first recess, the two-dimensional electron gas concentration (n _2D1 ) in the region excluding the second recess portion is lower than the two-dimensional electron gas concentration (n _2D0 ) in the region other than the first recess. During the first recess, the size (length) of the region excluding the second recess portion, that is, the size (length) of the side wall made of the second insulating film is limited to a very small range of 0.1 μm or less. It becomes possible to do. As a result, it is possible to suppress the contribution of the increase in sheet resistance due to the low two-dimensional electron gas concentration (n _2D1 ) in the region other than the second recess portion during the first recess.

  That is, in the field effect transistor according to the present invention, in the conventional enhancement (normally off) type field effect transistor having the structure shown in FIG. The problem that it is difficult to suppress the size (length) of the regions remaining on both sides of each to 0.2 μm or less is also solved by selecting the above-mentioned means.

On the other hand, in the field effect transistor according to the present invention, the T-type gate electrode formed to be embedded in the second recess has a MIS gate structure in which a gate insulating film is provided between the electron supply layer made of AlGaN. Can do. Even when the MIS gate structure is adopted, if the T-type gate electrode is positively biased, the depletion layer under the T-type gate electrode is reduced, and a two-dimensional electron gas is induced at the interface between the electron supply layer and the electron transit layer, "ON state". At that time, as the positive gate voltage V _G applied to the T-type gate electrode increases, the electric field in the electron supply layer made of AlGaN decreases, the conduction band edge becomes flat, and immediately below the second recess. The two-dimensional electron gas concentration (n _2D2 ) accumulated in the gas rises. When the MIS gate structure is adopted, a gate insulating film exists between the electron supply layer and the gate electrode, and this gate insulating film flows into the T-type gate electrode from the electron supply layer made of AlGaN ( gate current) acts as a barrier to I _G. It is applied to the T-shaped gate electrode, increasing a positive gate voltage V _G, the end, the conduction band edge of the electron supply layer made of AlGaN is completely flattened. Furthermore, when the positive gate voltage V _G is increased, the effective energy difference between the planarized conduction band edge energy (Ec) of the electron supply layer made of AlGaN and the barrier edge due to the gate insulating film decreases. Electron inflow from the electron supply layer made of AlGaN to the T-type gate electrode (gate current): I _G increases. That is, when the MIS gate structure is adopted, for example, in the configuration of the electron supply layer made of Ni / Au gate electrode / SiN gate insulating film / undoped Al _0.2 Ga _0.8 N, a gate voltage V _G flows through the gate in the forward direction. Can be raised to + 4V or more.

On the other hand, when a Schottky junction type gate electrode formed on the electron supply layer is employed, a Schottky barrier height (Φ _B ) is formed at the interface between the gate electrode and the electron supply layer. When the positive gate voltage V _G applied to the gate electrode reaches V _G = Φ _B / e, the conduction band edge of the electron supply layer made of AlGaN is completely flattened. When this “flat band” state is reached, the electron inflow (gate current): I _G from the electron supply layer made of AlGaN to the T-type gate electrode rapidly increases. For example, when the Schottky barrier height (Φ _B ) is Φ _B = 1.2 eV, when the positive gate voltage V _G reaches V _G = Φ _B /e=1.2 V, the forward direction of the gate The current that flows in I: I _G increases rapidly.

Therefore, when a Schottky junction type gate electrode is employed, the positive gate voltage V _G applied to the gate electrode is “flat” in order to avoid a rapid increase in the current I _G flowing in the forward direction of the gate. • Selected in a range that does not reach the “Band” state. That is, the operating condition of the field effect transistor is selected so that the positive gate voltage V _G applied to the gate electrode is substantially lower than the upper limit of V _G = Φ _B / e. Therefore, the two-dimensional electron gas concentration (n _2D2 ) accumulated immediately below the second recess under the operating conditions is the two-dimensional electron gas concentration when the AlGaN electron supply layer reaches the “flat band” state. It will be a considerably lower level. On the other hand, when the MIS gate structure is adopted, even if the positive gate voltage V _G applied to the gate electrode is set so that the electron supply layer made of AlGaN reaches the “flat band” state, Current flowing in the forward direction: _IG is at a sufficiently low level. Thus, the operating conditions of a field effect transistor, is applied to the gate electrode, a positive gate voltage V _G, can be selected in the range up to the state reaches "flat band" condition. That is, under the operating conditions, the two-dimensional electron gas concentration (n _2D2 ) stored immediately below the second recess is the two-dimensional electron gas concentration when the electron supply layer made of AlGaN reaches the “flat band” state. Can be increased up to. Therefore, when adopting the MIS gate structure, the "flat band" condition can be achieved, in the state of applying a positive gate voltage V _G, it is possible to lower the "on-resistance".

On the other hand, the threshold bias to the "on state"; about V _T, in the positive state of applying a gate voltage V _G to the gate electrode, as compared with the case of employing the MIS gate structure, the gate electrode of the Schottky junction type When it is adopted, the current I _G flowing in the forward direction of the gate increases. Therefore, the ratio between the source-drain current I _SD and the source-drain bias V _SD ; {V _SD / I _SD } ≈R _on is a Schottky junction type compared to the case where the MIS gate structure is adopted. When the gate electrode is adopted, it is larger.

In other words, as compared with the case of employing the gate electrode of the Schottky junction, in the case of employing the MIS gate structure, a current flows in the forward direction of the gate: the result of the increase in I _G can be suppressed, the range in general the operating conditions , The “on resistance” can be lowered.

  Further, by utilizing a step between the upper surface of the T-type gate electrode and the surface of the contact layer, an ohmic contact is formed adjacent to the T-type gate electrode on the surface of the contact layer made of highly doped AlGaN in a self-aligned manner. An auxiliary electrode may be formed. This ohmic auxiliary electrode can also achieve ohmic contact with the surface of the contact layer made of highly doped AlGaN. Furthermore, the ohmic auxiliary electrode is electrically connected to the source electrode or the drain electrode, respectively. Therefore, as a current flow path through the contact layer made of highly doped AlGaN, in addition to the path passing through the interface between the contact layer and the source electrode or the drain electrode, it passes through the interface between the contact layer and the ohmic auxiliary electrode. A path reaching the source electrode or the drain electrode via the ohmic auxiliary electrode is also available. That is, the ohmic auxiliary electrode plays a role of effectively increasing the contact area between the source electrode or the drain electrode and the contact layer. As a result, by adopting the ohmic auxiliary electrode, the access resistance from the source electrode or the drain electrode to the two-dimensional electron gas layer formed at the interface between the electron supply layer and the electron transit layer can be further reduced. Figured. Therefore, by adopting the ohmic auxiliary electrode, the “on resistance” can be further reduced.

In the field effect transistor using the nitride semiconductor according to the present invention having the above-described configuration, the layered structure of the nitride semiconductor immediately below the source electrode or the drain electrode has an electron travel made of GaN or InGaN. It includes a structure in which a layer, an electron supply layer made of AlGaN, and a contact layer made of AlGaN are stacked in this order. At this time, the two-dimensional electron gas concentration (n _2D0 ) accumulated at the interface between the electron _transit layer made of GaN or InGaN and the electron supply layer made of AlGaN is at least n _2D0 = 0.6 × 10 ¹³ / cm. ^Two or more are preferable. In this region, the two-dimensional electron gas concentration (n _2D0 ) accumulated at the interface between the electron _transit layer and the electron supply layer is 0.6 × 10 ¹³ / cm ^{2 to} 1.5 × 10 ¹³ / cm ² . It is more desirable to select a range.

At that time, GaN or InGaN constituting the electron transit layer is preferably selected in the range of GaN or In _y Ga _1-y N (0 <y ≦ 0.1). Further, the film thickness (d ₂ ) of GaN or InGaN constituting the electron transit layer is at least 2 nm or more, for example, when In _y Ga _1-y N (0 <y ≦ 0.1) is used. Is preferably 20 nm or less. That is, the GaN as a buffer layer on its upper _{surface, In y Ga 1-y N} (0 <y ≦ 0.1) when epitaxially grown, the critical film thickness: considering t _cr, InGaN having a thickness (d ₂ ) is preferably selected in the range of d ₂ ≦ t _cr .

On the other hand, for example, when AlGaN (GaN) is used as a buffer layer and In _y Ga _1-y N (0 <y ≦ 0.1) is epitaxially grown on the upper surface thereof, electron travel is sandwiched between the electron supply layer and the buffer layer. The layer has an AlGaN / InGaN / AlGaN structure. At this time, two-dimensional accumulation of electrons does not occur at the InGaN / AGaN interface between the electron transit layer and the buffer layer, but only at the AlGaN / InGaN interface between the electron supply layer and the electron transit layer. A structure in which accumulation of electron gas is concentrated is preferable. For that purpose, the thickness (d ₂ ) of InGaN used for the electron transit layer is preferably selected in the range of ₂ nm ≦ d ₂ ≦ 5 nm. When the above condition is satisfied, when the gate voltage V _G = 0V is set, the electron transit layer made of InGaN directly under the gate electrode can be in a state where two-dimensional electrons are not accumulated. That is, when the gate voltage V _G is set to 0 V, both the AlGaN / InGaN interface between the electron supply layer and the electron transit layer and the InGaN / AlGaN interface between the electron transit layer and the buffer layer accumulate electrons. It is in a state where has not been made. On the other hand, when the gate voltage V _G is positively biased and turned on, in the electron transit layer made of InGaN directly under the gate electrode, the AlGaN / InGaN interface between the electron supply layer and the electron transit layer is Dimensional electron gas accumulation is concentrated.

Furthermore, it is possible to adopt a form in which a non-doped AlN layer having a film thickness (d _i ) of 1 nm or less is inserted as an intermediate layer between an electron supply layer made of AlGaN and an electron transit layer made of GaN or InGaN. . At that time, a larger conduction band edge energy difference (band offset): ΔEc is formed at the interface between the AlN layer used as the intermediate layer and the electron transit layer made of GaN or InGaN. When this form is selected, the effect of improving the mobility of the two-dimensional electron gas accumulated at the interface when turned on is shown. When the Schottky junction is forward-biased, it also functions as a potential barrier against electron inflow from the electron transit layer made of GaN or InGaN to the electron supply layer made of AlGaN.

In the case of inserting the intermediate layer, after the second recess is formed, d _i ≦ 1 nm, and the film thickness of the electron supply layer made of AlGaN (d _sp2) remaining directly under the second recess ) And the intermediate layer thickness (d _i ) {d _sp2 + d _i } is at least in the range of 3 nm ≦ {d _sp2 + d _i } ≦ 15 nm, preferably 3 nm ≦ {d _sp2 + d _i } ≦ 12 nm It is desirable to select the range.

On the other hand, the composition of the AlGaN layer constituting the electron supply layer made of AlGaN is preferably selected in the range of Al _x1 Ga _1-x1 N (0 <x ₁ ≦ 0.5). That is, in order to set the two-dimensional electron gas concentration (n _2D0 ) accumulated at the interface between the electron _transit layer and the electron supply layer within the above range, the conduction band edge between the AlGaN layer and the GaN or InGaN layer is used. Energy difference (band offset): ΔEc is preferably selected in the range of 200 meV ≦ ΔEc ≦ 700 meV. At that time, the composition of the AlGaN layer constituting the electron supply layer made of AlGaN is preferably selected in the range of Al _x1 Ga _1-x1 N (0.15 ≦ x ₁ ≦ 0.5). More preferably, the band offset: ΔEc between the AlGaN layer and the GaN or InGaN layer is selected in the range of 200 meV ≦ ΔEc ≦ 500 meV. At that time, the composition of the AlGaN layer constituting the electron supply layer made of AlGaN is more preferably selected within the range of Al _x1 Ga _1-x1 N (0.15 ≦ x ₁ ≦ 0.35). When the electron supply layer made of AlGaN is composed of Al _x1 Ga _1-x1 N (0.15 ≦ x ₁ ≦ 0.35), the film thickness (d _sp1 ) is at least 20 nm ≦ d _sp1. It is preferable to select within the range of ≦ 30 nm.

Next, formed on the electron supply layer composed of AlGaN of aluminum composition A _1, aluminum composition A ₂ of AlGaN constituting the contact layer, and A ₂ ≧ A _1. On the other hand, this contact layer is doped with an n-type impurity of 2 × 10 ¹⁹ cm ⁻³ or more. As this n-type impurity, it is preferable to use a group 14 element such as Si or C, or a group 16 element such as S or O. The difference between the aluminum composition A _{2 of} AlGaN constituting the contact layer and the aluminum composition A _{1 of} AlGaN constituting the electron supply layer, (A ₂ −A ₁ ) is 0 ≦ (A ₂ −A ₁ ) ≦ It is preferable to select in the range of 0.1. That is, in order for the source electrode or drain electrode formed on the contact layer to achieve good ohmic contact, the aluminum composition A _{2 of} AlGaN constituting the contact layer is 0.1 ≦ A ₂ ≦ 0. It is more preferable to select the range of 6. Note that the thickness (d _c ) of the contact layer made of AlGaN is selected to be 10 nm or less, preferably in the range of 2 to 10 nm. At this time, in order to avoid an increase in the spreading resistance of the entire contact layer, it is preferable to reduce the thickness (d _c ) of the contact layer and increase the n-type impurity concentration (N _D ) to be doped. That is, the contact layer thickness (d _c ) and the doped n-type impurity concentration (N _D ) so that the product {d _c × N _D } is equal to or greater than {10 nm × 1 × 10 ¹⁹ cm ⁻³ }. Is more preferable.

  For the source electrode and drain electrode formed on the contact layer, for example, Ti / Al (30/180 nm) is formed at a predetermined location on the surface of the contact layer by using a vapor deposition / lift-off method. Thereafter, RTA (Rapid Thermal Anneal) is performed at 700 ° C. for 60 seconds to form good ohmic contact at the interface with the contact layer.

  Note that an ohmic auxiliary electrode is also used that forms ohmic contact with the contact layer surface. For example, Ti / Al (15/60 nm) is used and RTA is performed at 600 ° C. for 30 seconds to form ohmic contact with the contact layer.

On the other hand, the length (L ₁ ) of the first recess formed by etching away the contact layer is determined based on the length (L ₂ ) of the second recess to be formed therein. Selection is made so as to satisfy the relationship of the length (t ₂ ) of the side wall made of the film and L ₂ ≈L ₁ −2 × t ₂ .

In the present invention, the length (t ₂ ) of the side wall made of the second insulating film is preferably selected at least in the range of t ₂ ≦ 0.1 μm (100 nm).

On the other hand, the length (L ₂ ) of the second recess to be formed is selected based on the film thickness (d _sp2 ) of the electron supply layer made of AlGaN left immediately below the second recess. For example, the length (L ₂ ) of the second recess is selected so as to satisfy the relationship of (L ₂ ) ≧ 5 × (d _sp2 ) with respect to the film thickness (d _sp2 ) of the remaining electron supply layer. It is desirable. In other words, in order to induce the two-dimensional electron gas layer and the elimination thereof directly under the second recess, the length (L _G ) of the gate electrode is set to satisfy the above condition ( It is desirable to select so as to satisfy the relationship of L _G ) ≧ 5 × (d _sp2 ). At this time, the length (L _G ) of the gate electrode G embedded in the second recess is slightly shorter than the length (L ₂ ) of the second recess.

On the other hand, from the viewpoint of control accuracy in etching processing, at least the range of (L ₂ ) ≧ (d _sp1 -d _sp2 ) is selected based on the thickness (d _sp1 -d _sp2 ) of the AlGaN layer to be removed by etching. It is desirable to do. That is, in the etching process of the AlGaN layer performed when forming the second recess, the opening length (L ₂ ) of the mask is equal to or more than the target etching depth (d _sp1 -d _sp2 ). It is preferable to select.

Note that the film thickness (d _sp2 ) of the electron supply layer made of AlGaN left immediately below the second recess is the conduction between the electron supply layer made of AlGaN and the electron transit layer made of GaN or InGaN. Band edge energy difference (band offset): ΔEc, and Schottky barrier height (Φ _B ) when the gate electrode forms a Schottky junction with respect to the electron supply layer made of AlGaN, Selected. Usually, the film thickness (d _sp2 ) of the remaining electron supply layer made of AlGaN is preferably selected in the range of at least 3 nm ≦ d _sp2 ≦ 15 nm, preferably in the range of 3 nm ≦ d _sp2 ≦ 12 nm.

The first insulating film is used as an etching mask when the contact layer is removed by etching to form the first recess. Accordingly, an opening having a length corresponding to the target length (L ₁ ) of the first recess is provided. This opening is formed by etching the first insulating film. At this time, considering the accuracy in etching the first insulating film, the ratio between the length (L ₁ ) of the opening and the film thickness (t ₁ ) of the first insulating film: {L ₁ / t _1} is preferably selected in the range of _{{L 1 / t 1} ≧} 1.

In addition, when the ohmic auxiliary electrode is formed, the first insulating film functions as an insulating spacer for separating the ohmic auxiliary electrode and the gate electrode in the height direction. At that time, the film thickness (t ₁ ) of the first insulating film is at least in the range of (t ₁ ) / (t _m3 ) ≧ 2, based on the film thickness (t _m3 ) of the entire ohmic auxiliary electrode. Is preferably selected in the range of (t ₁ ) / (t _m3 ) ≧ 2.5.

For example, when 75 nm is selected as the film thickness (t _m3 ) of the entire ohmic auxiliary electrode, the film thickness (t ₁ ) of the first insulating film is at least (t ₁ ) ≧ 150 nm, preferably (t ₁ ) A range of ≧ 200 nm is selected. Accordingly, corresponds to the length of the first recess (L _1), the length of the opening (L ₁₎ also, (L ₁₎ ≧ 150 nm, preferably, selected within the range of (L ₁₎ ≧ 200 nm To do.

Next, when the side wall made of the second insulating film is formed, the second insulating film having a film thickness (t ₂ ) is formed on the upper surface of the first insulating film and the side wall surface of the opening of the first insulating film. In addition, the first recess is once formed so as to entirely cover the side surface and the bottom surface of the first recess. At that time, the size (length) of the “opening portion” left in the first recess portion is {L ₁ −2 × t ₂ }. An anisotropic etching process is performed to selectively remove the second insulating film existing on the top surface of the first insulating film and the bottom portion of the “opening portion” left in the first recess portion.

The insulating material that can be used as the second insulating film covers the entire top surface of the first insulating film, the side wall surface of the opening of the first insulating film, and the side and bottom surfaces of the first recess. It is an insulating material that can be coated with a uniform film thickness. That is, it is an insulating material capable of performing isotropic film formation by vapor phase growth. For example, it is preferable to use an insulating material capable of isotropic film formation such as SiN, SiO ₂ , SiON, Al ₂ O ₃ , AlN, ZrO ₂ , and HfO ₂ . Of these insulating materials capable of isotropic film formation, an insulating material suitable for anisotropic etching is used. Therefore, SiN, SiO ₂ , SiON, and the like are listed as insulating materials that can be used as the second insulating film.

Note that "aperture" to be left in the first recess portion, the opening length _{{L 1 -2 × t 2}} , depth, and has a _{{t 1 + d c -t 2} } . Finally, when the anisotropic etching process is completed, the shape of the opening used to form the second recess is that the length of the upper opening is L ₁ , and the length of the bottom surface Is {L ₁ −2 × t ₂ }, and the depth is {t ₁ + d _c }. When etching is performed using this as a mask, the length (L ₂ ) corresponding to the length of the bottom surface and the thickness (d _sp1 -d _sp2 ) of the AlGaN layer to be removed by etching are obtained. Recesses are formed.

When the MIS gate structure is adopted, the gate having a film thickness (t ₃ ) so as to cover the bottom surface and the side wall surface of the second recess, the side wall made of the second insulating film, and the top surface of the first insulating film. An insulating film is formed. At this time, the gap in the second recess of the electron supply layer made of AlGaN has an opening length of {L ₂ −2 × t ₃ } ≈ {L ₁ −2 × t ₂ −2 × t _3. }, The depth of the AlGaN layer region portion is {(d _sp1 -d _sp2 )-(t ₃ )}.

The insulating material that can be used as the gate insulating film has a uniform film thickness so as to cover the bottom surface and the side wall surface of the second recess, the side wall made of the second insulating film, and the top surface of the first insulating film. It is an insulating material that can be covered with. That is, it is an insulating material capable of performing isotropic film formation by vapor phase growth. For example, it is preferable to use an insulating material capable of isotropic film formation such as SiN, SiO ₂ , SiON, Al ₂ O ₃ , AlN, ZrO ₂ , and HfO ₂ . Furthermore, it has high adhesion to the metal material used for forming the gate electrode, and covers the bottom surface and the side wall surface of the second recess, the side wall made of the second insulating film, and the top surface of the first insulating film. In addition, it is more preferable to select one that can be uniformly coated with such a metal material. Including this requirement, for example, SiN, SiO ₂ , SiON, Al ₂ O _{3 and the} like are more preferable insulating materials. The film thickness (t ₃ ) of the gate insulating film is selected in consideration of the frequency at which the field effect transistor is used and the gate voltage V _G to be used. Generally, the film thickness is 3 nm ≦ t ₃ ≦ 80 nm, preferably It is preferable to select the range of ₃ nm ≦ t ₃ ≦ 30 nm.

  The gate electrode formed so as to be embedded in the second recess without a gap is a T-type gate electrode having a T-shaped cross section. That is, after the inside of the second recess is filled without a gap, the etching mask to be used can be easily patterned when the upper surface is etched into a desired planar shape. Also, in order to maintain the transconductance of the gate electrode in that direction with respect to the width of the gate electrode, it is preferable to employ a T-type gate electrode.

As a metal material for forming the gate electrode, a metal material capable of forming a Schottky junction having a Schottky barrier height (Φ _B ) of Φ _B ≧ 0.8 eV with respect to undoped AlGaN constituting the electron supply layer It is desirable to use Note that it is preferable that a metal material exhibiting high electrical conductivity is stacked on the metal material for forming the Schottky junction. Further, as the metal material for forming the Schottky junction, an undoped AlGaN constituting the electron supply layer serving as the underlayer, or a material having adhesion to the gate insulating film is preferably used. For example, the gate electrode is preferably manufactured using Ni / Au, Pt / Au, Pd / Au, Ni / Pt / Au, Ni / Pd / Au, or the like.

  Hereinafter, the present invention will be described in more detail with reference to specific examples. The following specific examples are examples of the best embodiments of the present invention, but the present invention is not limited to these embodiments.

(First embodiment)
A field effect transistor according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing the structure of the field effect transistor according to the first embodiment.

The nitride semiconductor used in the field effect transistor according to the first embodiment has the following layered structure. On the substrate 101, a buffer layer 102, an electron transit layer 103 made of GaN having a thickness of 1 μm, an electron supply layer 104 made of undoped Al _0.2 Ga _0.8 N having a thickness of 25 nm, and Si of 2 × 10 ¹⁹ cm ⁻ as an n-type impurity. ^A contact layer 105 made of Al _0.2 Ga _0.8 N having a thickness of 5 nm and doped ³ is epitaxially grown in this order to form a laminated structure. A source electrode 106 and a drain electrode 107 are formed on the contact layer 105. A T-type gate electrode 108 is provided between the source electrode 106 and the drain electrode 107.

  The T-type gate electrode 108 and the region in which it is provided have the following configuration.

  The contact layer 105 is removed by etching at a part between the source electrode 106 and the drain electrode 107 to expose the electron supply layer 104, thereby forming a first recess 110. A first insulating film 109 made of SiN having a thickness of 200 nm formed under the umbrella of the T-type gate electrode 108 is formed on the contact layer 105 in a region other than the first recess 110. In addition, the second recess 112 is formed in the first recess 110 by partially reducing the thickness of the electron supply layer 104 to 5 nm. On the other hand, in the region other than the second recess 112 in the first recess 110, a side wall made of the second insulating film 111 formed by etching SiN having an original film thickness of 100 nm is formed. . A gate insulating film 113 made of SiN having a thickness of 12 nm is formed in the second recess 112 and on the side wall made of the second insulating film 111 and the first insulating film 109. A T-type gate electrode 108 is formed on the gate insulating film 113 without any gaps. An ohmic auxiliary electrode 114 is formed on the contact layer 105 where the first insulating film 109 is not formed, on the source electrode 106 and the drain electrode 107, and on the T-type gate electrode 108. ing. That is, the ohmic auxiliary electrode 114 is divided into a total of three portions, and is electrically connected to the source electrode 106, a portion on the source electrode side, and a drain electrode electrically connected to the drain electrode 107 It is divided into a portion on the side and a portion on the T-type gate electrode formed on the T-type gate electrode 108.

A T-type gate electrode 108 is formed on the electron supply layer 104 immediately below the second recess 112 via a gate insulating film 113, and has a MIS structure. Since the thickness of the electron supply layer 104 immediately below the second recess 112 is reduced to 5 nm, the field effect transistor is in an OFF state when the gate voltage V _G is V _G = 0V. The threshold voltage V _{th of the} gate which turns on this field effect transistor is V _th = + 0.5 V, and an enhancement (normally off) type field effect transistor is obtained.

In the structure shown in FIG. 1, when the gate voltage V _G is V _G = 0V, the electron transit layer 103 made of GaN and the undoped Al _0.2 Ga _0.8 N are directly under the region covered with the contact layer 105. Two-dimensional electron gas is present at the interface of the electron supply layer 104. Further, in the first recess 110, regions other than the second recess 112 are formed on the surface of the electron supply layer 104 made of undoped Al _0.2 Ga _0.8 N having a thickness of 25 nm, on the side wall made of the second insulating film 111, A bias voltage of the T-type gate electrode 108 is applied through the gate insulating film 113 thereon. When the gate voltage V _G is V _G = 0V, a two-dimensional electron gas is present at the interface between the electron transit layer 103 and the electron supply layer 104 even immediately below this partial region. When the T-type gate electrode 108 is positively biased and turned on, there is no region in which the two-dimensional electron gas has disappeared, and thus there is an effect that a low on-resistance can be obtained. Therefore, when the T-type gate electrode 108 is positively biased and the gate voltage V _G reaches the threshold bias V _th and becomes “on”, the interface between the electron transit layer 103 and the electron supply layer 104 is There is no region where the two-dimensional electron gas has disappeared. As a result, an operation characteristic of an enhancement (normally off) type field effect transistor exhibiting a low “on resistance” can be obtained.

The contact layer 105 is doped with Si as an n-type impurity at a concentration of 2 × 10 ¹⁹ cm ⁻³ , and a source electrode 106 and a drain electrode 107 are formed thereon, and the source electrode 106 or the drain electrode Compared with the case where 107 is formed on the electron supply layer 104 made of undoped Al _0.2 Ga _0.8 N, the contact resistance is reduced. Further, undoped Al _0.2 Ga _0.8 N constituting the electron supply layer 104 and high-concentration doped Al _0.2 Ga _0.8 N constituting the contact layer 105 have the same lattice constant, and the conduction band edge is formed at the interface between the two. Difference in energy Ec (band offset): ΔEc does not exist. Therefore, no negative polarization charge is generated at the interface between the contact layer 105 and the electron supply layer 104, and a potential barrier due to the band offset: ΔEc does not occur. In addition, the contact layer 105 itself has a very thin film thickness of 5 nm and its resistivity is sufficiently low, so that the series resistance of the contact layer 105 itself is very small.

  As a result, compared with the case where the contact layer 105 is not provided, when the contact layer 105 having the above configuration is provided, the access resistance between the source electrode 106 or the drain electrode 107 and the two-dimensional electron gas is comprehensively determined. Is obtained.

In particular, the contact layer 105 made of highly doped Al _0.2 Ga _0.8 N is formed so as to cover the surface of the electron supply layer 104 made of undoped Al _0.2 Ga _0.8 N, excluding the region of the first recess 110. Therefore, the current passing through the source electrode 106 or the drain electrode 107 undergoes current diffusion in the lateral direction in the contact layer 105 made of this highly doped Al _0.2 Ga _0.8 N. The effect of current diffusion in the contact layer 105 is that the current density [dI / dS] becomes rough as exp {− (d _c ) ² / (d _cr ) ² } as the film thickness d _c of the contact layer 105 increases. Reduce at an approximate rate. The reduction of the current density [dI / dS] due to the current diffusion effect reduces the series resistance in the electron supply layer 104 made of undoped Al _0.2 Ga _0.8 N, and thus the access resistance is reduced.

FIG. 3 is a graph showing a simulation result for explaining the effect of reducing the access resistance caused by the current diffusion effect caused by the contact layer 105 made of the high-concentration doped Al _0.2 Ga _0.8 N. In FIG. 3, the total {d _sp1 + d _c } of the film thickness (d _sp1 ) of the electron supply layer 104 and the film thickness (d _c ) of the contact layer 105 is fixed to 30 nm, and the sheet resistance due to the two-dimensional electron gas is 500Ω. When / □, the result of simulation calculation of the relationship between the access resistance between the source electrode 106 or the drain electrode 107 and the two-dimensional electron gas and the film thickness d _{c of the} contact layer is shown. According to FIG. 3, the access resistance when the thickness of the contact layer 105 is 0 nm, that is, when the source electrode 106 and the drain electrode are directly formed on the electron supply layer 104 made of undoped AlGaN is 0.87 Ωmm. It can be seen that by setting the thickness to 5 nm, the access resistance is reduced to about 1/8, that is, 0.11 Ωmm.

  On the other hand, by keeping the thickness of the contact layer 105 at 5 nm and the thickness of the electron supply layer at 25 nm and suppressing the decrease in thickness, the region where the contact layer 105 outside the first recess 110 remains. The sheet resistance of the first recess 110 is 550 Ω / □ while the sheet resistance of the sheet is 500 Ω / □, and the increase rate of the sheet resistance accompanying the formation of the first recess is suppressed to 10%. . In the field effect transistor according to the prior art shown in FIG. 6, the sheet resistance of the gap between the gate electrode G and the recess 7 reaches 500 kΩ / □, and the first embodiment shown in FIG. In the structure of the field effect transistor, it can be seen that the access resistance is remarkably reduced.

  In addition, since the gate insulating film 113 is provided between the electron supply layer 104 and the T-type gate electrode 108 in the second recess 112, the voltage at which current starts to flow in the forward direction of the gate electrode becomes + 4V. Yes. As a result, in the “ON state” of the MIS type field effect transistor shown in FIG. 1, the two-dimensional electron gas concentration immediately below the T-type gate electrode 108 is increased, so that the “ON resistance” is also reduced. .

  In addition, by providing the ohmic auxiliary electrode 114 on the contact layer 105, the sheet resistance in the region where the ohmic auxiliary electrode 114 and the contact layer 105 are in contact with each other is further reduced, and this contribution further reduces the “on resistance”. The effect of doing.

(Manufacturing process)
Next, a method for manufacturing the MIS field effect transistor according to the first embodiment shown in FIG. 1 will be described with reference to FIGS.

First, using a metal organic vapor phase epitaxy (MOVPE), a buffer layer 102, an electron transit layer 103 made of GaN having a thickness of 1 μm, an undoped Al _{0.2 having} a thickness of 25 nm are formed on the substrate 101. electron supply layer 104 made of Ga _0.8 n, a contact layer 105 having a thickness of 5nm by n-type impurity as the Si is 2 × 10 ¹⁹ cm ^-3 doped Al _0.2 Ga _0.8 n epitaxially grown in this order, is used for preparing A laminated structure of nitride semiconductor is obtained (FIG. 2-1 (a)).

  Next, a Ti / Al (30/180 nm) electrode is formed at a predetermined location on the surface of the contact layer 105 by vapor deposition / lift-off method. Thereafter, RTA (Rapid Thermal Anneal) is performed at 700 ° C. for 60 seconds to obtain the source electrode 106 and the drain electrode 107 (FIG. 2-1 (b)).

A first insulating film 109 made of SiN having a thickness (t ₁ ) of 200 nm is formed on the entire surface by plasma CVD (Chemical Vapor Deposition). Thereafter, a photoresist mask in which an opening pattern is formed in accordance with the planar shape pattern of the first recess 110 at a position where the first recess 110 is to be formed between the source electrode 106 and the drain electrode 107 is manufactured. To do. Using this photoresist mask, the first insulating film 109 made of SiN is etched by RIE (Reactive Ion Etching) (FIG. 2-1 (c)). Using the first insulating film 109 as a mask, the contact layer 105 is removed by etching using an ICP (Inductively Coupled Plasma) dry etching method. In accordance with the opening pattern, the contact layer 105 is removed, the surface of the electron supply layer 104 made of undoped Al _0.2 Ga _0.8 N is exposed, and the first recess 110 is formed.

Thereafter, a second insulating film 111 made of SiN is formed on the entire surface by plasma CVD. The film thickness (t ₂ ) of the second insulating film 111 is selected to be 100 nm in the above example. At that time, in the region of the upper surface of the first insulating film 109 and the first recess 110, the electron supply layer exposed on the etching side surface of the first insulating film 109 and the contact layer 105 and the bottom surface of the first recess 110. The surface of 104 is covered with the second insulating film 111.

  Furthermore, anisotropic etching is performed on the manufactured second insulating film 111 from the upper surface by using the RIE method. At that time, the second insulating film 111 made of SiN formed on the top surface of the first insulating film 109 and the surface of the electron supply layer 104 exposed on the bottom surface of the first recess 110 is removed by etching. To do. At that time, in the region of the first recess 110, the second insulating film 111 made of SiN remains in the shape of the side wall at the portion covering the etching side surface of the first insulating film 109 and the contact layer 105. . The second insulating film 111 made of SiN remaining in the shape of the side wall is used as a side wall made of the second insulating film 111 (FIG. 2-2 (d)).

At this stage, the planar shape of the electron supply layer 104 exposed on the bottom surface of the first recess 110 is covered with a sidewall made of the second insulating film 111 based on the planar shape of the first recess 110. The part where it is narrowed. On the other hand, the size (length) of the portion covered with the side wall made of the second insulating film 111 is changed from the side surface of the first recess 110 to the film thickness of the second insulating film 111 formed on the side surface. It is equivalent. That is, in the planar shape of the exposed electron supply layer 104, the length (L ₂ ) is the second insulation formed on the side surface from the length (L ₁ ) in the planar shape of the first recess 110. A value obtained by subtracting twice the film thickness (t ₂ ) of the film 111 is L ₂ ≈L ₁ −2 × t ₂ .

  Using the side wall made of the second insulating film 111 and the first insulating film 109 as a mask, the electron supply layer 104 is etched by 20 nm using an ICP dry etching method to form a second recess 112. Thereafter, a gate insulating film 113 made of SiN is formed to a thickness of 12 nm by plasma CVD. Next, Ni / Au (30/300 nm) is formed so as to embed the second recess 112 by vapor deposition / lift-off method. As a result, the cross-sectional shape of Ni / Au (30/300 nm) formed and patterned on the gate insulating film 113 becomes T-type, and the T-type gate electrode 108 is obtained (FIG. 2-2 (e)).

Using the T-type gate electrode 108 as a mask, the gate insulating film 113 and the first insulating film 109 are removed by etching using the RIE method. Next, Ti / Al (15/60 nm) is deposited. At that time, a first insulating film 109 made of SiN having a thickness (t ₁ ) of 200 nm, a gate insulating film 113 made of SiN having a thickness (t ₃ ) of 12 nm, Ni / A step composed of Au (30/300 nm) is formed. Using this step, the deposited Ti / Al (15/60 nm) is divided into a part on the source electrode 106 side, a part on the drain electrode 107 side, and a part on the T-type gate electrode 108.

  Finally, an ohmic auxiliary electrode 114 of Ti / Al (15/60 nm) is formed by RTA at 600 ° C. for 30 seconds. A field effect transistor employing the MIS gate structure shown in FIG. 1 is manufactured.

In the field effect transistor according to the first embodiment, the contact layer 105 is made of AlGaN having the same Al composition as the electron supply layer 104, and Si, which is an n-type impurity, is doped at a concentration of 2 × 10 ¹⁹ cm ^−3. You have selected. A structure is employed in which a source electrode 106 and a drain electrode 107 are formed on the contact layer 105 made of this highly doped AlGaN, and in addition, an ohmic auxiliary electrode is provided. By selecting this structure, as described above, there is an advantage that the access resistance between the source electrode 106 or the drain electrode 107 and the two-dimensional electron gas can be significantly reduced.

Further, when the second recess 112 is formed in the first recess 110, the side wall made of the second insulating film 111 formed on the side surface of the first recess 110 is used as an etching mask. . By setting the film thickness (t ₂ ) of the second insulating film 111 formed on the side surface of the first recess 110 to 100 nm, the length (L ₃ ) of the electron supply layer 104 covered with the sidewall is also increased. The thickness is 0.1 μm, which corresponds to the thickness (t ₂ ) of the second insulating film 111. In addition, in the portion covered by the sidewall, the film thickness _dsp of the electron supply layer 104 is 25 nm, and two-dimensional electron gas is present at the interface between the electron supply layer 104 and the electron transit layer 103 immediately below the electron supply layer 104. A state that exists exists. As a result, the length of the portion of the first recess 110 excluding the region where the second recess 112 is formed, that is, the length of the portion covered with the side wall made of the second insulating film 111 is the same as that of the source electrode 106 side and the drain electrode. Each side is limited to a small region having a length of 0.1 μm on the 107 side. In addition, this small region has a state in which two-dimensional electron gas exists at the interface between the electron supply layer 104 and the electron transit layer 103 immediately below, and minimizes an “increase in on-resistance” due to recess formation. The advantage that it can be suppressed to the limit is obtained.

  When the electron transit layer / electron transit layer to be used, the gate length, the distance between the source electrode or the drain electrode and the gate electrode are the same, the “on resistance” in the conventional recessed structure field effect transistor shown in FIG. It becomes about 5.5 Ωmm. On the other hand, the “on-resistance” in the field effect transistor according to the first embodiment is 1.1 Ωmm, which is 1/5 of the conventional one.

(Second embodiment)
In the first embodiment described above, by using the contact layer 105 made of highly doped Al _0.2 Ga _0.8 N and the ohmic auxiliary electrode 114, the electrode area of the source electrode and the drain electrode is effectively expanded. Thereby, an effect of remarkably reducing the access resistance between the source electrode 106 or the drain electrode 107 and the two-dimensional electron gas is obtained.

In the case where the current diffusion effect by the contact layer 105 made of high-concentration doped Al _0.2 Ga _0.8 N is sufficiently exhibited, the ohmic auxiliary electrode 114 may not be formed.

  Hereinafter, an example of the field effect transistor according to the second embodiment, in which the formation of the ohmic auxiliary electrode 114 is omitted, will be described with reference to FIG.

The nitride semiconductor used in the field effect transistor according to the second embodiment shown in FIG. 4 has the following layered structure. On a substrate 401, a buffer layer 402, a second buffer layer 415 made of GaN having a thickness of 1 μm, an electron transit layer 403 made of In _0.05 Ga _0.95 N having a thickness of 3 nm, and an undoped Al _0.2 Ga _0.8 N having a thickness of 25 nm. An electron supply layer 404 and a contact layer 405 made of Al _0.25 Ga _0.75 N with a thickness of 5 nm doped with Si 2 × 10 ¹⁹ cm ⁻³ as an n-type impurity are epitaxially grown in this order to form a stacked structure. Yes. A source electrode 406 and a drain electrode 407 are formed on the contact layer 405. A T-type gate electrode 408 is provided between the source electrode 406 and the drain electrode 407.

  This T-type gate electrode 408 and the region in which it is provided have the following configuration.

  The contact layer 405 is removed by etching at a part between the source electrode 406 and the drain electrode 407 to expose the electron supply layer 404, thereby forming a first recess 410. A first insulating film 409 made of SiN having a thickness of 200 nm and formed under the umbrella of the T-type gate electrode 408 is formed on the contact layer 405 in a region other than the first recess 410. In addition, the second recess 412 is formed in the first recess 410 by partially reducing the thickness of the electron supply layer 404 to 4 nm. On the other hand, in the region other than the second recess 412 in the first recess 410, a side wall made of the second insulating film 411 formed by etching SiN having an original film thickness of 120 nm is formed. . A gate insulating film 413 made of SiN having a thickness of 15 nm is formed in the second recess 412 and on the side wall made of the second insulating film 411 and on the first insulating film 409. A T-type gate electrode 408 is formed on the gate insulating film 413 without any gaps.

  Since the ohmic auxiliary electrode is not formed in the field effect transistor according to the second embodiment shown in FIG. 4, the current diffusion effect in the contact layer is further improved by providing the ohmic auxiliary electrode on the contact layer. The effect of letting go is lost. That is, by providing the ohmic auxiliary electrode on the contact layer, the sheet resistance in the region where the ohmic auxiliary electrode and the contact layer are in contact with each other is further reduced, and this contribution loses the effect of further reducing the “on resistance”. It has been broken.

  On the other hand, the process for forming the ohmic auxiliary electrode, that is, the etching process by the RIE method in which the first insulating film and the gate insulating film are removed by etching to expose the contact layer, the vapor deposition process, and the sintering process by RTA are omitted. Therefore, the manufacturing process can be simplified and the cost can be reduced accordingly.

  In the above-described configuration of the field effect transistor according to the second embodiment, by adopting InGaN for the electron transit layer 403, the two-dimensional electron gas concentration accumulated in this layer can be increased, and the sheet resistance can be reduced. Has been made. This effect greatly contributes in reducing the “on resistance” of the field effect transistor.

Further, the Al composition of AlGaN constituting the contact layer 405 is 0.25, which is higher than the Al composition of AlGaN constituting the electron supply layer 404, so that the boundary between the contact layer 405 and the electron supply layer 404 is present. The existing potential barrier is effectively reduced. As a result, the contribution of the resistance component at the boundary between the contact layer 405 and the electron supply layer 404 in the access resistance can be reduced. In addition, distortion caused by lattice mismatch between the electron transit layer 403 made of In _0.05 Ga _0.95 N, the electron supply layer 404 made of Al _0.2 Ga _0.8 N, and the contact layer 405 made of Al _0.25 Ga _0.75 N is The strain is larger than the strain caused by lattice mismatch between the electron transit layer made of GaN and the electron supply layer made of Al _0.2 Ga _0.8 N. The effect also shows the effect of increasing the two-dimensional electron gas concentration accumulated at the interface between the electron supply layer 404 made of Al _0.2 Ga _0.8 N and the electron transit layer 403 made of In _0.05 Ga _0.95 N. This contributes to reduction of on-resistance.

In the above configuration of the field effect transistor according to the second embodiment, the reduction effect derived from the ohmic auxiliary electrode is lost, but the electron transit layer made of In _0.05 Ga _0.95 N and the contact made of Al _0.25 Ga _0.75 N. By adopting the layer, an effect of reducing the access resistance is given. As a result, the “on resistance” in the conventional recessed structure field effect transistor shown in FIG. 6 is about 5.5 Ωmm, but the “on resistance” in the field effect transistor according to the second embodiment having the above-described configuration is 1 .3Ωmm, which is reduced to ¼ or less of the conventional one.

(Third embodiment)
The field effect transistor according to the second embodiment employs a MIS gate structure, but may employ a MES gate structure, that is, a Schottky junction type gate electrode.

  An example of the field effect transistor according to the third embodiment that employs a Schottky junction type gate electrode instead of the MIS gate structure will be described below with reference to FIG.

The nitride semiconductor used in the field effect transistor according to the second embodiment shown in FIG. 5 has the following layered structure. On the substrate 501, a buffer layer 502, a second buffer layer 515 made of GaN having a thickness of 1.5 μm, an electron transit layer 503 made of In _0.1 Ga _0.9 N having a thickness of 2 nm, and an undoped Al _0.2 Ga _{0.8 having} a thickness of 28 nm. An electron supply layer 504 made of N and a contact layer 505 made of Al _0.25 Ga _0.75 N having a thickness of 2 nm doped with Si as an n-type impurity at 1 × 10 ²⁰ cm ⁻³ are epitaxially grown in this order to form a stacked structure is doing. A source electrode 506 and a drain electrode 507 are formed on the contact layer 505. A T-type gate electrode 508 is provided between the source electrode 506 and the drain electrode 507.

  The T-type gate electrode 508 and the region where it is provided have the following configuration.

  The contact layer 505 is removed by etching at a part between the source electrode 506 and the drain electrode 507 to expose the electron supply layer 504, thereby forming a first recess 510. A first insulating film 509 made of SiN having a thickness of 150 nm formed under the umbrella of the T-type gate electrode 508 is formed on the contact layer 505 in a region other than the first recess 510. In addition, a second recess 512 is formed in the first recess 510 by partially reducing the thickness of the electron supply layer 504 to 3 nm. On the other hand, in the region other than the second recess 512 in the first recess 510, a side wall made of the second insulating film 511 formed by etching SiN having an original film thickness of 80 nm is formed. . A T-type gate electrode 508 is formed in the second recess 512 without any gap.

In the field effect transistor according to the third embodiment shown in FIG. 5, since the ohmic auxiliary electrode is not formed, the current diffusion effect in the contact layer is further improved by providing the ohmic auxiliary electrode on the contact layer. The effect of letting go is lost. On the other hand, the contact layer 505 itself made of Al _0.25 Ga _0.75 N having a thickness of 2 nm and doped with Si as an n-type impurity at 1 × 10 ²⁰ cm ⁻³ itself has a lower lateral spreading resistance. The current spreading effect is even higher. In addition, a source electrode 506 and a drain electrode 507 are formed on the surface of a contact layer 505 made of Al _0.25 Ga _0.75 N that is more highly doped, and the contact resistance of the electrode portion is further reduced. Yes.

In the above configuration of the field effect transistor according to the third embodiment, by adopting the electron transit layer 503 made of In _0.1 Ga _0.9 N, the concentration of the two-dimensional electron gas accumulated in this layer can be increased, Sheet resistance has been reduced. In particular, the difference in conduction band edge energy Ec (band offset) at the interface between the electron transit layer 503 made of In _0.1 Ga _0.9 N and the electron supply layer 504 made of Al _0.2 Ga _0.8 N: ΔEc, the lattice between them The accumulated two-dimensional electron gas concentration is higher due to the distortion caused by mismatching and the fact that the thickness of the electron supply layer 504 made of Al _0.2 Ga _0.8 N is 28 nm. . This effect greatly contributes to reducing the “on resistance” of the field effect transistor.

Further, the Al composition of AlGaN constituting the contact layer 405 is 0.25, which is higher than the Al composition of AlGaN constituting the electron supply layer 404, so that the boundary between the contact layer 405 and the electron supply layer 404 is present. The existing potential barrier is effectively reduced. As a result, the contribution of the resistance component at the boundary between the contact layer 405 and the electron supply layer 404 in the access resistance can be reduced. In addition, distortion caused by lattice mismatch between the electron transit layer 403 made of In _0.05 Ga _0.95 N, the electron supply layer 404 made of Al _0.2 Ga _0.8 N, and the contact layer 405 made of Al _0.25 Ga _0.75 N is The strain is larger than the strain caused by lattice mismatch between the electron transit layer made of GaN and the electron supply layer made of Al _0.2 Ga _0.8 N. The effect also shows the effect of increasing the two-dimensional electron gas concentration accumulated at the interface between the electron supply layer 404 made of Al _0.2 Ga _0.8 N and the electron transit layer 403 made of In _0.05 Ga _0.95 N. This contributes to reduction of on-resistance.

On the other hand, the first embodiment described above, the field-effect transistor of the second embodiment, by employing the MIS gate structure, the threshold of the gate electrode bias becomes "ON state": have high V _T. Before the gate electrode bias reaches the threshold value V _T , the region in the first recess other than the region immediately below the second recess is in a state in which the two-dimensional electron gas is accumulated. For this reason, the factor that increases the “on resistance” derived from the fact that the region where the two-dimensional electron gas density disappears remains when the “on state” is reached is eliminated. In contrast, the field-effect transistor of the third embodiment, in order to adopt a gate electrode of the Schottky junction, the "on state" to become the gate electrode bias thresholds: prevent the V _T decreases relatively Therefore, the thickness of the electron supply layer 504 immediately below the second recess 512 is reduced to 3 nm. As a result, also in the field effect transistor of the third embodiment, before the gate electrode bias reaches the threshold value V _T , the region in the first recess other than the region immediately below the second recess is two-dimensional. The electron gas is accumulated.

  On the other hand, when the configuration of the field effect transistor of the third embodiment is selected, in addition to the process for forming the ohmic auxiliary electrode, the process of forming the gate insulating film can be omitted, and the manufacturing process can be simplified. The effect of lowering costs is higher.

In the above configuration of the field effect transistor according to the third embodiment, the reduction effect derived from the ohmic auxiliary electrode is lost, but the electron transit layer made of In _0.1 Ga _0.9 N, Si is 1 × 10 ²⁰ cm ^−. By adopting a contact layer made of Al _0.25 Ga _0.75 N doped with ³ and an electron supply layer made of Al _0.2 Ga _0.8 N having a larger film thickness, an effect of reducing access resistance is given. As a result, the “on resistance” in the conventional recessed structure field effect transistor shown in FIG. 6 is about 5.5 Ωmm, but the “on resistance” in the field effect transistor according to the second embodiment having the above-described configuration is 1 .8Ωmm, which is reduced to 1/3 or less of the conventional one.

  As described above, in order to explain in more detail the principle used for reducing the “on resistance” in the field effect transistor of each embodiment according to the present invention, the composition, doping concentration and thickness of each nitride semiconductor, and the metal of each electrode Specifically, the type, the laminated structure, the type and thickness of each insulating film are disclosed. As long as the principle used for reducing the “on resistance” described above is satisfied, the configuration is not limited to the numerical values and materials disclosed in the above specific examples, and a nitride semiconductor is used. The materials and structures generally used in manufacturing the field effect transistor can be widely used.

  The enhancement (normally-off) type field effect transistor using a nitride semiconductor according to the present invention has the advantage of having a low on-resistance and a structure that can reduce power consumption. The present invention can be applied to a transistor that constitutes a high-power microwave amplifier used in a system or the like, and a transistor that is used in a power control device such as a PC power supply or an automobile power steering.

It is sectional drawing which shows typically an example of a structure of the field effect transistor concerning the 1st Embodiment of this invention. FIG. 4 is a schematic diagram of a field effect transistor manufacturing process according to the first embodiment of the present invention, in which (a) an epitaxial growth process, (b) a source electrode and drain electrode formation process, and (c) a first insulating film etching process are performed. FIG. During the manufacturing process of the field effect transistor according to the first embodiment of the present invention, (d) a step of forming a sidewall by anisotropic etching of the second insulating film, (e) a T-type gate on the gate insulating film It is sectional drawing which illustrates the formation process of an electrode typically. In the configuration of the field effect transistor according to the first embodiment of the present invention, the result of simulation calculation of the dependency of the contact layer thickness on the effect of reducing the access resistance by providing the contact layer made of highly doped AlGaN is shown. It is a graph to show. It is sectional drawing which shows typically an example of a structure of the field effect transistor concerning the 2nd Embodiment of this invention. It is sectional drawing which shows typically an example of a structure of the field effect transistor concerning the 3rd Embodiment of this invention. It is sectional drawing which shows typically an example of the structure of the field effect transistor which has the conventional recessed gate structure. During the manufacturing process of a field effect transistor having a conventional recess gate structure, (a) an epitaxial growth step, (b) a selective oxidation treatment step for forming a recess structure, and (c) a recess formation step by etching removal of the selective oxidation region. It is sectional drawing demonstrated typically.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 3 Electron travel layer 4 Electron supply layer 6 Two-dimensional electron gas 7 Recessed portion 8 Portion corresponding to just under the gate 9 Intermediate layer 10 SiO ₂ layer 11 Oxide layer 101, 401, 501 Substrate 102, 402, 502 Buffer layer 103, 403, 503 Electron transit layer 104, 404, 504 Electron supply layer 105, 405, 505 Contact layer 106, 406, 506 Source electrode 107, 407, 507 Drain electrode 108, 408, 508 T-type gate electrode 109, 409, 509 First insulating film 110, 410, 510 First recess 111, 411, 511 Second insulating film 112, 412, 512 Second recess 113, 413 Gate insulating film 114 Ohmic auxiliary electrode 415, 515 Second Buffer layer (GaN)

Claims (8)

A field effect transistor using a nitride semiconductor,
The layered structure of the nitride semiconductor is
An electron transit layer made of GaN or InGaN;
An electron supply layer made of AlGaN;
Including a structure in which contact layers made of AlGaN are stacked in this order;
The field effect transistor is:
A source electrode and a drain electrode formed on the contact layer;
A T-type gate electrode provided between the source electrode and the drain electrode;
In the region where the T-type gate electrode is provided,
A first recess formed by etching away the contact layer at a portion between the source electrode and the drain electrode;
A first insulating film formed under the umbrella of the T-type gate electrode in a region other than the first recess on the contact layer;
A second recess formed by reducing the thickness of the electron supply layer in a part of the first recess;
A sidewall made of a second insulating film formed in a region other than the second recess in the first recess;
A gate insulating film formed in the second recess and on the side wall made of the second insulating film and on the first insulating film;
The T-type gate electrode is formed to be embedded on the gate insulating film without a gap;
On the contact layer excluding the region where the T-type gate electrode is provided, on the region where the first insulating film is not formed, on the source electrode and on the drain electrode, and on the T-type gate electrode A field effect transistor using a nitride semiconductor, comprising an ohmic auxiliary electrode formed. A field effect transistor using a nitride semiconductor,
The layered structure of the nitride semiconductor is
An electron transit layer made of GaN or InGaN;
An electron supply layer made of AlGaN;
Including a structure in which contact layers made of AlGaN are stacked in this order;
The field effect transistor is:
A source electrode and a drain electrode formed on the contact layer;
A T-type gate electrode provided between the source electrode and the drain electrode;
In the region where the T-type gate electrode is provided,
A first recess formed by etching away the contact layer at a portion between the source electrode and the drain electrode;
A first insulating film formed under the umbrella of the T-type gate electrode in a region other than the first recess on the contact layer;
A second recess formed by reducing the thickness of the electron supply layer in a part of the first recess;
A sidewall made of a second insulating film formed in a region other than the second recess in the first recess;
A gate insulating film formed in the second recess and on the side wall made of the second insulating film and on the first insulating film;
The field effect transistor using a nitride semiconductor, wherein the T-type gate electrode is formed on the gate insulating film so as to be embedded without a gap. A field effect transistor using a nitride semiconductor,
The layered structure of the nitride semiconductor is
An electron transit layer made of GaN or InGaN;
An electron supply layer made of AlGaN;
Including a structure in which contact layers made of AlGaN are stacked in this order;
The field effect transistor is:
A source electrode and a drain electrode formed on the contact layer;
A T-type gate electrode provided between the source electrode and the drain electrode;
In the region where the T-type gate electrode is provided,
A first recess formed by etching away the contact layer at a portion between the source electrode and the drain electrode;
A first insulating film formed under the umbrella of the T-type gate electrode in a region other than the first recess on the contact layer;
A second recess formed by reducing the thickness of the electron supply layer in a part of the first recess;
A sidewall made of a second insulating film formed in a region other than the second recess in the first recess;
The field effect transistor using a nitride semiconductor, wherein the T-type gate electrode is formed to be embedded in the second recess without any gap. A field effect transistor using a nitride semiconductor,
The layered structure of the nitride semiconductor is
An electron transit layer made of GaN or InGaN;
An electron supply layer made of AlGaN;
Including a structure in which contact layers made of AlGaN are stacked in this order;
The field effect transistor is:
A source electrode and a drain electrode formed on the contact layer;
A T-type gate electrode provided between the source electrode and the drain electrode;
In the region where the T-type gate electrode is provided,
A first recess formed by etching away the contact layer at a portion between the source electrode and the drain electrode;
A first insulating film formed under the umbrella of the T-type gate electrode in a region other than the first recess on the contact layer;
A second recess formed by reducing the thickness of the electron supply layer in a part of the first recess;
A sidewall made of a second insulating film formed in a region other than the second recess in the first recess;
The T-type gate electrode is embedded in the second recess without any gap;
On the contact layer excluding the region where the T-type gate electrode is provided, on the region where the first insulating film is not formed, on the source electrode and on the drain electrode, and on the T-type gate electrode A field effect transistor using a nitride semiconductor, comprising an ohmic auxiliary electrode formed. A method of manufacturing a field effect transistor using a nitride semiconductor,
Forming a layered structure of the nitride semiconductor including at least an electron transit layer made of a nitride semiconductor, an electron supply layer, and a contact layer by epitaxial growth; and
Forming a source electrode and a drain electrode on the contact layer;
Forming a first insulating film on the source and drain electrodes and the contact layer;
Etching away the first insulating film at a portion between the source electrode and the drain electrode;
Using the first insulating film as a mask, etching the contact layer to form a first recess;
Forming a second insulating film covering at least the first recess;
Performing anisotropic etching on the second insulating film to form a sidewall made of the second insulating film in the first recess;
Etching the electron supply layer using the sidewall as a mask to form a second recess;
Forming a gate insulating film;
Forming a T-type gate electrode on the gate insulating film in the second recess without a gap;
Removing the first insulating film by anisotropic etching using the umbrella of the T-type gate electrode as a mask;
And a step of forming an ohmic auxiliary electrode. A method of manufacturing a field effect transistor using a nitride semiconductor,
Forming a layered structure of the nitride semiconductor including at least an electron transit layer made of a nitride semiconductor, an electron supply layer, and a contact layer by epitaxial growth; and
Forming a source electrode and a drain electrode on the contact layer;
Forming a first insulating film on the source and drain electrodes and the contact layer;
Etching away the first insulating film at a portion between the source electrode and the drain electrode;
Using the first insulating film as a mask, etching the contact layer to form a first recess;
Forming a second insulating film covering at least the first recess;
Performing anisotropic etching on the second insulating film to form a sidewall made of the second insulating film in the first recess;
Etching the electron supply layer using the sidewall as a mask to form a second recess;
Forming a gate insulating film;
Forming a T-type gate electrode on the gate insulating film in the second recess without a gap;
A method for producing a field effect transistor, comprising: A method of manufacturing a field effect transistor using a nitride semiconductor,
Forming a layered structure of the nitride semiconductor including at least an electron transit layer made of a nitride semiconductor, an electron supply layer, and a contact layer by epitaxial growth; and
Forming a source electrode and a drain electrode on the contact layer;
Forming a first insulating film on the source and drain electrodes and the contact layer;
Etching away the first insulating film at a portion between the source electrode and the drain electrode;
Using the first insulating film as a mask, etching the contact layer to form a first recess;
Forming a second insulating film covering at least the first recess;
Performing anisotropic etching on the second insulating film to form a sidewall made of the second insulating film in the first recess;
Etching the electron supply layer using the sidewall as a mask to form a second recess;
Forming a T-type gate electrode in the second recess without gaps;
A method for producing a field effect transistor, comprising: A method of manufacturing a field effect transistor using a nitride semiconductor,
Forming a layered structure of the nitride semiconductor including at least an electron transit layer made of a nitride semiconductor, an electron supply layer, and a contact layer by epitaxial growth; and
Forming a source electrode and a drain electrode on the contact layer;
Forming a first insulating film on the source and drain electrodes and the contact layer;
Etching away the first insulating film at a portion between the source electrode and the drain electrode;
Using the first insulating film as a mask, etching the contact layer to form a first recess;
Forming a second insulating film covering at least the first recess;
Performing anisotropic etching on the second insulating film to form a sidewall made of the second insulating film in the first recess;
Etching the electron supply layer using the sidewall as a mask to form a second recess;
Forming a T-type gate electrode in the second recess without gaps;
And a step of forming an ohmic auxiliary electrode.

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