JPH09306927A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make gate length of a GaAs-MESFET short and to be able to form with high precision by such means as providing a GaAlAs stopper layer on a GaAs active layer, forming a side wall on a side surface of an opening part formed on a GaAs ohmic layer, forming a recess by masking the side wall and so on. SOLUTION: A first conductive GaAlAs stopper layer 3 of which carrier density is about the same as of a GaAs active layer 2 is provided on the GaAs active layer 2 of a GaAsMESFET and a stopper insulating film 5 is provided on a GaAs ohmic layer 4. An insulating side wall 7 is so formed on a side surface of an opening part 6 on the ohmic layer 4 as to be mounted on a part of the GaAlAs stopper layer 3 and a recess 10 is formed by eliminating the GaAlAs stopper layer 3 on the bottom of the opening part 6 which exists out of the side wall 7. A gate electrode 11 is formed on the bottom of the recess 10 and ohmic electrodes 15 and 16 are formed on the GaAs ohmic layer 4 by partially eliminating the stopper insulating film 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a low noise and high gain Ga for communication.
The present invention relates to a technique effectively applied to a manufacturing technique of AsMMIC.

[0002]

2. Description of the Related Art In the manufacture of semiconductor devices such as semiconductor integrated circuit devices, microfabrication has progressed, and microfabrication beyond the resolution by lithography is required. In particular, miniaturization of the gate in the FET is indispensable for improving the device performance.

As a processing method for forming a fine pattern of resolution or more by lithography, there is a technique of anisotropically etching the insulating film on the side surface of the spacer insulating film (spacer film) to leave it as a side wall and making it smaller than the opening size by lithography. Are known.

Regarding the technique of determining the size of the opening by the side wall, for example, "Technical Research Report of The Institute of Electronics, Information and Communication Engineers" Vol.94 No.429 P13-P18 is published.
[ED94-130 0.3 μm-Si bipolar process technology for ultra high-speed LSI].

This document describes a technique for forming the width of the emitter opening of a bipolar transistor to 0.3 μm by utilizing a side wall. That is, a thin oxide film and a thick spacer film are formed on a two-layered polysilicon having a partial opening by a CVD method, and then the spacer film is etched by dry etching to form sidewalls on the side surfaces of the opening. . Then, the oxide film (thickness: 50 nm) is etched using the sidewalls as a mask, doped with phosphorus and heat-treated to form a shallow emitter layer.

On the other hand, as one of the communication MMICs, Ga
A semiconductor device incorporating an As-MESFET is known. For example, Baifukan Co., Ltd. “Ultra High Speed Compound Semiconductor Device” issued on November 30, 1986, P72 contains MESFE
As one of Ts, an n ⁺ recess gate structure in which a gate electrode is formed on an n type operation layer and an ohmic electrode to be a source / drain electrode is provided on an n ⁺ type layer provided on the operation layer is described. ing.

[0007]

[Problems to be Solved by the Invention] Recess gate structure G
In manufacturing the aAs-MESFET, when a sidewall is formed on the side surface of the opening of the spacer insulating film to perform etching to form a recess, and a gate electrode having a Schottky barrier junction structure is formed on the recess bottom, It has been clarified by the present inventors that the following problems occur.

That is, a method of anisotropically etching an insulating film on a side surface of the spacer insulating film to leave it as a side wall, and making the opening size of the opening smaller by etching using the side wall as a mask is described in The side wall forming insulating film is formed of a SiO ₂ type or SiN type material that is etched by F radicals. Therefore, when the sidewall is processed, both the spacer insulating film and the insulating film for forming the sidewall are etched by F radicals, so that the selection ratio is insufficient.
As a result, side wall film side etching occurs due to the reduction of the spacer insulating film, the remaining side wall insulating film has a non-uniform thickness, and the gate length may not be formed accurately.

In addition, a stopper layer (etching stopper) may be formed as a protective film on the semiconductor layer in order to prevent damage to the underlying semiconductor layer when processing the sidewall forming insulating film. . However, since the stopper layer is also formed of a SiN-based insulating film, it is etched by F radicals similarly to the sidewall forming insulating film, so that the etching selection ratio is insufficient. Therefore, in order to prevent damage to the underlying semiconductor layer, it is necessary to make the stopper layer thick, but if the stopper layer becomes thick, it becomes difficult to perform fine processing.

Further, the GaAs-MESFET has many defects in that there are many interface levels between the insulating film and GaAs, the surface depletion layer is widened thereby, and the parasitic resistance between the gate and the source increases. One of the methods to overcome this is a recess gate structure or an n ⁺ recess gate structure. In the recess gate structure, a portion of the FET operating layer (active layer) immediately below the gate is removed by etching to obtain a desired channel layer thickness, and the thickness of the n-layer region between the source and the gate is made larger than the channel layer thickness. Reduce the parasitic resistance.

However, this recess gate structure is not suitable for a highly integrated circuit, because the desired channel layer thickness is obtained by etching, and the variation in etching directly affects the IC yield.

An object of the present invention is GaAs-MESFET.
It is an object of the present invention to provide a semiconductor device capable of shortening the gate length and accurately forming the gate length, and a manufacturing method thereof.

Another object of the present invention is GaAs-MESF.
It is an object of the present invention to provide a semiconductor device that can reduce the parasitic resistance of ET and a manufacturing method thereof.

The above and other objects and novel features of the present invention will be apparent from the description of the present specification and the accompanying drawings.

[0015]

The following is a brief description of an outline of typical inventions disclosed in the present application.

(1) A semiconductor device comprises a semi-insulating GaAs substrate and a first conductivity type (n type) formed on the main surface of the substrate.
GaAs operating layer and Ga formed on the GaAs operating layer and having a higher carrier concentration than the GaAs operating layer.
An As ohmic layer, an opening formed by selectively etching a portion of the GaAs ohmic layer, and a gate electrode formed on the GaAs operating layer at the bottom of the opening and insulated from the GaAs ohmic layer. And the Ga
GaAs-MESFE comprising ohmic electrodes serving as source / drain electrodes formed on the As ohmic layer
A semiconductor device having T, wherein a GaAlAs stopper layer of the first conductivity type is provided on the GaAs operating layer and has a carrier concentration substantially the same as that of the GaAs operating layer, and a stopper provided on the GaAs ohmic layer. An insulating film, an insulating side wall formed on a part of the GaAlAs stopper layer and formed on a side surface of the opening, and a recess formed by removing the GaAlAs stopper layer at the bottom of the opening separated from the side wall. The gate electrode formed on the bottom of the recess and the stopper insulating film are partially removed to remove the G
and an ohmic electrode formed on the aAs ohmic layer.

The GaAlAs stopper layer has an Al mixed crystal ratio x (0.4) which enables selective etching with respect to GaAs.
And the stopper insulating film is G
The aGaAs ohmic layer and the GaAlAs stopper layer are formed of a material which is not etched by an etching means for etching the aGaAs ohmic layer and the GaAlAs stopper layer and an etching means at the time of forming the sidewall and which can selectively etch the GaAs ohmic layer, and the sidewall etches the GaAlAs stopper layer. It is made of a material that is not etched by the etching means.

The GaAs operating layer and the GaAlAs stopper layer each have a thickness of several tens nm, and the Ga
The As ohmic layer has a thickness of several 100 nm, and the stopper insulating film has a thickness of several nm.

Such a semiconductor device has a semi-insulating GaA structure.
A GaAs operating layer of the first conductivity type (n type) on the main surface of the s substrate,
The first has a carrier concentration substantially the same as that of the GaAs operating layer
A step of sequentially forming a conductive GaAlAs stopper layer, a first conductive type GaAs ohmic layer having a higher carrier concentration than the GaAs operating layer, and a stopper insulating film, and remaining after selectively etching the stopper insulating film. A step of etching the GaAs ohmic layer to the GaAlAs stopper layer to form an opening by using the stopper insulating film and the GaAlAs stopper layer as an etching stopper; and a step of forming a sidewall forming insulating film on the main surface of the substrate, The stopper insulating film and GaAlA
etching the side wall forming insulating film using the s stopper layer as an etching stopper to form a side wall on the side surface of the opening to form a recess forming groove;
Etching the GaAlAs stopper layer using the stopper insulating film on the ohmic layer and the sidewall as an etching mask to form a recess, forming a gate electrode on the bottom of the recess, and stopper on the GaAs ohmic layer It is manufactured by a step of selectively removing the insulating film and forming ohmic electrodes to be source / drain electrodes in the removed portion.

The GaAlAs stopper layer has a mixed crystal ratio x (0.4) of Al that enables selective etching with respect to GaAs.
And the stopper insulating film is G
The aGaAs ohmic layer and the GaAlAs stopper layer are formed of a material which is not etched by an etching means for etching the aGaAs ohmic layer and the GaAlAs stopper layer and an etching means at the time of forming the sidewall and which can selectively etch the GaAs ohmic layer, and the sidewall etches the GaAlAs stopper layer. It is made of a material that is not etched by the etching means.

The stopper insulating film is made of AlN or Al ₂ O ₃
And selectively etched by dry etching with Cl radicals, the GaAs ohmic layer is selectively etched by dry etching with Cl-based gas, and the sidewall forming insulating film is formed of SiN and dry by F radicals. It is selectively etched by etching, and the GaAlAs stopper layer is H
It is etched with an F-based etching solution.

The GaAs operating layer and the GaAlAs stopper layer each have a thickness of several tens nm, and the Ga
The As ohmic layer has a thickness of several 100 nm, and the stopper insulating film has a thickness of several nm.

(2) Semi-insulating G having a GaAs operating layer and a GaAlAs stopper layer (Al mixed crystal ratio x 0.4 or more) having substantially the same carrier concentration in the means (1).
This is a method for obtaining an aAs substrate, which is a non-insulating GaAlAs layer (A
(a mixed crystal ratio of l × 0.4 or more) is epitaxially formed, and then a desired impurity is implanted using the selectively formed photoresist film as a mask so that the peak concentration of the impurity is the Ga
It is formed so as to be near the interface of the AlAs layer, and then annealed to form a Ga and GaAs operating layer having a carrier concentration approximately the same.
An AlAs stopper layer is formed.

According to the means (1), (a) GaA
After selectively etching the s ohmic layer to form an opening, and forming a sidewall on the side surface of the opening, the sidewall of the GaAs ohmic layer is completely etched with respect to the etching of the sidewall forming insulating film. GaAlAs stopper layer and stopper insulating film having the following etching selection ratio are provided in advance, and then the stopper insulating film and the GaAs ohmic layer are etched to form an opening, and then a sidewall forming insulating film is formed and a sidewall forming insulating film is formed. Since the side wall is formed by anisotropically etching the insulating film,
During the anisotropic etching, the anisotropic etching is stopped by the stopper insulating film separated from the opening, and the height (thickness) of the spacer film including the GaAs ohmic layer and the stopper insulating film is low (thin). 2), the overhanging length of the side wall is always constant and the size of the recess forming opening is constant, and as a result, a constant gate length can be formed.

(B) Since the recess forming opening is formed by using the side wall, the gate length can be shortened.

(C) The GaAlAs stopper layer is a number 1
Since the thickness is 0 nm and the stopper insulating film is as thin as several nm, fine processing can be achieved.

(D) Since the GaAlAs stopper layer as an etching stopper is provided on the GaAs operating layer, the surface of the GaAs operating layer is not damaged by the etching at the time of forming the opening and the sidewall, and the characteristics are stable. It is possible to manufacture such a semiconductor device.

(E) The recess is GaA on the GaAs operating layer.
Since it is formed by etching only the 1As stopper layer, the thickness of the channel layer at the bottom of the recess is formed by the GaAs operating layer whose film thickness and film quality are made uniform by epitaxial growth. Is improved and the characteristics of the GaAs-MESFET are stabilized.

(F) GaAlAs stopper layers are present on both sides of the recess, and G having a high impurity concentration is present on both sides of the opening.
Since the aAs ohmic layer is present, the parasitic resistance can be reduced.

(G) Shorter gate length due to the ability to always form a side wall with a constant thickness, microfabrication due to the thin thickness of the GaAlAs stopper layer and stopper insulating film, constant channel layer thickness, channel Since it is possible to form a highly accurate GaAs-MESFET by preventing damage to the layer surface, it is possible to reduce the manufacturing cost and improve the integration of the semiconductor device by improving the yield.

According to the above-mentioned means (2), the semi-insulating GaAs substrate having the GaAs operating layer and the GaAlAs stopper layer having the same carrier concentration can be manufactured by a simple method.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments of the present invention, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

FIG. 1 is a sectional view showing an outline of a semiconductor device according to an embodiment of the present invention, FIGS. 2 to 7 are views relating to a method of manufacturing a semiconductor device according to the present embodiment, and FIG. FIG. 3 is a cross-sectional view showing a state in which a GaAs operating layer, a GaAlAs stopper layer, a GaAs ohmic layer and a stopper insulating film are formed on the main surface of a GaAs substrate. FIG. 3 shows an opening formed by selectively etching the stopper insulating film and the GaAs ohmic layer. 6 is a sectional view showing a state where a side wall forming insulating film is formed on the main surface of the substrate, FIG. 5 is a sectional view showing a side wall forming state by etching the side wall forming insulating film, and FIG. FIG. 7 is a sectional view showing a state in which a recess is formed by etching using the sidewall and the stopper insulating film as an etching mask, and FIG. 7 is a sectional view showing a state in which a gate electrode is formed on the recess bottom.

In this embodiment, an example in which the present invention is applied to a GaAs-MESFET incorporated in a semiconductor device will be described.

The semiconductor device of this embodiment has a semi-insulating Ga.
It is formed using the As substrate 1. Semi-insulating GaAs
On the main surface of the substrate 1, for example, a GaAs operating layer 2 composed of a GaAs layer of the first conductivity type (n type) having a thickness of several 10 nm.
And a thickness of 10 n formed on the GaAs operating layer 2
A GaAlAs stopper layer 3 of m 1st conductivity type (n-type) Ga _1-x Al _x As is provided. This Ga
The Al mixed crystal ratio x of the AlAs stopper layer 3 is 0.4 or more, and HF wet etching can be selectively etched with respect to GaAs. Since the GaAs operating layer 2 is formed by epitaxial growth, the film thickness and film quality are uniform.

On the GaAlAs stopper layer 3, a thickness of several 10 having a higher impurity concentration than the GaAs operating layer 2 is provided.
Ga consisting of a 0 nm first conductivity type (n-type) GaAs layer
An As ohmic layer 4 is provided. Furthermore, the G
A stopper insulating film 5 made of AlN or Al ₂ O ₃ having a thickness of several nm is provided on the aAs ohmic layer 4.

The stopper insulating film 5 and the GaAs ohmic layer 4 under the stopper insulating film 5 are selectively etched to form an opening 6. And
An insulating side wall 7 made of, for example, SiN is formed on the side surface of the opening 6.

On the other hand, the GaAlAs stopper layer 3 portion of the bottom portion of the opening 6 which is separated from the side wall 7 is etched to form a recess 10.

A gate electrode 11 is formed on the GaAs operating layer 2 at the bottom of the recess 10. The gate electrode 11 is formed of a lower layer electrode 12 made of WSi or the like, which has stable interface characteristics with GaAs, and an upper layer electrode 13 made of a low resistance metal such as Au or Al.

GaA is sandwiched between the gate electrodes 11.
Ohmic electrodes 15 and 16 serving as source / drain electrodes are provided on the s ohmic layer 4.

An insulating film 20 is provided on the stopper insulating film 5 and the gate electrode 11.

In the above structure, the predetermined material is formed of a material that acts as an etching mask or an etching stopper by each etching means in the manufacturing. That is, as described above, Ga _1-X Al _X As
The GaAlAs stopper layer 3 made of Al has an Al mixed crystal ratio x of 0.4 or more so that it can be selectively etched with respect to GaAs. Therefore, the GaAlAs stopper layer 3 acts as an etching stopper when the GaAs ohmic layer 4 is etched (dry etching with a chlorine-based gas).

Further, the stopper insulating film 5 is an etching means for etching the GaAs ohmic layer 4 and the GaAlAs stopper layer 3 (dry etching with a chlorine-based gas or wet etching with HF) and an etching means for forming the side wall 7 ( Is not etched by anisotropic dry etching with F radicals) and the GaAs
The ohmic layer 4 is formed of a material (AlN or Al ₂ O ₃ ) capable of performing selective etching (dry etching using Cl radicals, wet etching using hot phosphoric acid, or ion milling).

The side wall 7 is formed of a material (SiN or the like) which is not etched by the etching means (wet etching with HF) for etching the GaAlAs stopper layer 3.

Next, a method of manufacturing the semiconductor device of this embodiment will be described.

First, as shown in FIG. 2, a semi-insulating GaAs substrate 1 having a predetermined thickness is prepared. This semi-insulating GaAs
On the main surface of the substrate 1, a GaAs operating layer 2 composed of a GaAs layer of the first conductivity type (n type) 2 and GaA of the first conductivity type (n type)
lAs stopper layer 3, GaAs ohmic layer 4 composed of GaAs layer of the first conductivity type (n type) 4, AlN or Al ₂
A stopper insulating film 5 made of O ₃ or the like is sequentially laminated.

The GaAs operating layer 2 is a layer for forming a channel layer, has a predetermined impurity concentration (carrier concentration), and has a thickness of several tens nm. Further, since the GaAs operating layer 2 is formed by epitaxial growth and has a uniform film thickness and film quality, a desired drain / source current can be obtained when used as a channel layer.

The GaAlAs stopper layer 3 is formed of the G
The impurity concentration is substantially the same as that of the aAs operating layer 2, and the thickness thereof is several tens nm. G consisting of Ga _1-X Al _X As
The aAlAs stopper layer 3 is selected to have a mixed crystal ratio x of Al of 0.4 or more, and is made of GaAs by HF wet etching.
It becomes possible to selectively etch. In addition, GaAlAs
Since the stopper layer 3 is made of the same material, the lower GaA layer is formed.
The interface characteristics are stable with respect to the s-motion layer 2. Also,
The GaAlAs stopper layer 3 acts as an etching stopper during etching when forming the opening 6 and the side wall 7, and also acts as a protective film for preventing damage of the GaAs operating layer 2 due to etching. GaAl
At the time of etching, the As stopper layer 3 is etched by wet etching with HF.

The GaAs ohmic layer 4 is made of GaA.
The impurity concentration is higher than that of the s-operation layer 2, and ohmic contact can be established between the ohmic electrodes 15 and 16. The thickness of this GaAs ohmic layer 4 is several tens.
It is 0 nm. At the time of etching, the GaAs ohmic layer 4 is etched by dry etching using a chlorine-based gas (for example, CCl ₂ F ₂ + He).

The stopper insulating film 5 is formed by etching means for etching the GaAs ohmic layer 4 (dry etching by chlorine gas), etching means for etching the GaAlAs stopper layer 3 (wet etching by HF), and the side wall 7. The GaAs ohmic layer 4 is formed of a material which is not etched by the etching means at the time of formation and which can be selectively etched with respect to the GaAs ohmic layer 4.
For example, the side wall forming insulating film forming the side wall 7 is
Since the stopper insulating film 5 is formed of SiN that is etched by anisotropic dry etching using F radicals,
It is formed of AlN or Al ₂ O ₃ and is etched by dry etching using Cl radicals or wet etching using hot phosphoric acid. Further, since the stopper insulating film 5 is as thin as several nm, it can be etched by ion milling.

Next, as shown in FIG. 3, after the photoresist film 25 is selectively formed on the main surface side of the substrate 1, the photoresist film 25 is used as an etching mask and the GaAlAs on the GaAs operation layer 2 is formed. Using the stopper layer 3 as an etching stopper, the stopper insulating films 5 and G are formed.
The aAs ohmic layer 4 is etched to form an opening 6 in the gate formation region. The opening 6 is, for example,
The length is 0.3 μm.

The stopper insulating film 5 is made of AlN or Al.
_{Since it is made of 2} O _3, etc., it is etched by dry etching using Cl radicals or wet etching using hot phosphoric acid. In addition, since the stopper insulating film 5 is as thin as several nm, the stopper insulating film 5 can be formed by ion milling.
Can be selectively removed.

Further, since the stopper insulating film 5 is as thin as several nm, fine processing becomes possible and the opening 6 can be formed with high precision.

Although not shown in the figure, following this step, using the predetermined photoresist as a mask, the GaAs
The operating layer 2 is also removed to perform element isolation.

Next, after the photoresist film 25 is removed, as shown in FIG.
An insulating film 26 for forming a sidewall having a thickness of 0 nm is formed. The side wall forming insulating film 26 is used as an etching mask when the GaAlAs stopper layer 3 is etched. Therefore, the side wall forming insulating film 26 is not etched by the means for etching the GaAlAs stopper layer 3 (wet etching with HF), and is different from the stopper insulating film 5 made of AlN or Al ₂ O ₃ or the like. The material to be etched is selected. That is, the sidewall forming insulating film 26 is formed of SiN that is etched by anisotropic dry etching using F radicals.
It is formed by

Next, as shown in FIG. 5, the sidewall forming insulating film 26 is etched by anisotropic dry etching using F radicals to form sidewalls 7 on the side surfaces of the opening 6. In this etching means, since the stopper insulating film 5 and the GaAlAs stopper layer 3 act as an etching stopper, the side wall 7 is formed without etching the stopper insulating film 5 accompanying the etching of the side wall forming insulating film 26. The thickness of the spacer film composed of the GaAs ohmic layer 4 and the stopper insulating film 5 does not decrease, and the side wall 7 having a constant thickness (overhanging length) is always formed. These sidewalls 7 form a recess forming opening 27 having a smaller size than the opening 6 formed by lithography. The length of the recess forming opening 27 is, for example, 0.15 μm.

Next, as shown in FIG. 6, the opening 6 is formed by using the stopper insulating film 5 and the side wall 7 as an etching mask.
The GaAlAs stopper layer 3 exposed at the bottom of is etched by wet etching with HF. GaAlAs
Since the mixed crystal ratio x of Al of the stopper layer 3 is 0.4 or more, selective etching is possible, and the recess 10 can be formed without etching the GaAs operating layer 2 below the GaAlAs stopper layer 3. . Since the GaAlAs stopper layer 3 is as thin as several tens of nanometers, fine processing is possible, and the length of the recess 10 is 0.15 μm like the length of the recess forming opening 27. And, as a final result, this becomes a substantially gate length.

Next, as shown in FIG. 7, a metal such as WSi having a stable interface characteristic with respect to GaAs is formed on the main surface of the substrate 1 to a thickness of several 100 nm, and a low metal such as Au or Al is formed. Resistive metals are sequentially formed by vapor deposition or the like. After that, a photoresist film 30 is selectively formed on the low resistance metal, and then the low resistance metal and a metal having stable interface characteristics with respect to GaAs are etched by using the photoresist film 30 as an etching mask to etch the gate electrode 1.
Form one. The gate electrode 11 is formed by a lower layer 31 made of WSi having a Schottky barrier junction structure with respect to the operating layer 2 and an upper layer 32 made of Au, Al or the like and overlying the lower layer 31.

Next, after removing the photoresist film 30, as shown in FIG. 1, an insulating film 20 is formed on the main surface of the substrate 1, and the stopper insulating film 5 and the insulating film on both sides of the gate electrode 11 are formed. The film 20 is selectively etched to form ohmic electrodes 15 and 16 on the exposed GaAs ohmic layer 4 as source and drain electrodes. Further, the substrate 1 is cut vertically and horizontally to manufacture a semiconductor device incorporating a GaAs-MESFET as shown in FIG.

The semiconductor device and the method for manufacturing the same according to this embodiment have the following effects.

(1) The GaAs ohmic layer 4 is selectively etched to form the opening 6, and then the side wall 7 is formed on the side surface of the opening 6, the lower surface and the upper surface of the GaAs ohmic layer 4 are mainly covered. The GaAlAs stopper layer 3 and the stopper insulating film 5 having a perfect etching selectivity with respect to the etching of the side wall forming insulating film 26 are provided in advance, and then the stopper insulating film 5 and the G
After the aAs ohmic layer 4 is etched to form the opening 6, the sidewall forming insulating film 26 is formed, and the sidewall forming insulating film 26 is anisotropically etched to form the sidewall 7. During the anisotropic etching, the anisotropic etching is stopped by the stopper insulating film 5 separated from the opening 6, and the height (thickness) of the spacer film composed of the GaAs ohmic layer 4 and the stopper insulating film 5 is low ( Since the overhanging length of the side wall 7 is always constant and the size of the recess forming opening 27 is constant, the recess 10 formed by etching using the side wall 7 as an etching mask is formed with high accuracy. To be done. As a result, the gate length of the gate electrode formed by burying a metal in the recess 10 can be formed with high accuracy.

(2) Since the recess forming opening 27 is formed by utilizing the side wall 7, the gate length can be shortened.

(3) The GaAlAs stopper layer 3 has a thickness of several tens nm, and the stopper insulating film 5 has a thickness of several nm.
Since the thickness is thin, it is possible to achieve fine processing.

(4) Since the GaAlAs stopper layer 3 (Al mixed crystal ratio x 0.4 or more) as an etching stopper is provided on the GaAs operating layer 2, it is possible to perform etching when forming the opening and forming the sidewall. GaAs
It is possible to manufacture a semiconductor device having stable characteristics without damaging the surface of the operating layer 2.

(5) The recess 10 is the GaAs operating layer 2
Upper GaAlAs stopper layer 3 (Al mixed crystal ratio x 0.4
Only the above) are formed by etching.
As a result, the GaAs operating layer 2 at the bottom of the recess becomes a channel layer. Since the GaAs operating layer 2 is formed with uniform film thickness and film quality by epitaxial growth, the reproducibility of the thickness of the channel layer is improved, and the characteristics of the GaAs-MESFET are stabilized.

(6) GaAl is formed on both sides of the recess 10.
Since the As stopper layer 3 exists and the GaAs ohmic layer with a high impurity concentration exists on both sides of the opening 6, the parasitic resistance can be reduced. That is, GaAs operating layer 2 and Ga
By selective etching with the AlAs stopper layer 3, the channel layer under the gate becomes a single layer of the GaAs operating layer 2, but the conductive portion under the side wall 7 has the GaAs operating layer 2 and GaAlAs.
Since it becomes the stopper layer 3, the parasitic resistance between the gate and the source can be reduced. Further, since the GaAs ohmic layer 4 is used as the spacer film for forming the side wall 7, the sheet resistance from the side wall 7 to the source electrode is lower than the sheet resistance below the side wall 7, and the parasitic resistance is reduced. Can be achieved.

(7) Shorter gate length due to the ability to always form the side wall 7 having a constant thickness (constant overhang length), G
Microfabrication by thinning the thickness of the aAlAs stopper layer 3 and the stopper insulating film 5, uniformization of the thickness of the channel layer (GaAs operating layer 2), channel layer (GaAs operating layer 2)
Highly accurate GaAs-MES by preventing surface damage
Since the FET can be formed, the manufacturing cost can be reduced and the semiconductor device can be highly integrated by improving the yield.

(Embodiment 2) FIGS. 8 and 9 are views relating to a method of manufacturing a semiconductor device according to another embodiment of the present invention. FIG. 8 is a semi-insulating GaAs having a non-doped GaAlAs layer on its main surface. FIG. 9 is a cross-sectional view showing a state in which a GaAs operation layer and a GaAlAs stopper layer are formed by selectively implanting and annealing impurities on the main surface of the substrate, and FIG. 9 shows a GaAs ohmic layer and a stopper insulating film sequentially formed on the main surface of the substrate. FIG. 6 is a cross-sectional view showing a state in which an opening is formed by selectively etching the stopper insulating film and the GaAs ohmic layer.

In the present embodiment, in order to obtain the semi-insulating GaAs substrate 1 having the GaAs operating layer 2 and the GaAlAs stopper layer 3 having substantially the same carrier concentration, as shown in FIG. Thickness of several 10 nm on the surface
Of the non-doped GaAlAs layer (Al mixed crystal ratio x 0.4 or more) is epitaxially formed, and then the desired impurity is implanted using the selectively formed photoresist film 40 as a mask so that the peak concentration of the impurity is the interface of the GaAlAs layer. The GaAs active layer 2 and the GaAlAs stopper layer 3 are formed so as to be close to each other and then annealed to form the GaAs operating layer 2 and the GaAlAs stopper layer 3 having substantially the same carrier concentration.

Then, after removing the photoresist film 40, as shown in FIG. 9, n-type G having a high carrier concentration and a thickness of several hundreds nm is formed on the main surface side of the semi-insulating GaAs substrate 1.
An aAs ohmic layer 4 and a stopper insulating film 5 made of AlN or Al ₂ O ₃ and having a thickness of several nm are formed.
The GaAs ohmic layer 4 and the stopper insulating film 5 serve as a spacer film for forming sidewalls. After that, through the same steps as those in the above-described embodiment (see FIGS. 3 to 7), the GaAs-MES
The FET is manufactured.

That is, in FIG. 9, the photoresist film 2 is formed on the spacer film, as in FIG. 3 in the above embodiment.
5 is selectively formed, and the photoresist film 2
An opening 6 is formed using 5 as an etching mask.

In the present embodiment, the semi-insulating GaAs substrate 1 having the GaAs operating layer 2 and the GaAlAs stopper layer 3 which have almost the same carrier concentration can be manufactured by a simple method.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say.

[0074]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) When the spacer film is selectively etched to form an opening for forming a recess in the gate formation region and a side wall is formed on the side surface of the opening, the spacer film is formed as a lower layer. Since the GaAs ohmic layer and the upper layer are formed of a stopper insulating film having a thickness of several nm, and the upper layer is formed of an insulating film which is not etched during the anisotropic etching of the side wall forming insulating film for forming the side wall. The spacer film is not thinned during the anisotropic etching, and the side wall having a constant thickness (constant overhang length) can be formed, so that the highly accurate recess forming opening can be formed. Since the stopper insulating film is as thin as several nm, fine processing becomes possible, and the dimensional accuracy of the opening becomes high, and therefore the dimensional accuracy of the recess forming opening also becomes high.

(2) Since a GaAlAs stopper layer of several tens of nm capable of being selectively etched is formed on the GaAs operating layer and a spacer film is formed on the GaAlAs stopper layer, the spacer film is selectively etched. To form a channel layer when forming an opening
The surface of the working layer is not damaged by etching. Further, the GaAlAs stopper layer has stable interface characteristics with respect to the GaAs operating layer. Moreover, since the GaAs operating layer is formed by epitaxial growth with stable film thickness and film quality, the channel layer is always constant. Therefore, a GaAs-MESFET having stable characteristics can be obtained.

(3) The selectively etchable GaAlAs exposed at the bottom of the opening using the sidewall as an etching mask.
Since the recess is formed by etching the stopper layer, the thickness of the GaAlAs stopper layer may be as thin as several tens of nm, so that the recess with high dimensional accuracy can be formed, and the gate length of the gate electrode formed by being embedded in the recess can be reduced. The dimensional accuracy is always constant.

(4) Since the recess forming opening and the recess are formed by using the side wall, a short gate length can be achieved.

(5) The conductive portion under the gate electrode is GaA
s operating layer only, the conductive portion at the bottom of the side wall becomes the GaAs operating layer and the GaAlAs stopper layer, and the GaAs operating layer, GaAlAs stopper layer, and G
Since it has a stacked structure of aAs ohmic layers, parasitic resistance can be reduced.

(6) Short gate length due to the ability to always form a side wall with a constant thickness, fine processing due to the thin thickness of the GaAlAs stopper layer and stopper insulating film, constant channel layer thickness, channel Since it is possible to form a highly accurate GaAs-MESFET by preventing damage to the layer surface, it is possible to reduce the manufacturing cost and improve the integration of the semiconductor device by improving the yield.

[Brief description of drawings]

FIG. 1 is a sectional view schematically showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 shows a method of manufacturing a semiconductor device according to the present embodiment,
On the main surface of the semi-insulating GaAs substrate, GaAs operating layer, GaA
FIG. 3 is a cross-sectional view showing a state where an 1As stopper layer, a GaAs ohmic layer, and a stopper insulating film are formed.

FIG. 3 shows a method of manufacturing a semiconductor device according to the present embodiment,
FIG. 6 is a cross-sectional view showing a state in which an opening is formed by selectively etching the stopper insulating film and the GaAs ohmic layer.

FIG. 4 shows a method of manufacturing a semiconductor device according to the present embodiment,
FIG. 4 is a cross-sectional view showing a state in which a side wall forming insulating film is formed on the main surface of the substrate.

FIG. 5 shows a method of manufacturing a semiconductor device according to the present embodiment,
It is sectional drawing which shows the state which formed the side wall by etching the insulating film for side wall formation.

FIG. 6 shows a method of manufacturing a semiconductor device according to the present embodiment,
FIG. 6 is a cross-sectional view showing a state in which a recess is formed by etching using the sidewall and the stopper insulating film as an etching mask.

FIG. 7 shows a method of manufacturing a semiconductor device according to the present embodiment,
It is sectional drawing which shows the state which formed the gate electrode on a recess bottom.

FIG. 8 is a view showing a semiconductor device manufacturing method according to another embodiment of the present invention, in which a GaAs ohmic layer and a GaAlAs stopper are formed by selectively implanting impurities into the main surface of a semi-insulating GaAs substrate having a non-doped GaAlAs layer on the main surface. It is sectional drawing which shows the state which formed the layer.

FIG. 9 is a view showing a method of manufacturing a semiconductor device according to another embodiment of the present invention, in which a GaAs ohmic layer and a stopper insulating film are sequentially formed on a main surface of a substrate, and then a stopper insulating film and a G are formed.
It is sectional drawing which shows the state which formed the opening part by selectively etching an aAs ohmic layer.

[Explanation of symbols]

1 ... Substrate (semi-insulating GaAs substrate), 2 ... GaAs operating layer, 3 ... GaAlAs stopper layer, 4 ... GaAs ohmic layer, 5 ... Stopper insulating film, 6 ... Opening portion, 7 ... Side wall,
10 ... Recess, 11 ... Gate electrode, 12 ... Lower layer electrode, 1
3 ... Upper layer electrode, 15, 16 ... Ohmic electrode, 20 ... Insulating film, 25 ... Photoresist film, 26 ... Sidewall forming insulating film, 27 ... Recess forming opening, 30 ... Photoresist film, 31 ... Lower layer, 32 ... Upper layer , 40 ... Photoresist film.

Claims (8)

[Claims] 1. A semi-insulating GaAs substrate, a GaAs operating layer of the first conductivity type formed on the main surface of the substrate, and the G
a GaAs ohmic layer formed on the aAs operating layer and having a carrier concentration higher than that of the GaAs operating layer;
an opening formed by selectively etching a part of the aAs ohmic layer, a gate electrode formed on the GaAs operating layer at the bottom of the opening and insulated from the GaAs ohmic layer, and the GaAs ohmic layer What is claimed is: 1. A semiconductor device having a GaAs-MESFET comprising an ohmic electrode serving as a source / drain electrode formed above, the semiconductor device being provided on the GaAs operation layer and comprising the GaAs
Ga of the first conductivity type whose carrier concentration is almost the same as that of the operating layer
An AlAs stopper layer, a stopper insulating film provided on the GaAs ohmic layer, an insulating side wall formed on a part of the GaAlAs stopper layer and formed on a side surface of the opening, and an opening separated from the side wall. GaAl on the bottom
A recess formed by removing the As stopper layer, a gate electrode formed on the bottom of the recess, and an ohmic electrode formed on the GaAs ohmic layer with the stopper insulating film partially removed. A semiconductor device characterized by: 2. The GaAlAs stopper layer is GaAs
The stopper insulating film is not etched by the etching means for etching the GaAs ohmic layer and the GaAlAs stopper layer or the etching means at the time of forming the side wall and has a mixed crystal ratio x of Al that enables selective etching. The GaAs ohmic layer is formed of a material that can be selectively etched, and the sidewall is formed of GaA.
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed of a material which is not etched by an etching means for etching the 1As stopper layer. 3. The first conductivity type is n-type, and the Ga
The As operating layer and the GaAlAs stopper layer each have a thickness of several tens nm, the GaAs ohmic layer has a thickness of several 100 nm, and the stopper insulating film has a thickness of several nm.
The semiconductor device according to claim 1 or 2, wherein 4. A GaAs operating layer of the first conductivity type on the main surface of the semi-insulating GaAs substrate, a GaAlAs stopper layer of the first conductivity type having a carrier concentration substantially the same as that of the GaAs operating layer, and a GaAs operating layer First with high carrier concentration
A step of sequentially forming a conductive type GaAs ohmic layer and a stopper insulating film, and a stopper insulating film and Ga remaining after the selective etching of the stopper insulating film.
Using the AlAs stopper layer as an etching stopper, the G
etching the aAs ohmic layer to the GaAlAs stopper layer to form an opening; forming a sidewall insulating film on the main surface of the substrate; and using the stopper insulating film and the GaAlAs stopper layer as etching stoppers. A step of etching the sidewall forming insulating film to form a sidewall on the side surface of the opening to form a recess forming groove; and a step of etching the Ga by using the stopper insulating film on the GaAs ohmic layer and the sidewall as an etching mask.
A step of forming a recess by etching the AlAs stopper layer, a step of forming a gate electrode on the bottom of the recess, a step of selectively removing the stopper insulating film on the GaAs ohmic layer, and a source / drain electrode in the removed portion. And a step of forming an ohmic electrode as described above. 5. A GaAs operating layer and a GaAlAs stopper layer (Al mixed crystal ratio × 0.4) having substantially the same carrier concentration.
The above is a method of obtaining a semi-insulating GaAs substrate having non-doped GaAl on the main surface of the semi-insulating GaAs substrate.
After the As layer (Al mixed crystal ratio x 0.4 or more) is epitaxially formed, desired impurities are implanted by using the selectively formed photoresist film as a mask so that the peak concentration of the impurities is near the interface of the GaAlAs layer. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the GaAs operating layer and the GaAlAs stopper layer having substantially the same carrier concentration are formed by annealing as described above. 6. The GaAlAs stopper layer is GaAs
The stopper insulating film is not etched by the etching means for etching the GaAs ohmic layer and the GaAlAs stopper layer or the etching means at the time of forming the side wall and has a mixed crystal ratio x of Al that enables selective etching. The GaAs ohmic layer is formed of a material that can be selectively etched, and the sidewall is formed of GaA.
6. The method of manufacturing a semiconductor device according to claim 4, wherein the lAs stopper layer is formed of a material that is not etched by an etching means. 7. The first conductivity type is n-type, the stopper insulating film is formed of AlN or Al ₂ O ₃ and is selectively etched by dry etching using Cl radicals, and the GaAs ohmic layer is Cl-based. Is selectively etched by dry etching with a gas, the sidewall forming insulating film is formed of SiN, and is selectively etched by dry etching with an F radical.
7. The method of manufacturing a semiconductor device according to claim 6, wherein the GaAlAs stopper layer is etched with an HF-based etching solution. 8. The GaAs operating layer and GaAlAs
Each of the stopper layers has a thickness of several tens of nm.
8. The method of manufacturing a semiconductor device according to claim 4, wherein the aAs ohmic layer has a thickness of several 100 nm, and the stopper insulating film has a thickness of several nm.