JPH0496338A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable a saturated drain current to be controlled precisely with a good repeatability and to reduce a gate and source resistance remarkably, by performing a recess etching while monitoring the saturated drain current. CONSTITUTION:After a buffer layer 101 of high purity and an activated layer 102 are laminated on a substrate 100 in succession, a metallic film for forming an ohmic contact is deposited. Further, a heat treatment is performed, and a base material 11S for a source electrode and a base material 11D for a drain electrode are formed. Then, after applying a resist film 12 thereto extensively, a through hole 13 of T-shape in section is formed in the resist film 12. Further, a recess etching is applied to the activated layer 102 via the through hole 13, while monitoring a saturated drain current. Continually, a metallic film for a gate electrode is deposited extensively, and a metallic film 14b in the through hole 13 and a metallic film 14a on the resist film 12 are provided. Then, by a lift-off method, the metallic film 14a on the resist film 12 and the resist film 12 itself are removed, and thereby, a gate electrode 14b of T-shape in section is formed. Continuously, a metallic film 15 for forming an ohmic contact is deposited, and after performing a heat treatment, a source electrode 16S and a drain electrode 16D are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device in which a method for forming electrodes is improved.

(Prior art) Field effect transistor (FET) or high electron mobility transistor (H
EMT) has been widely put into practical use as a semiconductor device that has excellent microwave characteristics and operates in the microwave band.

In order to further improve the microwave characteristics of these FETs, H, and EMTs, the gate length is shortened and parasitic resistances such as gate resistance and source resistance are reduced. This is very important.

To illustrate the current FET manufacturing method with reference to the process diagram shown in FIG. 2, as shown in FIG. 2(a), semi-insulating G
a High purity buffer layer 10 on the substrate 100
1. After sequentially stacking the active layer 102 by, for example, an epitaxial growth method, a metal film for forming an ohmic contact, for example, A
uGe/Ni is deposited and heat treated to form the active layer 102.
After forming a source electrode 103S and a drain electrode 103D which make ohmic contact with the resist film 103D, a resist film 104 is applied to the entire surface as shown in FIG. 2(b).

Holes 105 are formed in the resist film 104 according to a predetermined pattern.
The active layer 102 is recessed through the through hole 104. This recess etching is performed using FE.
This is performed for the purpose of controlling the saturated drain current of T, and during recess etching, the source electrode 103S and the drain electrode 1
By monitoring the drain current with 03D, the saturated drain current can be controlled with high precision. Next, a metal film for the gate electrode, for example AQ, is deposited on the entire surface, and the metal film portion on the resist film 104 and the resist are removed by a lift-off method. By removing the resist film 104, a gate electrode 106 is formed, and an FET as shown in FIG. 2(C) is formed.

Although this FET can easily control the saturated drain current, it has the following problems. That is, in order to improve the microwave characteristics of the FET, it is necessary to shorten the gate length and reduce the gate capacitance. However, by shortening the gate length, the cross-sectional area of the gate electrode 106 decreases, resulting in an increase in gate resistance. In particular, if the gate length is shortened to 0.26 μm or less, the gate resistance increases significantly, so no improvement in microwave characteristics can be expected.On the other hand, the source resistance is the resistance of the active layer 102 between the source and gate electrodes. Therefore, in order to reduce the source resistance, it is desirable to shorten the distance between the source and gate electrodes as much as possible.Moreover, since the source resistance fluctuates due to variations between the source and gate electrodes,
035 and the gate electrode 106 are required to have high overlay accuracy.

A method for solving the above problem is to shorten the gate length and reduce gate resistance by making the cross-sectional shape of the gate electrode 106 T-shaped, and to further reduce the source resistance, the gate electrode 106 is An FET in which the source electrode 103S is formed using a self-alignment method has been proposed. A method for manufacturing such an FET will be explained with reference to FIG. First, as shown in FIG. 3(a), a semi-insulating G
A high purity buffer layer 101, an active layer 102 . After sequentially stacking the resist films 104, the same figure (
As shown in b), a through hole 105 which is wide at the top and narrow at the bottom is formed in the resist film 104, and the active layer 102 is recessed through this hole 105 to a predetermined depth based on the thickness and carrier concentration of the active layer. Next, a metal film for the gate electrode is deposited on the entire surface, and the metal film on the resist film 104 and the resist film 104 are removed by a lift-off method to form a T-shaped cross section as shown in FIG. Next, using the gate electrode 116 as a mask, a metal film 103 for forming an ohmic contact is deposited and heat-treated to form the source electrode L.
O3S, forming a drain electrode 103D.

Further, among the metal films for forming ohmic contact, the metal film portion 103 deposited on the gate electrode 116 forms the gate electrode 106 as it is, thereby forming an FET as shown in FIG. 3(d). In this FET structure, by making the cross-sectional shape of the gate electrode 107 T-shaped, the cross-sectional area of the gate electrode increases, so even if the gate length is shortened, an increase in gate resistance can be suppressed. Since the electrode spacing is uniquely determined by the gate electrode shape, variations in source resistance within the wafer surface are small, and the gate-source spacing can be formed short, making this structure effective for reducing source resistance. It is.

According to the FET manufacturing method shown in FIG. 3, the depth of recess etching is determined based on information about the carrier concentration and film thickness of the active layer 102, since the current between the source and drain cannot be monitored. However, the variation in etching rate must be determined so that a saturated drain current of is obtained.

When considering variations in carrier concentration and film thickness between wafers due to instability of crystal growth.

It is extremely difficult to precisely control the saturation drain current of an FET with good reproducibility.

(Problems to be Solved by the Invention) As described above, with the conventional FET structure, it is extremely difficult to reduce the gate resistance and source resistance and precisely control the saturation drain current with good reproducibility. eliminates such shortcomings.

It is an object of the present invention to provide a method for manufacturing a semiconductor device that can reduce both gate resistance and source resistance, and can precisely control saturation drain current with good reproducibility.

[Structure of the invention]

(Means for Solving the Problems) A method for manufacturing a semiconductor device according to the present invention includes a step of forming a source electrode and a drain electrode on a compound semiconductor substrate;
a step of performing recess etching on a region where a gate electrode is to be formed between the source electrode and the train electrode on the compound semiconductor substrate; a step of forming a gate electrode having a T-shaped cross section in contact with the lower surface in the recess; The method is characterized by including a step of depositing a metal film for forming an ohmic contact in a region including the source electrode and drain electrode using the gate electrode as a mask to form a new source electrode and drain electrode.

(Function) In the method for manufacturing a semiconductor device according to the present invention, since recess etching can be performed while monitoring the saturated drain current, the saturated drain current can be precisely controlled with good reproducibility. Since the gate electrode has a shape and the source electrode and gate electrode can be formed in a self-alignment manner, gate resistance and source resistance can be reduced.

(Example) An embodiment of the present invention will be described with reference to the drawings.

In addition, in the description, parts that are the same as in the prior art will be shown with the same numbers as in the conventional drawings, and the explanation will be omitted.

As shown in FIG. 1(a), a semi-insulating GaAs substrate 10
After sequentially laminating a high-purity buffer layer 101 and an active layer 102 on the
e/Ni is deposited and heat treated to form the source electrode base 11S.
, the primary resist forming the drain electrode base 110 [
After coating the resist film 12 on the entire surface, a through hole 13 having a T-shaped cross section is formed in the resist film 12 according to a predetermined pattern as shown in FIG. 1(b). As described in the conventional example with reference to FIG. Drain current can be controlled. Next, Figure 1(c)
As shown in FIG.
/ Ti is vapor-deposited on the entire surface to provide the metal film 14b inside the through hole 13 and the metal film portion a on the resist 1112.

Next, gold Jji on the resist film 12 is removed by a lift-off method.
By removing C1114a and the resist 11fi+2, a gate electrode F@(substrate) 14b having a T-shaped cross-sectional shape as shown in FIG. 3(d) is formed. Here, by making the cross-sectional shape of the gate electrode T-shaped, the cross-sectional area of the gate electrode can be increased, and the gate resistance can be reduced even if the gate length is shortened. 14
Ohmic contact forming metal 11 [15
For example, by depositing AuGe/Ni and performing heat treatment, a new source current 1i16s and drain current 160 are formed, and of the metal film 15 for forming an ohmic contact, the metal film portion deposited on the gate electrode is left as it is. The gate electrode 116G is configured using the steps shown in FIG.

In FIG. 1(e), the source electrode 165 and the gate electrode 1
6G is because it can be formed by self-alignment.

The distance between the source and gate electrodes is determined by the shape,
Moreover, it is possible to form a short interval.

Variation in the source resistance within the wafer surface is small, and the source resistance can be reduced.

In this example, A is used as the metal film for forming ohmic contact.
Although the case where uGe/Ni is used has been described, the metal film for forming ohmic contact is not limited to AuGe/Ni, and may be a metal film such as Pt/AuGe, ^U/^uGe, etc.

(Effects of the Invention) As described above, in the method for manufacturing a semiconductor device according to the present invention, recess etching can be performed while monitoring the saturated drain current. It is also possible to precisely control the saturation drain current with good reproducibility. Furthermore,
Since the gate electrode has a T-shaped cross section and the source electrode and gate electrode can be formed in a self-alignment manner, there is an advantage that the gate resistance and the source resistance can be significantly reduced.

[Brief explanation of the drawing]

Figures 1 (Q) to 1 (,) are cross-sectional views showing one embodiment of the present invention in the order of steps, Figures 2 (, l) to 2 (C), and Figure 3 (a). ) to FIG. 3(d) are sectional views showing the conventional FET manufacturing method in the order of steps. 12...Resist film 13...Through hole 15.
...Metal film for ohmic contact formation 16G...Gate electrode Fi165...Source electrode 16rl...Drain electrode
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Claims (1)

[Claims] forming a source electrode and a drain electrode on a compound semiconductor substrate; etching a recess in a region where a gate electrode is to be formed between the source electrode and the drain electrode on the compound semiconductor substrate; A step of forming a contacting gate electrode with a T-shaped cross section, and a step of vapor depositing a metal film for forming an ohmic contact in a region including the source electrode and drain electrode using the gate electrode as a mask to form a new source electrode and drain electrode. A method for manufacturing a semiconductor device, comprising: