KR930011290A

KR930011290A - Manufacturing method of MESFET

Info

Publication number: KR930011290A
Application number: KR1019910019957A
Authority: KR
Inventors: 김기철
Original assignee: 이헌조; 주식회사 금성사
Priority date: 1991-11-11
Filing date: 1991-11-11
Publication date: 1993-06-24

Abstract

본 발명은 MESFET의 제조법과 관련된 것으로서, 종래에는 이러한 소자의 채널을 화학적 에칭 기술로서 형성시키므로써 그 채널의 균질한 두께를 보장할 수 없어서 그 소자특성의 균일성을 획득하기 어려운 것이었으며 게이트 형성시에도 평판면의 단차로 인해 게이트 형성의 정확성을 가지기 어려운 것이었다.The present invention relates to a method of manufacturing a MESFET, and in the related art, since the channel of such a device is formed by a chemical etching technique, it is difficult to guarantee a uniform thickness of the channel, and thus it is difficult to obtain uniformity of the device characteristics. Due to the step height of the flat plate, it was difficult to have the accuracy of gate formation.

본 발명은 상기와 같은 종래기술에서의 공정상의 문제점을 개선할 수 있도록 기판(11)에 버퍼층(12), 액티브층(13)을 형성시키는 차단막 역할을 하는 게이트 금속(14) 및 절연막(15)형성의 공정 및, 상기 절연막을 선택적 식각하여 게이트금속(14)의 측부에 절연막(15)을 남겨둔채 오믹용 에피층(16)을 형성하는 공정 및, 메사층 형성소스, 드레인 형성의 공정을 포함하는 처리방법의 MESFET 제조법을 제공하는데 있다.According to the present invention, the gate metal 14 and the insulating film 15 which serve as a blocking film for forming the buffer layer 12 and the active layer 13 on the substrate 11 can improve the process problems in the prior art as described above. And forming the epitaxial layer 16 for ohmic, leaving the insulating film 15 on the side of the gate metal 14 by selectively etching the insulating film, and forming a mesa layer source and drain. The present invention provides a method for manufacturing a MESFET.

Description

Manufacturing method of MESFET

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도 (a) 내지 (g)는 본 발밍의 제조공정을 나타낸 실시예도이다.2 (a) to 2 (g) are exemplary views showing the manufacturing process of the present balming.

Claims

An insulating film for sequentially forming a buffer layer 12 and an active layer 13 on the substrate 11, forming a gate metal serving as a blocking film on the active layer, and separating a gate and an ohmic epi layer on the gate metal. After forming 15), only the part which is not necessary for growth is etched, and the rest is etched, and after the selective insulating film viewing, the epi layer 16 for ohmic is formed, and the mesa layer is formed to form the source and drain electrodes. And a drain electrode is formed.

※ Note: The disclosure is based on the initial application.