JP6047998B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device in which a nitride compound semiconductor is formed on a substrate.

  Since nitride-based compound semiconductors such as gallium nitride have a high dielectric breakdown electric field, they are expected to be applied to low-loss high-voltage power devices. Therefore, it is desired not only to have good characteristics but also to produce a device at low cost. In view of these points, it is desirable to use a silicon (Si) substrate or the like that is easy to manufacture a large-diameter substrate, not a nitride-based single crystal substrate, as a growth substrate for the nitride-based compound semiconductor layer. Yes. For example, Patent Document 1 discloses a nitride-based semiconductor device formed on a silicon substrate using a known metal organic chemical vapor deposition (MOCVD) method. In such a nitride semiconductor device, if the nitride semiconductor layer is formed thick, cracks and the like are likely to occur, and the nitride semiconductor device cannot be formed so thick. As a result, when the thickness of the nitride semiconductor layer is sufficiently smaller than the distance between the source electrode and the drain electrode, for example, in the off state of the semiconductor device, the drain electrode passes through the buffer layer and the silicon (Si) substrate. As a result, there is a problem that a leak current flowing into the source electrode is likely to occur.

  In addition, the edge portion of the nitride semiconductor device is generally formed by using dry etching to form a mesa shape or a trench shape on the upper surface of the nitride-based compound semiconductor layer to form an element isolation (peripheral isolation) structure. However, since the outer peripheral isolation structure is formed using dry etching, crystal defects or the like are generated on the side wall of the nitride-based compound semiconductor layer. As a result, the vicinity of the outer peripheral isolation structure formed in the nitride-based compound semiconductor layer becomes a passage through which a leak current flows due to a lower resistance than other portions of the nitride semiconductor layer, and the breakdown voltage of the nitride semiconductor device is reduced. Or cause destruction. As a means for solving such a problem, for example, there is a method of Patent Document 2. In the nitride semiconductor device of Patent Document 2, the outer peripheral electrode is disposed on the end side of the nitride-based compound semiconductor layer with respect to the source electrode, and a depletion layer reaching the channel region is generated by the outer peripheral electrode when the semiconductor device is turned off. A structure for suppressing a leakage current flowing from an end portion of a physical compound semiconductor layer to a source electrode is disclosed.

JP 2006-5005 A JP 2009-60049 A

  However, in the semiconductor device of Patent Document 2, it is considered that the leakage current is reduced by depletion at the outer peripheral electrode, but the drain electrode is connected to the end of the nitride semiconductor layer via the substrate or the buffer layer. When the route to reach has a low impedance, the potential of the side wall portion of the nitride semiconductor layer increases to a value close to the drain electrode, and a high electric field is generated at the side wall portion of the nitride semiconductor layer. As a result, there is a problem that the leakage current cannot be sufficiently suppressed.

  The present invention provides a semiconductor device capable of sufficiently suppressing leakage current in view of the above-described state of the prior art.

In order to solve the above problems, a semiconductor device according to the present invention provides:
A substrate made of silicon, silicon carbide, or gallium nitride semiconductor;
A nitride-based compound semiconductor layer formed on the substrate and serving as a main current path;
A first main electrode and a second main electrode that are disposed on the nitride-based compound semiconductor layer and cause a current to flow through the main current path;
A base portion of an outer peripheral electrode disposed on the nitride-based compound semiconductor layer so as to surround the first and second main electrodes;
An extended portion of the outer peripheral electrode provided on the nitride-based compound semiconductor layer via an insulating layer and extended outward from the outer peripheral electrode in plan view;
A mesa structure outer peripheral isolation structure or trench provided by dry-etching the nitride compound semiconductor layer outside the extending portion of the outer peripheral electrode when the nitride compound semiconductor layer is viewed in a plan view And having a structure
The nitride-based compound semiconductor layer has a thickness smaller than a distance between the first main electrode and the second main electrode,
The outer peripheral electrode extends from the base of the outer peripheral electrode to the second electrode side, and on the second main electrode side of the outer peripheral electrode provided on the nitride compound semiconductor layer via an insulating layer It further has a stretched part to be stretched,
The extending portion extending toward the second main electrode is shorter than the extending portion of the outer peripheral electrode extending outward.

According to the semiconductor device of the present invention, the first extended portion of the outer peripheral electrode extending from the base portion of the first outer peripheral electrode toward the outer peripheral separation groove side is formed on the insulating layer, so that the nitride system The concentration of the electric field from the base portion of the first outer peripheral electrode of the compound semiconductor layer toward the outer peripheral separation groove can be reduced, and the leakage current flowing between the first outer peripheral electrode and the outer peripheral separation groove can be suppressed.

1 is a schematic cross-sectional structure diagram of a semiconductor device according to a first embodiment of the present invention. 1 is a plan view showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 6 is a schematic cross-sectional structure diagram of a semiconductor device according to a second embodiment of the present invention.

  Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings. The following first and second embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is the material of the component parts. The shape, structure, arrangement, etc. are not specified as follows. The technical idea of the present invention can be modified in various ways within the scope of the claims.

FIG. 1 shows a semiconductor device 30 for explaining a first embodiment according to the present invention.
A semiconductor device 30 shown in FIG. 1 includes a substrate 1, a buffer layer 2 formed on the substrate 1, an electron transit layer (channel layer) 3 made of a gallium nitride semiconductor such as GaN, and a gallium nitride such as AlGaN. An electron supply layer (barrier layer) 4 made of a semiconductor, a two-dimensional electron gas layer 20 formed in the vicinity of the interface between the electron supply layer 4 and the electron transit layer 3, and a trench isolation for defining the outer periphery of the semiconductor device The outer peripheral separation structure 13 and the outer peripheral electrode 8 are provided inside the outer peripheral separation structure 13 when the semiconductor device 30 is viewed in plan.

The first main electrode 12 electrically connected to the two-dimensional electron gas layer 20 and the two-dimensional electron gas layer 20 are electrically connected to the inside of the outer peripheral electrode 8 when the semiconductor device 30 is viewed in plan view. And a main current flowing between the first main electrode 9 and the second main electrode 12 of the semiconductor device, and the second main electrode 9 disposed so as to surround the first main electrode 12 from the outside. For this purpose, a control electrode 10 is provided between the first main electrode 12 and the second main electrode 9.

Hereinafter, the case where the first main electrode 12 is a drain electrode, the second main electrode 9 is a source electrode, and the control electrode 10 is a gate electrode will be described as an example. The first main electrode 12 is a source electrode, The main electrode 9 may be a drain electrode, and the control electrode 10 may be a gate electrode.

Hereinafter, the configuration of the semiconductor device 30 illustrated in FIG. 1 will be described. The substrate 1 is made of a gallium nitride semiconductor such as silicon, silicon carbide (SiC), or GaN. For example, a silicon substrate to which a p-type impurity is added is used.

The buffer layer 2 can employ a structure in which a plurality of nitride compound semiconductors having different lattice constants and thermal expansion coefficients are stacked. For example, as the buffer layer 2, a multi-layer buffer layer in which AlGaN layers having different composition ratios are stacked as one set, or a multi-layer buffer layer in which an AlN layer and a GaN layer are stacked as a set is used. To do. In addition, a nitride compound semiconductor layer thicker than the first and second multilayer films is disposed between the first multilayer film and the second multilayer film in which the AlN layer and the GaN layer are alternately stacked several times. It is also possible to adopt the intermittent buffer structure.

The electron transit layer 3 on the buffer layer 2 is made of a nitride compound semiconductor such as non-doped AlXGa1-XN (0 ≦ X ≦ 1), and the electron supply layer 4 is an n-type or non-doped AlYGa1-YN (X <Y It is composed of a nitride-based compound semiconductor having a composition different from that of the electron transit layer 3 such as ≦ 1), having a band gap larger than that of the electron transit layer 3 and having a lattice constant different from that of the electron transit layer 3. Note that a two-dimensional electron gas (2DEG) layer 20 is generated near the interface between the electron transit layer 10 and the electron supply layer 11. In FIG. 1, a cap layer 5 made of n-type AlzGa1-zN (0 ≦ z ≦ 1, z is different from Y) or the like is disposed on the electron supply layer 4. The film thickness of the carrier supply layer 4 is thinner than the carrier traveling layer 3, for example, about 5 to 50 nm, and more preferably about 5 to 30 nm. The cap layer 5 is about several nm.

  A spacer layer made of undoped AlN may be arranged between the electron supply layer 4 and the electron transit layer 3 made of GaN. Although not shown in FIG. 1, a contact layer made of n-type AlGaN, for example, may be disposed between the source electrode 9, the drain electrode 12, and the electron supply layer 4. The spacer layer has the effect of reducing the Coulomb interaction acting between the two-dimensional electron gas layer 20 and the positive charge caused by the ionized donors left in the electron supply layer 4, and the impurities in the electron supply layer 4 are added to the electron transit layer 3. It has the effect of preventing diffusion. The contact layer contributes to a reduction in contact resistance between the source electrode 9, the drain electrode 12, and the electron supply layer 4. In FIG. 1, the source electrode 9 and the drain electrode 12 are formed with engraved grooves reaching the electron transit layer 3 through the cap layer 5 and the electron supply layer 4 so as to contact the two-dimensional electron gas layer 20. A source electrode 9 and a drain electrode 12 are embedded in the engraved groove.

  The semiconductor device 30 further includes a control electrode (gate electrode) 10 that is disposed on the electron supply layer 4 between the source electrode 9 and the drain electrode 12 and is made of a material such as Ni / Au. The base 10 </ b> A of the control electrode 10 controls the main current that flows between the source electrode 9 and the drain electrode 12 through the electron transit layer 3. Between the base portion 10A of the control electrode 10 and the electron supply layer 4, a p-type material film such as p-type AlPGa1-PN (0 ≦ P <1), a p-type metal oxide, or an insulating film such as Al2O3 is used. Although the base film 11 is provided, the base film 11 may not be provided. For example, when the semiconductor device 30 is a normally-off type semiconductor device, the electron supply layer 4 below the base portion 10A of the control electrode 10 has a concave portion formed by a bottom sandwiched between an inclined side surface and an inclined side surface. In addition, the thickness of the electron supply layer 4 corresponding to the bottom of the recess is thin. Accordingly, by combining with the base film 11 under the base 10A of the control electrode 10, the two-dimensional electron gas layer 20 under the base 10A of the control electrode 10 is blocked, and the semiconductor device 30 can realize normally-off. At this time, the side surface of the cap layer 5 also has an inclined side surface, and the control electrode 10 and the base film 11 may be provided thereon.

An insulating film 6 is disposed on the cap layer 5. As shown in FIG. 1, the extending portion 10B of the control electrode 10 is also extended on the insulating film 6 so as to have a step from the base portion 10A of the control electrode 10. Make up plate. In the gate field plate, not only the drain electrode 12 side of the control electrode 10 but also the source electrode 9 side, the extending portion 10 </ b> B may be extended on the insulating film 6. Since the drain-gate voltage is larger than the source-gate voltage, the extended portion 10B on the drain electrode 12 side is more gradual than the extended portion 10B on the source electrode 9 side in the gate field plate. In addition, it is desirable that the extended portion 10B on the drain electrode 12 side extends longer than the extended portion 10B on the source electrode 9 side. Therefore, it is desirable that the extending portion 10 </ b> B of the control electrode 10 on the drain electrode 12 side extends stepwise from the upper surface of the cap layer 5 to the inclined surface of the insulating film 6 and the upper surface of the insulating film 6.

As shown in FIG. 1, the semiconductor device 30 includes an outer peripheral electrode 7 made of the same material such as Ni / Au as the control electrode 10 between the source electrode 9 on the electron supply layer 4 and the outer peripheral isolation structure 13. Is further provided. In order to suppress the leakage current satisfactorily, a p-type material film such as p-type AlPGa1-PN (0 ≦ P <1) or p-type metal oxide is provided between the base portion 7A of the outer peripheral electrode 7 and the electron supply layer 4; Alternatively, the base film 8 made of an insulating film such as Al 2 O 3 is provided, but the base film 8 may not be provided.
The outer peripheral electrode 7 may be applied with the same potential as the source electrode 9 or a lower potential (for example, a negative potential) than the source electrode 9 in order to suppress the leakage current. Further, the extending portion 7B of the outer peripheral electrode 7 extends from the base portion 7A of the outer peripheral electrode 7 to the insulating film 6 on the outer peripheral separation structure 13 side, and the electric field in the vicinity of the outer peripheral electrode 7 is relaxed. The extending portion 7B of the outer peripheral electrode 7 may be arranged to extend on the insulating film 6 not only on the outer peripheral separation structure 13 side of the outer peripheral electrode 7 but also on the source electrode 9 side. Since the peripheral isolation structure 13 and the source-to-source voltage are larger than the source-gate voltage, the extending part 7B on the outer peripheral isolation structure 13 side is more gradual than the extending part 7B on the source electrode 9 side, and the source electrode It is desirable that the extending portion 7B on the outer peripheral separation structure 13 side extends longer than the extending portion 7B on the 9 side. Therefore, the extending portion 7B of the outer peripheral electrode 7 on the outer peripheral separation structure 13 side extends step by step from the upper surface of the cap layer 5 to the inclined surface of the insulating film 6 and the upper surface of the insulating film 6. The extending portion 7B of the electrode 7 is desirably formed in a step shape. Further, at least one of the cross-sectional shape at the base portion 10A of the control electrode 10 and the base portion 7A of the outer peripheral electrode 7 and the cross-sectional shape at the extended portion 10B of the control electrode 10 and the extended portion 7B of the outer peripheral electrode 7 may be the same. Similarly to the control electrode 10, the electron supply layer 4 below the base portion 7 </ b> A of the outer peripheral electrode 7 has a concave portion formed by a bottom sandwiched between the inclined side surface and the inclined side surface. The thickness of the electron supply layer 4 corresponding to the bottom of the recess under the base 7A is thin. The leakage current can be suppressed satisfactorily. Incidentally, the concave portion under the base portion 7A of the outer peripheral electrode 7 penetrates the two-dimensional electron gas layer 20 in order to block the two-dimensional electron gas layer 20, and the bottom portion of the concave portion under the base portion 7A of the outer peripheral electrode 7 It may be below the two-dimensional electron gas layer 20 around the recess under the base 7A.

The outer periphery isolation structure 13 includes trench isolation for defining the outer periphery of the semiconductor device. The outer peripheral separation structure 13 is a groove etched to at least a position from the electron supply layer 4 so as to be deeper than a position where the two-dimensional electron gas layer 20 is formed. By forming the groove etched at least from the electron supply layer 4 to the position, the two-dimensional electron gas layer 20 is not formed in the region of the outer peripheral isolation structure 13, and the end of the semiconductor device and the inner side of the outer peripheral isolation structure 13 are formed. It can block well. Further, since the two-dimensional electron gas layer 20 is blocked, a plurality of element regions can be formed, and a semiconductor device composed of a plurality of nitride-based compound semiconductor elements can be obtained. However, the outer peripheral separation structure 13 may not be deeper than the position where the two-dimensional electron gas layer 20 is formed.
Further, when the semiconductor device is composed of a nitride compound semiconductor element having one characteristic, the outer peripheral separation structure 13 may not be provided. Since the outermost side wall of the nitride semiconductor layer is cut by dicing when forming the semiconductor device, crystal defects are likely to occur on the outermost side wall of the nitride semiconductor layer, which also causes a leak current. Therefore, it is preferable to provide the outer peripheral isolation structure 13 even when the semiconductor device is composed of a nitride compound semiconductor element having one characteristic.
Further, when the semiconductor device is composed of a nitride compound semiconductor element having a plurality of characteristics, the outer peripheral isolation structure 13 functions as an element isolation region.

As shown in FIG. 2, when the semiconductor device 30 is viewed in a plan view, the drain electrode 12 is branched from the drain pad electrode 120 into a comb shape. A source pad electrode 90 is provided on the side opposite to the drain pad electrode 120. The source electrode 9 extends from the source pad electrode 90 so as to extend between a portion formed so as to surround the drain pad electrode 120 and the drain electrode 12 with the source electrode pad 90 and a branched portion of the adjacent drain electrode 12. And a portion branched into a comb shape. Inside the source electrode 9, a control pad electrode 100 is provided on the same side as the drain pad electrode. The control electrode 10 is provided inside the source electrode 9 and extends from the control pad electrode 100 between the source electrode 9 and the drain electrode 12. Further, an outer peripheral electrode 7 is provided so as to surround the source electrode 9 and the source pad electrode 90. That is, the outer peripheral electrode 7 is provided outside the source pad electrode 90, the source electrode 9, the control electrode 10, the control pad electrode 100, the drain electrode 12, and the drain pad electrode 120. The outer peripheral separation structure 13 is further arranged outside the outer peripheral electrode 7 so as to surround it.

Next, effects of the semiconductor device 30 according to the first embodiment of the present invention will be described.
In the state in which the nitride compound semiconductor device is reverse-biased (that is, in the state in which the FET is off), the outer electrode 7 of the semiconductor device 30 has the same potential as that of the source electrode 9 or higher than that of the source electrode 9, as in Patent Document 2. Apply a low potential. The outer peripheral electrode 7 of the semiconductor device 30 has the two-dimensional electron gas layer 20 immediately below the outer peripheral electrode 7 depleted and blocked, so that the buffer layer 2, the substrate 1, the outer peripheral separation structure 13, and the two-dimensional electron gas are removed from the drain electrode 12. Leakage current flowing through the source electrode 9 via the layer 20 is suppressed. However, in the case of Patent Document 2, when a high voltage is applied and the path through which the leakage current flows is low impedance, the outer peripheral isolation structure 13 also has a high potential like the drain electrode 11, and not only the end of the drain electrode 11 but also the outer periphery. It has been discovered by the inventors that electric field concentration also occurs in the vicinity of the interface with the separation structure 13 and the leakage current of the semiconductor device 30 increases.

  Therefore, in the nitride-based compound semiconductor device of the present invention shown in FIGS. 1 and 2, the extending portion 7B of the outer peripheral electrode 7 functioning as a field plate is formed on the insulating layer on the outer peripheral separation structure 13 side, and the outer peripheral electrode Thus, the depletion layer extending in the direction of the outer peripheral separation structure 13 from just below 7 can be moderated to suppress electric field concentration near the outer peripheral electrode 7. Further, in the outer peripheral electrode 7 of the semiconductor device 30 shown in FIGS. 1 and 2, the extending portion 7 </ b> B on the outer peripheral isolation structure 13 side is gentler and longer than the source electrode 7 side. By forming the extending portion 7B of the outer peripheral electrode 7 in this way, the leakage current can be suppressed more favorably without increasing the chip size of the semiconductor device 30 as much as possible.

  Further, in the semiconductor device 30 shown in FIGS. 1 and 2, an increase in on-resistance due to a so-called current collapse phenomenon can be suppressed. The current collapse phenomenon is a phenomenon in which the on-resistance increases after reverse bias application (off) between the control electrode 10 and the drain electrode 12. This increase in on-resistance is said to occur when electrons trapped in defects inside the nitride semiconductor layer during reverse bias (off) reduce the charge stored in the two-dimensional electron gas layer 20 and the nitride semiconductor layer. Yes. In the semiconductor device 30 shown in FIGS. 1 and 2, the electrons trapped in the defects inside the nitride semiconductor layer are relatively low resistance due to damage in the on state. Since the electric field concentration in the vicinity of the outer peripheral separation structure 13 that is the end face can be relaxed, an increase in on-resistance after reverse bias application (off) can also be suppressed.

Similarly to the control electrode 11, the upper surface of the electron supply layer 4 below the base portion 7 </ b> A of the outer peripheral electrode 7 is formed with a recess composed of a bottom portion sandwiched between the inclined side surface and the inclined side surface. By reducing the thickness of the electron supply layer 4 corresponding to the bottom of the concave portion below the base portion 7A, the leakage current can be satisfactorily suppressed.
Further, since the voltage between the outer peripheral isolation structure 13 and the source is larger than the source-gate voltage, the extension part 7B on the outer peripheral isolation structure 13 side is more gradual than the extension part 7B on the source electrode 9 side, and the source electrode The extending portion 7B on the outer peripheral separation structure 13 side extends longer than the extending portion 7B on the 9 side. As a result, the chip size can be reduced as much as possible, and the leakage current can be suppressed satisfactorily.

(Second Embodiment)
FIG. 3 shows a nitride-based compound semiconductor device according to the second embodiment of the present invention. In the semiconductor device shown in FIG. 3, the distance between the outer peripheral isolation structure 13 and the source electrode 9 is longer than the distance between the source electrode 9 and the drain electrode 12. This is different from the first embodiment. Other configurations are the same as those of the nitride-based compound semiconductor device according to the first embodiment of the present invention shown in FIGS.

    Since the outer peripheral isolation structure 13 is formed using dry etching, in the conventional structure, a crystal defect or the like is likely to occur in the nitride-based compound semiconductor layer near the outer peripheral isolation structure 13. Since the vicinity of the outer peripheral isolation structure 13 where the crystal defect has occurred becomes a low resistance region compared to other portions of the nitride semiconductor layer, for example, the leakage current path from the drain electrode 12 to the outer peripheral isolation structure 13 has a low impedance. In this case, when a predetermined potential is applied to the drain electrode 12, the potential of the outer peripheral separation structure 13 is raised to a high potential similar to that of the drain electrode 12. Therefore, by setting the distance between the outer peripheral isolation structure 13 and the source electrode 9 to be longer than the distance between the source electrode 9 and the drain electrode 12, for example, a leakage current path from the drain electrode 12 to the outer peripheral isolation structure 13 Even in the case of a low impedance, the breakdown voltage between the outer peripheral separation structure 13 and the source electrode 9 can be secured satisfactorily, and the leakage current can be further suppressed.

Similarly, it is desirable that the distance between the outer peripheral separation structure 13 and the base portion 7A of the outer peripheral electrode 7 is longer than the distance between the base portion 10A of the control electrode and the drain electrode 12.

  As described above, the present invention has been described according to the first to second embodiments. However, it should not be understood that the description and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, the carrier running layer 3 and the carrier supply layer 4 include GaN, InGaN other than AlGaN, AlInGaN, AlN, AlP, GaP, AlInP, GaInP, AlGaP, AlGaAs, GaAs, AlAs, InAs, InP, InN, and GaAsP. III-V compound semiconductors, II-VI compound semiconductors such as zinc oxide (ZnO), or other compound semiconductors can be employed.

  The carrier supply layer 4 can be replaced with a hole supply layer made of a p-type semiconductor. In this case, a two-dimensional hole gas layer 20 ′ is generated as a two-dimensional carrier gas layer in a region corresponding to the two-dimensional electron gas layer 20.

Furthermore, the present invention can also be applied when the substrate 1 is a conductive substrate other than a silicon substrate, or when a low-insulating layer is present under the gallium nitride compound semiconductor. Further, a back electrode may be provided on the lower surface of the substrate 1.
Further, a groove 13 a shallower than the outer periphery separation structure 13 that does not reach the two-dimensional electron gas layer 20 may be separately formed between the outer periphery separation structure 13 and the outer periphery electrode 7. By forming the groove 13a, the concentration of the two-dimensional electron gas layer 20 immediately below the groove 13a is reduced, so that the leakage current between the outer peripheral separation structure 13 and the outer peripheral electrode 7 can be suppressed.

  In the first and second embodiments, the HEMT has been described as an example. However, the present invention can also be applied to a Schottky barrier diode (SBD).

  In addition, although the outer peripheral isolation structure 13 of the first to second embodiments has been described as a trench structure, the present invention can also be applied to a mesa structure.

  In the first and second embodiments, the outer peripheral electrode 7 and the control electrode 10, the base layer 8 immediately below the outer peripheral electrode 7, and the base layer 11 immediately below the control electrode 10 have been described as being formed of the same material. , At least one of them may be formed of a different material. Further, at least one of the base layers 8 and 11 may be deleted.

In addition, one semiconductor device 30 may include one outer peripheral isolation structure 13 and one outer peripheral electrode 7, but when the semiconductor device 30 includes a plurality of element structures, the outer peripheral isolation structure 13 and the outer peripheral electrode 7 are respectively provided. It may be provided so as to surround the element.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

DESCRIPTION OF SYMBOLS 1 ... Board | substrate 2 ... Buffer layer 3 ... Electron travel layer 4 ... Electron supply layer 5 ... Cap layer 6 ... Insulating layer 7 ... Outer electrode 8 ... Underlayer (of outer electrode) 9 ... Source electrode 10 ... Control electrode 11 ... (Control) Electrode base layer 12 ... Drain electrode 13 ... Peripheral separation structure 20 ... Two-dimensional electron gas layer

Claims (6)

A substrate made of silicon, silicon carbide, or gallium nitride semiconductor;
A nitride-based compound semiconductor layer formed on the substrate and serving as a main current path;
A first main electrode and a second main electrode that are disposed on the nitride-based compound semiconductor layer and cause a current to flow through the main current path;
A base portion of an outer peripheral electrode disposed on the nitride-based compound semiconductor layer so as to surround the first and second main electrodes;
An extended portion of the outer peripheral electrode provided on the nitride-based compound semiconductor layer via an insulating layer and extended outward from the outer peripheral electrode in plan view;
A mesa structure outer peripheral isolation structure or trench provided by dry-etching the nitride compound semiconductor layer outside the extending portion of the outer peripheral electrode when the nitride compound semiconductor layer is viewed in a plan view And having a structure
The nitride-based compound semiconductor layer has a thickness smaller than a distance between the first main electrode and the second main electrode,
The outer peripheral electrode extends from the base of the outer peripheral electrode to the second electrode side, and on the second main electrode side of the outer peripheral electrode provided on the nitride compound semiconductor layer via an insulating layer It further has a stretched part to be stretched,
2. A semiconductor device according to claim 1, wherein an extending portion extending toward the second main electrode is shorter than an extending portion of the outer peripheral electrode extending outward. The distance between the first main electrode and the second main electrode is equal to or less than the distance between the second main electrode and the outer peripheral isolation structure of the mesa structure or the trench structure . The semiconductor device according to claim 1 , wherein the main electrode has a higher potential than the second main electrode. A control electrode disposed on the nitride-based compound semiconductor layer between the first main electrode and the second main electrode;
The distance between the first main electrode and the control electrode, a semiconductor according to claim 1, wherein the outer circumference electrode and the or less distance between the outer isolation structure or the trench structure of the mesa structure apparatus. The nitride-based compound semiconductor layer includes a first nitride-based compound semiconductor layer,
A second nitride-based compound semiconductor layer formed on the first nitride-based compound semiconductor layer and having a composition different from that of the first nitride-based compound semiconductor layer;
A two-dimensional electron gas layer in the vicinity of the interface between the first nitride-based compound semiconductor layer and the second nitride-based compound semiconductor layer;
Periphery isolation structure or the trench structure of the mesa structure, a semiconductor device which satisfies the claims 2 or 3, characterized in that deeper than the two-dimensional electron gas layer. The first main electrode is an electrode to which a higher potential is applied than the second main electrode,
The peripheral electrode is a semiconductor device that satisfies the claims 1-4 any one, wherein a potential of less than or equal to the second main electrode and the same potential is applied. A recess is formed in the upper surface region of the nitride-based compound semiconductor layer under the outer peripheral electrode,
The semiconductor device satisfying any one of claims 1 to 5 , wherein a base portion of the outer peripheral electrode is disposed at a bottom portion of the concave portion.

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