JP2008016588A - GaN-BASED SEMICONDUCTOR ELEMENT - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a GaN-based semiconductor element having a low leakage current. <P>SOLUTION: In a horizontal power HFET 21, an AlInGaN layer 1 made of Al<SB>x</SB>In<SB>y</SB>Ga<SB>1-x-y</SB>N (0<x<1, 0<y<1, x+y<1), a GaN layer 2 made of an undoped GaN, and an AlGaN layer 3 made of undoped or n-type of Al<SB>z</SB>Ga<SB>1-z</SB>N (0<z<1), are laminated in this order. A source electrode 4, a drain electrode 5, and a gate electrode 6 are provided on the AlGaN layer 3. The AlInGaN layer 1 is formed to satisfy a relation, 0.4x≤y≤0.53x. The band gap of the AlInGaN layer 1 is larger than that of the GaN layer 2. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a GaN-based semiconductor device, and more particularly to a GaN-based semiconductor device for power control.

  Conventionally, research on power devices using wide band gap semiconductors has been actively conducted. Since GaN (gallium nitride) has a larger band gap than Si (silicon), a semiconductor device using GaN has a higher critical electric field than a semiconductor device using Si. For this reason, a GaN-based semiconductor element is easier to miniaturize and have a higher breakdown voltage than a Si-based semiconductor element, and when a power control semiconductor element is configured, a semiconductor element with low on-resistance and low loss is realized. be able to. Among GaN-based semiconductor elements, a field effect transistor (HFET) using an AlGaN / GaN heterostructure can obtain good characteristics with a simple element structure (see, for example, Patent Document 1). .)

  However, a semiconductor element using a nitride semiconductor such as GaN can realize a low on-resistance and a high breakdown voltage, but is not designed in consideration of a leakage current at the time of off. When the leakage current at the off time is large, the loss in the standby state increases. In addition, the element may be destroyed by self-heating due to leakage current.

JP 2002-057158 A

  An object of the present invention is to provide a GaN-based semiconductor device having a low leakage current.

According to one embodiment of the present invention, when the Al composition ratio is x (0 <x <1) and the In composition ratio is y (0 <y <1, x + y <1), Al _x In _y The composition ratio of Al is z (0 <z <1), the first semiconductor layer made of Ga _1-xy N, the second semiconductor layer made of undoped GaN formed on the first semiconductor layer, and Al. ), A third semiconductor layer formed on the second semiconductor layer and made of undoped or n-type Al _z Ga ₁ -zN, and a control formed on the third semiconductor layer. An electrode, a first main electrode connected to the third semiconductor layer, and a second main electrode connected to the third semiconductor layer, wherein the band gap of the first semiconductor layer is There is provided a GaN-based semiconductor element characterized by being larger than the band gap of the second semiconductor layer.

  According to the present invention, a GaN-based semiconductor element having a low leakage current can be realized.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same part in each drawing.

(First embodiment)
FIG. 1 is a cross-sectional view schematically illustrating a GaN-based semiconductor element according to the first embodiment of the invention. FIG. 1 also schematically illustrates the potential distribution in the thickness direction of the element.
The GaN-based semiconductor device according to this embodiment is a lateral power HFET.

As shown in FIG. 1, in the HFET 21 according to the present embodiment, an AlInGaN layer 1 made of Al _x In _y Ga _1-xy N is provided as a barrier layer. Note that x represents the composition ratio of Al (aluminum), y represents the composition ratio of In (indium), and 0 <x <1, 0 <y <1, and x + y <1. For example, the relationship 0.4x ≦ y ≦ 0.53x is satisfied.

A GaN layer 2 made of undoped GaN is provided as a channel layer on the AlInGaN layer 1, and an undoped Al _z Ga _1-z N or n as a barrier layer is provided on the GaN layer 2. An AlGaN layer 3 made of Al _z Ga _1-z N of the type is provided. Z represents the composition ratio of Al, and 0 <z <1.

  Further, a source electrode (first electrode) 4 and a drain electrode (second electrode) 5 are provided on the AlGaN layer 3 so as to be separated from each other, and between the source electrode 4 and the drain electrode 5. Are provided with a gate electrode (control electrode) 6 for forming a Schottky junction. The source electrode 4 and the drain electrode 5 are connected to the AlGaN layer 3.

Hereinafter, the operation of the lateral power HFET 21 according to the present embodiment will be described in comparison with the operation of a conventional element.
A conventional GaN-based HFET has a structure in which an AlGaN layer 3 as a barrier layer is formed on a GaN layer 2 as a channel layer, and the AlInGaN layer 1 is not provided. In such an element, in the ON state, a two-dimensional electron gas (2DEG) is generated in the vicinity of the heterointerface between the GaN layer 2 and the AlGaN layer 3, and the region immediately below the gate electrode 6 (channel region) using the 2DEG as a carrier. ), A current flows between the source electrode 4 and the drain electrode 5. In the off state, a voltage equal to or lower than the threshold voltage is applied to the gate electrode 6, whereby the channel region at the heterointerface is depleted and conduction by 2DEG is cut off. Thereby, the current between the source and the drain is interrupted.

  However, in this conventional GaN-based HEET, when a high voltage is applied to the drain electrode 5 in the off state, the potential barrier due to the depletion layer extending from the gate electrode 6 is pushed down by the drain voltage. As a result, a channel leakage current flows. In addition, since the electric field in the GaN layer 2 increases, a buffer leak current flows through the region immediately below the depletion layer so as to bypass the depletion layer in the GaN layer 2.

  In order to reduce the above-described channel leakage current, it is necessary to make it difficult to push down the potential barrier. For this purpose, the channel length must be increased or the gate voltage must be significantly reduced below the threshold voltage. Don't be. Increasing the channel length increases the on-resistance. When the gate voltage is significantly reduced, the electric field applied to the gate end portion increases and the withstand voltage decreases. Further, in order to reduce the above-described buffer leakage current, the resistance value of the GaN layer 2 must be increased, and impurities taken in during crystal growth must be reduced. As described above, when the leakage current is reduced in the conventional GaN-based HEET, the characteristics of the element are deteriorated, or strict doping control is required at the time of crystal growth.

  On the other hand, in the HFET 21 according to the present embodiment, by providing the AlInGaN layer 1, the channel layer GaN layer 2 is sandwiched between the AlInGaN layer 1 and the AlGaN layer 3 having a wider band gap than the GaN layer 2. It is out. Thereby, carriers can be confined in the GaN layer 2. As a result, like the semiconductor device having an SOI (Silicon On Insulator) structure, the potential barrier is difficult to be pushed down, and the AlInGaN layer 1 becomes a barrier and the buffer leak current hardly flows.

  Further, at the interface between the AlInGaN layer 1 and the GaN layer 2, there is a case where distortion occurs in the crystal lattice due to a difference in lattice constant, and polarization occurs due to this distortion, thereby generating a charge. When electric charges are generated at the interface, electric field concentration may easily occur when a high voltage is applied. Therefore, polarization may not occur at the interface between the AlInGaN layer 1 and the GaN layer 2 (AlInGaN / GaN interface). desirable. The polarization of the interface can be controlled by adjusting the Al composition ratio x and the In composition ratio y of the AlInGaN layer 1.

FIG. 2 is a diagram illustrating the theoretical value of the interface charge due to the polarization of the AlInGaN / GaN interface, with the In composition ratio y on the horizontal axis and the channel carrier concentration on the vertical axis.
In FIG. 2, when the channel carrier concentration represented by the vertical axis is positive, two-dimensional hole gas (2DHG) is generated at the interface, and when it is negative, 2DEG is generated. Since the AlInGaN / GaN interface is separated from the gate electrode 6, it is difficult to control the carriers generated at this interface by the gate electrode 6. Therefore, the channel carrier concentration at this interface is most preferably zero. However, in practice, it is difficult to control the channel carrier concentration so that it is always strictly zero. Therefore, considering the practically allowable range, it is preferable that the carrier generated at the AlInGaN / GaN interface is 2DHG rather than 2DEG. The reason is that since holes cannot pass through the AlGaN layer 3, no current flows between the source and drain. 2, in order to suppress the generation of 2DEG, the relationship between the Al composition ratio x and the In composition ratio y in Al _x In _y Ga _1-xy N forming the AlInGaN layer 1 is y ≧ 0. 4x is sufficient.

On the other hand, if the concentration of 2DHG at the AlInGaN / GaN interface becomes too high, the characteristics of the HFET 21 may deteriorate. Therefore, it is desirable that the 2DHG concentration at the AlInGaN / GaN interface be 1/10 or less of the 2DEG concentration at the interface between the AlGaN layer 3 and the GaN layer 2 used for on-state conduction. Usually, since the sheet concentration of 2DEG at the interface between the AlGaN layer 3 and the GaN layer 2 is about 1 × 10 ¹³ cm ⁻² , the sheet concentration of 2DHG at the interface between the AlInGaN layer 1 and the GaN layer 2 is 2DEG sheet. It is desirable that the concentration be 1 × 10 ¹² cm ⁻² or less, which is 1/10 or less of the concentration. From FIG. 2, when the relationship between the Al composition ratio x and the In composition ratio y at which the sheet density of 2DHG is 1 × 10 ¹² cm ⁻² or less is obtained, y ≦ 0.53x. Therefore, in Al _x In _y Ga _1-xy N forming the AlInGaN layer 1, it is preferable that 0.4x ≦ y ≦ 0.53x.

As described above, according to the present embodiment, by forming the HFET 21 using GaN, a power semiconductor device having a low on-resistance and a high breakdown voltage can be realized. By providing the AlInGaN layer 1 as a barrier layer below the GaN layer 2 that is the channel layer, carriers can be confined in the GaN layer 2 and the leakage current between the source and drain in the off state can be suppressed. . In addition, by properly defining the relationship between the Al composition ratio x and the In composition ratio y in Al _x In _y Ga _1-xy N forming the AlInGaN layer 1, the interface between the AlInGaN layer 1 and the GaN layer 2 is established. Thus, the carrier concentration at this interface can be regulated within a practically acceptable range. Thereby, the characteristics of the HFET 21 can be reliably improved. Thus, according to the present embodiment, it is possible to obtain a power GaN-based semiconductor element having a low on-resistance, a high breakdown voltage, and a low off-leakage current.

(Second Embodiment)
FIG. 3 is a cross-sectional view schematically illustrating a GaN-based semiconductor element according to the second embodiment of the invention. FIG. 3 also schematically illustrates the potential distribution in the thickness direction of the element. In FIG. 3, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 3, in the HFET 22 according to the present embodiment, 2DHG is generated due to polarization at the interface between the AlInGaN layer 1 and the GaN layer 2. On the other hand, 2DEG is generated at the interface between the GaN layer 2 and the AlGaN layer 3 due to polarization. The sheet concentration of 2DHG generated at the interface between the AlInGaN layer 1 and the GaN layer 2 is substantially equal to the sheet concentration of 2DEG generated at the interface between the GaN layer 2 and the AlGaN layer 3, for example, 1 × 10 ¹³ cm ^−2. Degree.

  When 2DEG and 2DHG are generated in the GaN layer 2 due to the polarization, charges of opposite polarity corresponding to the 2DEG and 2DHG are generated in the AlGaN layer 3 and the AlInGaN layer 1 due to the polarization. That is, when 2DHG is generated in the vicinity of the interface of the GaN layer 2 with the AlInGaN layer 1, a negative charge is generated in the vicinity of the interface of the AlInGaN layer 1, while the vicinity of the interface of the GaN layer 2 with the AlGaN layer 3 is generated. When 2DEG is generated, positive charge is generated in the vicinity of this interface in the AlGaN layer 3. Then, by applying a high voltage to the GaN layer 2, even if 2DEG and 2DHG in the GaN layer 2 disappear, the charges of the AlGaN layer 3 and the AlInGaN layer 1 due to polarization remain. However, since these charges have opposite polarities, the electric fields caused by these charges cancel each other. Thereby, the electric field in the GaN layer 2 is reduced, and a high breakdown voltage can be realized.

It is possible to generate 2DHG at the interface with the GaN layer 2 by adjusting the Al composition ratio x and the In composition ratio y of the AlInGaN layer 1. In order to generate 2DHG at a concentration similar to 2DEG, that is, a concentration of about 1 × 10 ¹³ cm ⁻² , in the vicinity of the interface between the GaN layer 2 and the AlInGaN layer 1, y = 0.5x + 0 from FIG. .1 is sufficient. Since the 2DHG concentration is preferably lower than the 2DEG concentration, it is preferably y ≦ 0.5x + 0.1.

In order to realize such an operation, it is necessary to confine carriers in the GaN layer 2. For this purpose, the band gap of the AlInGaN layer 1 must be wider than the band gap of the GaN layer 2.
FIG. 4 shows the results of theoretically determining the influence of the composition of the AlInGaN layer on the carrier concentration and the band gap by taking the Al composition ratio x of the AlInGaN layer on the horizontal axis and the In composition ratio y on the vertical axis. FIG.
As shown in FIG. 4, when the relationship between the Al composition ratio x and the In composition ratio y where the height ΔEc of the discontinuous portions of the conduction bands of the AlInGaN layer 1 and the GaN layer 2 is zero is theoretically obtained, y = 3 .33x ³ -4.29x ² + 0.77x. Therefore, in order to make the discontinuous height ΔEc at the AlInGaN / GaN interface larger than 0, y <3.33x ³ −4.29x ² + 0.77x may be set.

In order to confine 2DEG more strongly in the GaN layer 2, the discontinuous height ΔEc at the interface between the AlInGaN layer 1 and the GaN layer 2 is larger than the discontinuous height at the interface between the GaN layer 2 and the AlGaN layer 3. It is effective to do. Usually, the Al composition ratio z of Al _z Ga _1-z N forming the AlGaN layer 3 is about 15 to 30%. At this time, the discontinuous height at the interface between the GaN layer 2 and the AlGaN layer 3 is 0 About 2 to 0.4 eV. Therefore, the discontinuous height ΔEc at the interface between the AlInGaN layer 1 and the GaN layer 2 is preferably ΔEc> 0.2 eV. When the relationship between the Al composition ratio x and the In composition ratio y of the AlInGaN layer where ΔEc = 0.2 eV is theoretically obtained, y = 1040 × ^{6.3 as} shown by the broken line in FIG. Therefore, in order to .DELTA.Ec> 0.2 eV may if ^y <1040x ^6.3. For example, when the carrier concentration at the AlInGaN / GaN interface is 0, ΔEc> 0.2 eV can be achieved by making the Al composition ratio x larger than 0.23.

Therefore, as described in the first embodiment, no polarization charge is generated at the interface between the AlInGaN layer 1 and the GaN layer 2, or, as described in the present embodiment, the AlInGaN layer 1 and the GaN layer. In order to generate 2DHG of the same degree as 2DEG at the interface between the GaN layer 2 and the AlGaN layer 3 at the interface with the GaN layer 2 and to make the band gap of the AlInGaN layer 1 wider than the band gap of the GaN layer 2, It is effective to set the relationship between the Al composition ratio x and the In composition ratio y in the AlInGaN layer 1 within a region indicated by hatching in FIG. That is, 0 <x <1, 0 <y <1, x + y <1, 0.4x ≦ y ≦ 0.5x + 1, and y <3.33x ³ −4.29x ² + 0.77x. preferably, it is more preferable that the ^y <1040x ^6.3.

FIG. 5 is a cross-sectional view schematically illustrating an HFET according to a first modification of the second embodiment.
As shown in FIG. 5, in the HFET according to this modification, a part of the source electrode 4 extends downward, reaches the GaN layer 2 through the AlGaN layer 3. Thereby, the source electrode 4 is connected to the GaN layer 2. In the HFET according to the first and second embodiments described above, when a high voltage is applied between the source and the drain of the 2DHG hole generated at the AlInGaN / GaN interface, the GaN layer 2 and the AlGaN layer 3 are used. It is discharged from the source electrode 4. In the present modification, holes can be quickly discharged because the source electrode 4 is connected to the GaN layer 2.

  The depth of the source electrode 4 is preferably deep enough to be in contact with 2DHG. However, when the source electrode 4 reaches the AlInGaN layer 1, the generation of leakage current is promoted, so that the source electrode 4 is shallow enough not to reach the AlInGaN layer 1. It is desirable. Further, when the drain electrode 5 is brought into contact with 2DHG together with the source electrode 4, a hole current flows between the source electrode 4 and the drain electrode 5. Therefore, it is not preferable to extend the drain electrode 5 to the GaN layer 2. .

FIG. 6 is a cross-sectional view schematically illustrating an HFET according to a second modification of the second embodiment.
As shown in FIG. 6, in the HFET according to this modification, a p ⁺ contact layer 12 is formed in the vicinity of the lower end of the source electrode 4 in the GaN layer 2 as compared with the first modification described above. Is different. The p ⁺ contact layer 12 is a region where p-type impurities are implanted at a higher concentration than the surroundings. Thereby, the resistance between the source electrode 4 and the GaN layer 2 can be reduced, and holes can be discharged more quickly.

(Third embodiment)
FIG. 7 is a cross-sectional view schematically illustrating a GaN-based semiconductor device according to the third embodiment of the invention. FIG. 7 also schematically illustrates the potential distribution in the thickness direction of the element. In FIG. 7, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 7, the HFET 23 according to the present embodiment has an InGaN layer 7 between the AlInGaN layer 1 and the GaN layer 2 as compared with the HFET 21 (see FIG. 1) according to the first embodiment described above. Is different. InGaN layer 7 _is formed by _{In u Ga 1-u N (} 0 <u <1).

  The InGaN layer 7 has a narrower band gap than the AlInGaN layer 1 and the GaN layer 2. Therefore, as shown in FIG. 7, a large potential step 13 can be formed on the conduction band side at the interface between the AlInGaN layer 1 and the InGaN layer 7, and a potential step 14 can also be formed on the valence band side. can do. As a result, 2DEG can be effectively confined by the potential step 13, and the potential ratio 14 is the same as that in which the Al composition ratio and the In composition ratio of the AlInGaN layer 1 are adjusted in the second embodiment described above. 2DEG can be generated. Note that the InGaN layer 7 may be formed by continuously changing the Al composition ratio and the In composition ratio of the AlInGaN layer 1. In this case, there is no clear interface between the AlInGaN layer 1 and the InGaN layer 7.

FIG. 8 is a cross-sectional view schematically illustrating an HFET according to a first modification of the third embodiment.
As shown in FIG. 8, in the HFET according to this modification, a part of the source electrode 4 extends downward, passes through the AlGaN layer 3 and the GaN layer 2, and reaches the InGaN layer 7. . Thereby, the source electrode 4 is connected to the InGaN layer 7. As a result, holes can be quickly discharged from the InGaN layer 7.

FIG. 9 is a cross-sectional view schematically illustrating an HFET according to a second modification of the third embodiment.
As shown in FIG. 9, the HFET according to the present modification has a p ⁺ contact in the vicinity of the lower end portion of the source electrode 4 in the InGaN layer 7 as compared with the first modification of the third embodiment described above. The difference is that the layer 12 is formed. Thereby, the resistance between the source electrode 4 and the InGaN layer 7 can be reduced, and holes can be discharged more quickly.

(Fourth embodiment)
FIG. 10 is a cross-sectional view schematically illustrating a GaN-based semiconductor element according to the fourth embodiment of the invention. FIG. 10 also schematically illustrates the potential distribution in the thickness direction of the element. 10, the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. Only different parts will be described here.

  As shown in FIG. 10, in the HFET 24 according to the present embodiment, the thickness of the AlInGaN layer 1 is as thin as about 100 nm, for example, and the GaN layer 8 is formed under the AlInGaN layer 1. That is, in the HFET 24, the GaN layer 8, the AlInGaN layer 1, the GaN layer 2, and the AlGaN layer 3 are laminated in order from the lower layer side. For this reason, the HFET 24 has a structure similar to a structure in which an AlInGaN layer is inserted into a GaN buffer layer in a conventional AlGaN / GaN HFET.

  In order to reduce the manufacturing cost of the HFET 24, it is preferable to reduce the thickness of the AlInGaN layer 1 that requires strict control of the composition ratio as much as possible. Since the AlInGaN layer 1 can confine carriers if it has a thickness of about 100 nm, the thickness of the AlInGaN layer 1 can be reduced to about 100 nm. However, on the other hand, in order to ensure high breakdown voltage, the entire HFET 24 requires a thickness of about several μm. Therefore, in the present embodiment, the GaN layer 8 having a lower deposition cost than the AlInGaN layer 1 is formed thick, and the thin AlInGaN layer 1 is formed thereon, thereby ensuring the carrier confinement effect and high breakdown voltage. However, the manufacturing cost of the HFET 24 can be reduced.

  Also in the present embodiment, by adjusting the Al composition ratio and the In composition ratio of the AlInGaN layer 1, carriers due to polarization charge are not generated at the interface between the AlInGaN layer 1 and the GaN layer 8, and control is performed by the gate electrode 6. The concentration of difficult carriers can be suppressed to a level that causes no problem in practice, and the leakage current can be suppressed.

FIG. 11 is a cross-sectional view schematically illustrating a first application example of the fourth embodiment.
As shown in FIG. 11, in this application example, the HFET 24 (see FIG. 10) according to the fourth embodiment is formed on the Si substrate 10 as a support substrate. Further, an AlN layer 9 is provided as a buffer layer between the Si substrate 10 and the GaN layer 8. As the Si substrate 10, for example, a silicon wafer diced can be used. Even in this way, the HFET 24 according to the fourth embodiment can be realized.

  Instead of the Si substrate 10, a SiC substrate or a sapphire substrate may be used. In this application example, the example in which the AlN layer 9 is provided as the buffer layer has been shown. However, the present embodiment is not limited to this, and other layers such as an AlGaN layer or a laminated film of an AlN layer and a GaN layer can be used. This kind of buffer layer may be provided.

  According to this application example, an inexpensive HFET can be efficiently manufactured by using a Si substrate as a support substrate. Further, if the thickness of the AlInGaN layer 1 is insufficient, carriers may flow into the GaN layer 8 beyond the AlInGaN layer 1 when a high voltage is applied. By using a conductive substrate, the electric field applied to the AlInGaN layer 1 can be suppressed.

FIG. 12 is a cross-sectional view schematically illustrating a second application example of the fourth embodiment.
As shown in FIG. 12, in this application example, the back electrode 11 is provided on the back surface of the Si substrate 10 of the HFET according to the first application example described above. The back electrode 11 is connected to the source electrode 4 outside the HFET. Thereby, the electric field applied to the AlInGaN layer 1 can be relaxed by the field plate effect of the Si substrate 10. Then, carriers that have jumped over the AlInGaN layer 1 and entered the GaN layer 8 side can be discharged to the outside through the Si substrate 10 and the back electrode 11.

  As described above, the features of the present invention have been described with reference to the first to fourth embodiments. However, the present invention is not limited to these embodiments, and other modifications that can be easily considered by those skilled in the art are available. All the features of the present invention are included in the scope of the present invention. For example, in the first to third embodiments, as in the fourth embodiment, as a support substrate used to form the GaN layer and the AlGaN layer, a sapphire substrate, a SiC substrate, a Si substrate, a GaN substrate, or the like is used. A substrate can be used. Further, the material of the support substrate is not limited to these materials.

  In each of the above-described embodiments, the example in which the AlGaN layer 3 made of undoped AlGaN is provided as the barrier layer has been described. However, an n-type AlGaN layer may be used. Furthermore, in each of the above-described embodiments, an example in which the GaN-based semiconductor element is an HFET has been shown, but the present invention is not limited to this. Since the structure between the gate and drain of the HFET described in each of the above embodiments is the same as that of a heterostructure Schottky barrier diode (HSBD), the GaN-based semiconductor element according to the present invention may be HSBD. Is possible. By using the structure of the present invention, it is possible to realize a HSBD having a low leakage and a high breakdown voltage.

  Furthermore, in each of the above-described embodiments, the example in which the composition of the AlInGaN layer 1 is uniform within the layer has been shown. However, the present invention is not limited to this, and the composition of the AlInGaN layer 1 varies within the layer. May be. Furthermore, in each of the above-described embodiments, an example in which the gate portion has a planar Schottky gate structure has been shown. However, a planar Schottky structure such as a recess gate structure, a MIS gate structure, a structure in which a GaN cap layer or a p layer is formed, etc. A gate structure other than the gate structure may be used. Furthermore, a field plate electrode may be formed in order to suppress electric field concentration at the end of the gate electrode or the end of the drain electrode.

It is sectional drawing which illustrates typically the GaN-type semiconductor element which concerns on the 1st Embodiment of this invention. It is a figure which illustrates the theoretical value of the interface charge by the polarization of an AlInGaN / GaN interface, taking In composition ratio y as a horizontal axis and taking a channel carrier concentration as a vertical axis. It is sectional drawing which illustrates typically the GaN-type semiconductor element which concerns on the 2nd Embodiment of this invention. FIG. 4 is a graph illustrating the results of theoretically determining the influence of the composition of the AlInGaN layer on the carrier concentration and the band gap by taking the Al composition ratio x of the AlInGaN layer on the horizontal axis and the In composition ratio y on the vertical axis. is there. It is sectional drawing which illustrates typically HFET which concerns on the 1st modification of 2nd Embodiment. It is sectional drawing which illustrates typically HFET which concerns on the 2nd modification of 2nd Embodiment. It is sectional drawing which illustrates typically the GaN-type semiconductor element which concerns on the 3rd Embodiment of this invention. It is sectional drawing which illustrates typically HFET which concerns on the 1st modification of 3rd Embodiment. It is sectional drawing which illustrates typically HFET which concerns on the 2nd modification of 3rd Embodiment. It is sectional drawing which illustrates typically the GaN-type semiconductor element which concerns on the 4th Embodiment of this invention. It is sectional drawing which illustrates typically the 1st application example of 4th Embodiment. It is sectional drawing which illustrates typically the 2nd application example of 4th Embodiment.

Explanation of symbols

1 AlInGaN layer (first semiconductor layer), 2 GaN layer (second semiconductor layer), 3 AlGaN layer (third semiconductor layer), 4 source electrode (first main electrode), 5 drain electrode (second Main electrode), 6 gate electrode (control electrode), 7 InGaN layer (fourth semiconductor layer), 8 GaN layer (fifth semiconductor layer), 9 AlN layer, 10 Si substrate, 11 back electrode, 12 p ⁺ Contact layer, 13, 14 Potential step, 21-24 HFET

Claims (5)

When the composition ratio of Al is x (0 <x <1) and the composition ratio of In is y (0 <y <1, x + y <1), it is composed of Al _x In _y Ga _1-xy N. A first semiconductor layer;
A second semiconductor layer formed on the first semiconductor layer and made of undoped GaN;
When the Al composition ratio is z (0 <z <1), a third semiconductor layer formed on the second semiconductor layer and made of undoped or n-type Al _z Ga _1-z N;
A control electrode formed on the third semiconductor layer;
A first main electrode connected to the third semiconductor layer;
A second main electrode connected to the third semiconductor layer;
With
A GaN-based semiconductor device, wherein a band gap of the first semiconductor layer is larger than a band gap of the second semiconductor layer.   2. The GaN-based semiconductor device according to claim 1, wherein the In composition ratio y in the first semiconductor layer is 0.4 times or more of the Al composition ratio x.   3. The GaN-based semiconductor device according to claim 2, wherein the In composition ratio y in the first semiconductor layer is 0.53 times or less of the Al composition ratio x. 3. The GaN-based semiconductor device according to claim 2, wherein the Al composition ratio x and the In composition ratio y in the first semiconductor layer satisfy the following mathematical formula.
y ≦ 0.5x + 0.1 5. The GaN-based semiconductor device according to claim 1, wherein an Al composition ratio x and an In composition ratio y in the first semiconductor layer satisfy the following mathematical formula.
y <33.33x ³ -4.29x ² + 0.77x

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