JP2020167275A - Semiconductor device, manufacturing method of semiconductor device and electronic device - Google Patents

Abstract

To realize a semiconductor device having excellent characteristics by using a nitride semiconductor.SOLUTION: A semiconductor device 10A includes a channel layer 11 using a nitride semiconductor, and a barrier layer 12 thereon. On the barrier layer 12, a gate electrode 15, a source electrode 16 and a drain electrode 17 are provided. In a region above the barrier layer 12 where the gate electrode 15 is provided, a cap structure 14 having a cap layer 14a using InGaN, and a cap layer 14b provided thereon and using GaN is provided. In the cap structure 14, the surface of InGaN is protected by GaN, and damage on InGaN, and generation of leakage current resulting therefrom are restrained. By piezo polarization generated in the InGaN on the barrier layer 12, damage on which is restrained, concentration of 2DEG13 of the channel layer 11 below the gate electrode 15 is lowered, and normally-off is achieved.SELECTED DRAWING: Figure 2

Description

The present invention relates to semiconductor devices, methods for manufacturing semiconductor devices, and electronic devices.

A semiconductor device using a nitride semiconductor as a semiconductor material is known. For example, a semiconductor device is known in which a barrier layer using aluminum gallium nitride (AlGaN) is provided on a channel layer using gallium nitride (GaN), and a two-dimensional electron gas is generated in the channel layer. Regarding such a semiconductor device, for example, a technique is known in which a passivation film of an insulator that applies a predetermined stress to the barrier layer is provided on the barrier layer. In addition, a technique of providing a cap layer such as p-type GaN on the barrier layer and a technique of providing an indium gallium nitride (InGaN) cap layer on the barrier layer are known.

Japanese Unexamined Patent Publication No. 2009-267155 Japanese Unexamined Patent Publication No. 2015-173151 JP-A-2009-32713

IEEE Electron Device Letters, July 2007, Vol. 28, No. 7, p. 549-551

In the above-mentioned semiconductor device using a nitride semiconductor, the concentration of the two-dimensional electron gas generated in the channel layer is modulated by the passivation film of the insulator provided on the barrier layer, the p-type GaN, and the cap layer of InGaN. Will be done. Attempts have also been made to utilize this to partially modulate the concentration of two-dimensional electron gas generated in the channel layer to enhance the characteristics of the semiconductor device. However, with the passivation film of an insulator, the modulation effect is small, and a semiconductor device having sufficient characteristics may not be obtained. In the cap layer such as p-type GaN, the diffusion of p-type impurities contained therein to other layers, and in the cap layer of InGaN itself, damage due to heat or the like may cause deterioration of the characteristics of the semiconductor device. is there.

In one aspect, it is an object of the present invention to use a nitride semiconductor to realize a semiconductor device having excellent characteristics.

In one embodiment, a channel layer containing a first nitride semiconductor, a barrier layer provided on the channel layer and containing a second nitride semiconductor, and a cap provided in a first region on the barrier layer. The cap structure includes a first layer containing In _x Ga _1-x N (0 <x <1) and a second layer provided on the first layer and containing GaN. The semiconductor device to have is provided.

Further, in one aspect, a method for manufacturing a semiconductor device as described above and an electronic device including the semiconductor device as described above are provided.

On one aspect, it becomes possible to realize a semiconductor device having excellent characteristics by using a nitride semiconductor.

It is a figure which shows the example of the semiconductor device. It is a figure explaining an example of the semiconductor device which concerns on 1st Embodiment. It is a figure explaining the energy band structure of an example of the semiconductor device which concerns on 1st Embodiment. It is a figure explaining the modification of the semiconductor device which concerns on 1st Embodiment. It is a figure explaining an example of the semiconductor device which concerns on 2nd Embodiment. It is a figure explaining the 1st modification of the semiconductor device which concerns on 2nd Embodiment. It is a figure explaining the 2nd modification of the semiconductor device which concerns on 2nd Embodiment. It is a figure explaining an example of the semiconductor device which concerns on 3rd Embodiment. It is a figure explaining an example of the semiconductor device which concerns on 4th Embodiment. It is a figure (the 1) explaining an example of the forming method of the semiconductor device which concerns on 4th Embodiment. It is a figure (the 2) explaining an example of the forming method of the semiconductor device which concerns on 4th Embodiment. It is a figure (the 3) explaining an example of the forming method of the semiconductor device which concerns on 4th Embodiment. It is a figure (the 4) explaining an example of the forming method of the semiconductor device which concerns on 4th Embodiment. It is a figure (the 5) explaining an example of the forming method of the semiconductor device which concerns on 4th Embodiment. It is a figure explaining an example of the semiconductor device which concerns on 5th Embodiment. It is a figure (the 1) explaining an example of the forming method of the semiconductor device which concerns on 5th Embodiment. It is a figure (the 2) explaining an example of the forming method of the semiconductor device which concerns on 5th Embodiment. It is a figure (the 3) explaining an example of the forming method of the semiconductor device which concerns on 5th Embodiment. It is a figure (the 4) explaining an example of the forming method of the semiconductor device which concerns on 5th Embodiment. It is a figure explaining an example of the semiconductor device which concerns on 6th Embodiment. It is a figure explaining an example of the semiconductor package which concerns on 7th Embodiment. It is a figure explaining an example of the power factor improvement circuit which concerns on 8th Embodiment. It is a figure explaining an example of the power-source device which concerns on 9th Embodiment. It is a figure explaining an example of the amplifier which concerns on 10th Embodiment.

First, an example of a semiconductor device using a nitride semiconductor will be described.
FIG. 1 is a diagram showing an example of a semiconductor device. FIG. 1A schematically shows a cross-sectional view of a main part of a first example of a semiconductor device. FIG. 1B schematically shows a cross-sectional view of a main part of a second example of a semiconductor device.

The semiconductor device 100A shown in FIG. 1A is an example of a High Electron Mobility Transistor (HEMT). The semiconductor device 100A has a channel layer 101 in which a nitride semiconductor is used, and a barrier layer 102 that is provided on the channel layer 101 and in which a nitride semiconductor is used. For example, GaN is used for the channel layer 101 and AlGaN is used for the barrier layer 102. Two dimensional electron gas (2DEG) 103 is generated in the channel layer 101 near the junction interface with the barrier layer 102. The semiconductor device 100A further includes a cap layer 104A provided on the barrier layer 102, a gate electrode 105 provided on the cap layer 104A, and a source electrode 106 and a drain electrode 107 provided on the barrier layer 102. .. For the cap layer 104A, a p-type nitride semiconductor, for example, GaN (p-type GaN) containing magnesium (Mg) as a p-type impurity is used. A gate electrode 105 is provided on such a cap layer 104A, and a source electrode 106 and a drain electrode 107 are provided on the barrier layers 102 on both sides of the gate electrode 105. Metal is used for the gate electrode 105, the source electrode 106, and the drain electrode 107.

The exemplary semiconductor device 100A attempts to suppress the formation of 2DEG 103 by pushing up the conduction band at the junction interface between the channel layer 101 and the barrier layer 102 below the gate electrode 105 by the fixed charge of the p-type GaN cap layer 104A. Is.

Further, the semiconductor device 100B shown in FIG. 1B is another example of HEMT. The semiconductor device 100B is different from the semiconductor device 100A in that InGaN is used for the cap layer 104B provided on the barrier layer 102.

In the exemplary semiconductor device 100B, the InGaN cap layer 104B provided on the AlGaN barrier layer 102 has compressive strain. The semiconductor device 100B pushes up the conduction band at the junction interface between the channel layer 101 and the barrier layer 102 below the gate electrode 105 by the piezo polarization generated in the cap layer 104B due to this compression strain, and suppresses the formation of the 2DEG 103. Is to be.

In the semiconductor device 100A and the semiconductor device 100B, if the 2DEG 103 generated in the channel layer 101 below the gate electrode 105 is suppressed, the current flowing between the drain electrode 107 and the source electrode 106 is cut off when the gate voltage is turned off. A mold HEMT is realized. In order to modulate the channel layer 101 so as to partially suppress the formation of the 2DEG103, in the semiconductor device 100A and the semiconductor device 100B, the cap layer 104A using p-type GaN and the cap layer 104B using InGaN are used, respectively. Provided.

However, when p-type GaN is used for the cap layer 104A as in the semiconductor device 100A, p-type impurities such as Mg contained therein may diffuse to the channel layer 101, resulting in deterioration of the on-resistance (Ron). .. Further, since the activation rate of p-type impurities such as Mg injected into GaN is low, the contribution of the cap layer 104A is small, and the concentration of 2DEG103 in the channel layer 101 may not be sufficiently modulated. Since the activation rate of p-type impurities is low, when a large amount of p-type impurities is introduced into GaN, the above-mentioned diffusion of p-type impurities into the channel layer 101 and deterioration of on-resistance are likely to occur.

Further, in the semiconductor device 100B using InGaN for the cap layer 104B, in the manufacturing process, after the cap layer 104B is formed on the barrier layer 102, the cap layer 104B may be exposed to high temperature heat while being exposed to the surface. is there. When the cap layer 104B is exposed to high-temperature heat while being exposed to the surface in this way, the cap layer 104B is liable to be damaged, such as desorption of indium (In), which is relatively sensitive to heat. If the cap layer 104B is damaged, the leakage current may increase or the sufficient modulation effect of the 2DEG 103 of the channel layer 101 may not be obtained.

As described above, in the semiconductor device 100A and the semiconductor device 100B, it may not be possible to realize sufficient characteristics such as low on-resistance, low leakage current, and normalization by density modulation of 2DEG103 by using a nitride semiconductor.

In view of the above points, here, a configuration as illustrated below as an embodiment is adopted, and a nitride semiconductor is used to realize a semiconductor device having excellent characteristics.
[First Embodiment]
FIG. 2 is a diagram illustrating an example of a semiconductor device according to the first embodiment. FIG. 2 schematically shows a cross-sectional view of a main part of an example of a semiconductor device.

The semiconductor device 10A shown in FIG. 2 is an example of HEMT. The semiconductor device 10A has a channel layer 11, a barrier layer 12, a cap structure 14, a gate electrode 15, a source electrode 16, and a drain electrode 17.

The channel layer 11 is provided on a predetermined substrate (not shown), for example, a substrate such as silicon carbide (SiC) or a substrate on which a nucleation layer or a buffer layer is formed. A nitride semiconductor, for example, GaN is used for the channel layer 11. In addition, a nitride semiconductor such as InGaN, AlGaN, or indium aluminum gallium nitride (InAlGaN) may be used for the channel layer 11. The channel layer 11 may have a single-layer structure of one kind of nitride semiconductor, or may have a laminated structure of one kind or two or more kinds of nitride semiconductors. For the channel layer 11, for example, an undoped nitride semiconductor is used. For example, the channel layer 11 is formed on a predetermined substrate using the Metal Organic Chemical Vapor Deposition (MOCVD, or Metal Organic Vaper Phase Epitaxy; MOVPE) method. The channel layer 11 is also referred to as an electronic traveling layer.

The barrier layer 12 is provided on the channel layer 11. A nitride semiconductor, for example, AlGaN is used for the barrier layer 12. In addition, a nitride semiconductor such as indium aluminum nitride (InAlN), InAlGaN, or aluminum nitride (AlN) may be used for the barrier layer 12. The barrier layer 12 may have a single-layer structure of one type of nitride semiconductor, or may have a laminated structure of one type or two or more types of nitride semiconductors. For the barrier layer 12, for example, an undoped nitride semiconductor is used. For example, the barrier layer 12 is formed on the channel layer 11 using the MOVPE method. The barrier layer 12 is also referred to as an electron supply layer.

Here, nitride semiconductors having different band gaps are used for the channel layer 11 and the barrier layer 12. By providing the barrier layer 12 using a nitride semiconductor having a band gap larger than that on the channel layer 11, a heterojunction structure having a band discontinuity is formed. By setting the Fermi level above the conduction band (high energy side) of the junction interface between the channel layer 11 and the barrier layer 12, 2DEG13 is generated in the channel layer 11 of the junction interface. Piezo polarization is generated in the barrier layer 12 by providing the barrier layer 12 using a nitride semiconductor having a larger lattice constant than the channel layer 11. The spontaneous polarization of the nitride semiconductor used for the barrier layer 12 and the piezo polarization generated due to its lattice constant produce a high concentration of 2DEG13 in the channel layer 11 at the junction interface. For the channel layer 11 and the barrier layer 12, nitride semiconductors having a combination such that 2DEG13 is generated in the vicinity of their junction interface are used.

Note that FIG. 2 illustrates a state in which a part of 2DEG13 generated in the vicinity of the junction interface between the channel layer 11 and the barrier layer 12 is eliminated. This point will be described later.

The cap structure 14 is provided in a part of the barrier layer 12, in this example, in the area where the gate electrode 15 is provided. A nitride semiconductor is used for the cap structure 14. The cap structure 14 has a first cap layer 14a on the lower layer side provided on the barrier layer 12 and a second cap layer 14b on the upper layer side provided on the cap layer 14a. In _x Ga _1-x N (0 <x <1) (also simply referred to as InGaN) is used for the cap layer 14a on the lower layer side. GaN is used for the cap layer 14b on the upper layer side. As shown in FIG. 2, the cap layer 14a containing InGaN has a function of suppressing the formation of 2DEG13, which is a part of the channel layer 11. This point will be described later. The cap layer 14b containing GaN has a function of protecting the surface of the cap layer 14a containing In, which is relatively heat-sensitive.

For the cap layer 14a on the lower layer side, for example, undoped InGaN is used. The InGaN of the cap layer 14a is formed on the barrier layer 12 by using, for example, the MOVPE method. For the cap layer 14b on the upper layer side, for example, undoped GaN is used. The GaN of the cap layer 14b is formed on the cap layer 14a by using, for example, the MOVPE method.

The gate electrode 15 is provided on the cap structure 14. A protective film such as an oxide, a nitride, or an oxynitride may be interposed between the gate electrode 15 and the cap structure 14. The gate electrode 15 functions as a Schottky electrode or a Schottky gate electrode. A metal is used for the gate electrode 15. For example, as the gate electrode 15, a metal electrode having nickel (Ni) and gold (Au) provided on the nickel (Ni) is provided. The gate electrode 15 is formed by using a vapor deposition method or the like.

The source electrode 16 and the drain electrode 17 are provided on the barrier layers 12 on both sides of the gate electrode 15. The source electrode 16 and the drain electrode 17 are provided on the barrier layer 12 so as to function as ohmic electrodes. Metal is used for the source electrode 16 and the drain electrode 17. For example, as the source electrode 16 and the drain electrode 17, a metal electrode having tantalum (Ta) and aluminum (Al) provided on the tantalum (Ta) is provided. The source electrode 16 and the drain electrode 17 are formed by using a vapor deposition method or the like.

Subsequently, the concentration modulation of 2DEG13 generated in the channel layer 11 will be described.
FIG. 3 is a diagram illustrating an energy band structure of an example of the semiconductor device according to the first embodiment. FIG. 3A shows an energy band structure in the thickness direction when the gate voltage is off in a region where the cap structure is not provided. FIG. 3B shows an energy band structure in the thickness direction when the gate voltage is off in the region where the cap structure is provided.

Here, a semiconductor device 10A in which GaN is used for the channel layer 11 and AlGaN is used for the barrier layer 12 is taken as an example. In such a semiconductor device 10A, the AlGaN of the barrier layer 12 has a larger bandgap and a smaller lattice constant than the GaN of the channel layer 11. Due to this, the band discontinuity and polarization, and the Fermi level Ef are higher than the conduction band Ec of the junction interface (AlGaN / GaN junction interface) between the barrier layer 12 and the channel layer 11, so that FIG. 3 (A) ), A high concentration of 2DEG13 is generated near the AlGaN / GaN junction interface.

In the semiconductor device 10A shown in FIG. 2, the region where the cap structure 14 is not provided, that is, the channel layer 11 below the region on both sides of the gate electrode 15 has an energy band structure as shown in FIG. 3 (A). Based on this, 2DEG13 is generated.

In the semiconductor device 10A, a cap structure 14 having a cap layer 14a using InGaN and a cap layer 14b using GaN on it is provided on the barrier layer 12 using AlGaN in the region where the gate electrode 15 is provided. .. The InGaN of the cap layer 14a has a larger lattice constant than the AlGaN of the barrier layer 12. Therefore, the InGaN of the cap layer 14a provided on the AlGaN of the barrier layer 12 has a compressive strain. Due to this compressive strain, piezo polarization opposite to that generated in AlGaN of the barrier layer 12 is generated in InGaN of the cap layer 14a. As shown in FIG. 3B, the piezopolarization generated in the InGaN of the cap layer 14a pushes up the conduction band Ec of the AlGaN of the barrier layer 12 and the GaN of the channel layer 11, and is near the AlGaN / GaN junction interface. The production of 2DEG13 is suppressed. For example, the conduction band Ec at the AlGaN / GaN junction interface is pushed up above the Fermi level Ef, so that 2DEG13 disappears.

In the region of the semiconductor device 10A shown in FIG. 2 where the cap structure 14 is provided, that is, in the channel layer 11 below the gate electrode 15, 2DEG13 is generated based on the energy band structure as shown in FIG. 3B. Is suppressed and 2DEG13 is reduced or eliminated.

In the semiconductor device 10A, the 2DEG 13 generated in the channel layer 11 is modulated by the InGaN of the cap layer 14a provided on the barrier layer 12 so as to be partially reduced in concentration. In this example, the 2DEG13 of the channel layer 11 below the gate electrode 15 is modulated so that the concentration is lower than that of other parts, thereby realizing a semiconductor device 10A that functions as a normal-off type HEMT.

The cap structure 14 will be further described.
As described above, the InGaN of the cap layer 14a that partially reduces the concentration of 2DEG13 of the channel layer 11 contains In that is relatively heat-sensitive. Therefore, when the InGaN cap layer 14a is exposed to a high temperature of several hundred ° C. while being exposed to the surface, the InGaN cap layer 14a is susceptible to damage such as desorption of In. For example, in the manufacturing process of the semiconductor device 10A, the InGaN of the cap layer 14a is exposed to a high temperature from the time when the cap layer 14a is formed until the end of the formation of the gate electrode 15 provided on the cap layer 14a (when the passivation film or the gate electrode is formed, etc.). Can be done. If InGaN is damaged by exposure to a high temperature, the leakage current may increase or the concentration of 2DEG13 in the channel layer 11 below the gate electrode 15 may not be sufficiently reduced.

In the semiconductor device 10A, a cap layer 14b that protects the InGaN of the cap layer 14a is provided on the cap layer 14a that can receive such damage. GaN is used for the cap layer 14b. When the InGaN of the cap layer 14a is formed by the MOVPE method, the GaN of the cap layer 14b can be continuously formed on the InGaN by the MOVPE method in which the raw material gas is switched (the supply of the In source is stopped). .. In this way, the cap layer 14a is protected by the GaN of the cap layer 14b continuously formed on the InGaN, so that the cap layer 14a is prevented from being exposed to high temperature heat while being exposed to the surface. As a result, InGaN with suppressed damage is formed on the barrier layer 12 as a cap layer 14a for partially reducing the concentration of 2DEG13 of the channel layer 11.

The InGaN of the cap layer 14a is protected by the GaN of the cap layer 14b, and the damage of the InGaN is suppressed. Therefore, the generation of leakage current due to the damaged InGaN is suppressed, and a highly reliable semiconductor device 10A is realized. Will be done. Further, since the damage of InGaN is suppressed by the protection by GaN, the formation of 2DEG13 in the channel layer 11 below the gate electrode 15 is sufficiently suppressed by the InGaN, and normalization is realized. Further, diffusion of p-type impurities, which occurs when a p-type nitride semiconductor is used for the cap layer, and deterioration of on-resistance due to the diffusion are avoided. By providing the cap structure 14 having InGaN and the GaN that protects it, a semiconductor device 10A using a nitride semiconductor having excellent characteristics such as high reliability, normal off type, and low on-resistance is realized.

By the way, as one of the techniques for realizing normalization, there is a technique of adjusting the thickness and composition of a barrier layer in which AlGaN or the like is used to suppress the generation of 2DEG due to the polarization effect. However, in this technique, the 2DEG concentration in the channel layer decreases and the resistance of the channel layer increases, leading to an increase in on-resistance. Therefore, with this technique, it is difficult to achieve both normalization and low on-resistance. On the other hand, in the semiconductor device 10A, the cap structure 14 as described above is provided on the barrier layer 12 in the region where the gate electrode 15 is provided. As a result, while achieving low on-resistance, the concentration of 2DEG13 in the channel layer 11 below the gate electrode 15 is partially reduced, and thus normalization is realized.

Table 1 shows an example of the results of a simulation performed on the semiconductor device 10A having the above configuration.

Table 1 shows the concentration [cm ^-3 ] of 2DEG13 of the channel layer 11 and the sheet in the “with cap structure” region where the cap structure 14 is provided and the “without cap structure” region where the cap structure 14 is not provided. An example of the simulation result of the resistance [Ω / □] is shown. From Table 1, the concentration of 2DEG13 in the channel layer 11 is significantly higher in the “with cap structure” region, that is, below the gate electrode 15, than in the “without cap structure” region, that is, below the regions on both sides of the gate electrode 15. To reduce to. Further, the sheet resistance of the channel layer 11 is significantly increased in the “with cap structure” region as compared with the “without cap structure” region.

As described above, in the semiconductor device 10A, the cap structure 14 modulates the 2DEG 13 generated in the channel layer 11 so as to reduce the concentration below the gate electrode 15 to normalize off. By providing the cap structure 14 in the region where the gate electrode 15 is provided, the semiconductor device 10A having excellent device characteristics is realized.

In the cap structure 14, the thickness of InGaN in the cap layer 14a is preferably 2 nm or less. This is because if the thickness of InGaN in the cap layer 14a exceeds 2 nm, the possibility of electrons leaking into the cap layer 14a increases, and the withstand voltage of the cap layer 14a may decrease. Further, in the cap structure 14, the In composition x of InGaN of the cap layer 14a is preferably in the range of 0.05 or more and 0.20 or less (0.05 ≦ x ≦ 0.20). This is because when the In composition x is less than 0.05, the difference from GaN becomes small, and the effect of providing InGaN can be small. This is because if the In composition x exceeds 0.20, the possibility of electrons leaking to the cap layer 14a increases, and the withstand voltage of the cap layer 14a may decrease. Further, when the In composition x exceeds 0.20, the lattice mismatch of the barrier layer 12 with AlGaN becomes large, appropriate piezo polarization cannot be obtained, and the effect of providing InGaN can be reduced.

Further, in the cap structure 14, the thickness of GaN in the cap layer 14b is preferably 2 nm or more. This is because if the thickness of the GaN of the cap layer 14b is less than 2 nm, the surface of the InGaN of the cap layer 14a is not sufficiently covered with GaN, and the damage of the InGaN may not be sufficiently suppressed.

The thickness of the cap structure 14 having the InGaN cap layer 14a and the GaN cap layer 14b that protects the cap layer 14a is determined, for example, from the viewpoint of realizing an appropriate on / off operation by the electric field of the gate electrode 15 provided on the cap layer 14a. It can be set to 5 nm or less.

The gate electrode 15 does not necessarily have to be entirely provided on the upper surface of the cap structure 14.
FIG. 4 is a diagram illustrating a modified example of the semiconductor device according to the first embodiment. FIG. 4 schematically shows a cross-sectional view of a main part of an example of a semiconductor device.

The semiconductor device 10B shown in FIG. 4 has a configuration in which a part of the gate electrode 15 is provided on the upper surface 14c of the cap structure 14 and the other part of the gate electrode 15 is provided on the upper surface 12c of the barrier layer 12. , Different from the semiconductor device 10A. In the semiconductor device 10B, one side surface of the cap structure 14 (one side surface of InGaN of the cap layer 14a and one side surface of GaN of the cap layer 14b) is covered with the gate electrode 15.

Also in such a semiconductor device 10B, the cap structure 14 modulates the 2DEG 13 generated in the channel layer 11 so that the concentration is partially reduced below the gate electrode 15. As a result, normalization is realized.

In addition, the gate electrode 15 may be provided with a size larger than that of the cap structure 14 so as to cover all the upper surface and the side surface of the cap structure 14 provided on the barrier layer 12. Further, the gate electrode 15 may be provided with a small size so that the edge thereof is located inside the edge of the cap structure 14 provided on the barrier layer 12.

[Second Embodiment]
FIG. 5 is a diagram illustrating an example of a semiconductor device according to the second embodiment. FIG. 5 schematically shows a cross-sectional view of a main part of an example of a semiconductor device.

The semiconductor device 10C shown in FIG. 5 is an example of HEMT. The semiconductor device 10C has a channel layer 11, a barrier layer 12, a cap structure 14, a gate electrode 15, a source electrode 16, and a drain electrode 17. The semiconductor device 10C has a structure in which the cap structure 14 is provided on the barrier layer 12 between the gate electrode 15 and the drain electrode 17. In this example, the cap structure 14 is provided in the region on the barrier layer 12 from a part under the gate electrode 15 to reach the drain electrode 17. A part of the gate electrode 15 is provided on the upper surface 14c of the cap structure 14, and the other part of the gate electrode 15 is provided on the upper surface 12c of the barrier layer 12. As described above, the semiconductor device 10C has the cap structure 14 on the barrier layer 12 between the gate electrode 15 and the drain electrode 17, and is different from the semiconductor device 10A (FIG. 2) described in the first embodiment. It is different.

Similar to the semiconductor device 10A, the cap structure 14 of the semiconductor device 10C has an InGaN cap layer 14a and a GaN cap layer 14b that protects the surface thereof. In the semiconductor device 10C, such a cap structure 14 is provided on the barrier layer 12 between the gate electrode 15 and the drain electrode 17. In the semiconductor device 10C, the cap structure 14 provided on the barrier layer 12 in this way reduces the concentration of 2DEG13 in the channel layer 11 below it.

That is, also in the semiconductor device 10C, piezo polarization is generated in the InGaN due to the compressive strain of the InGaN of the cap layer 14a provided on the barrier layer 12 such as AlGaN, as described for the semiconductor device 10A. .. The piezo polarization generated in the InGaN of the cap layer 14a pushes up the conduction band Ec at the junction interface between the channel layer 11 and the barrier layer 12, which corresponds to the region between the gate electrode 15 and the drain electrode 17, and 2DEG13. Generation is suppressed. As a result, the concentration of 2DEG13 in the channel layer 11 below the region between the gate electrode 15 and the drain electrode 17 is reduced.

In this way, the cap structure 14 is provided on the barrier layer 12 between the gate electrode 15 and the drain electrode 17, and the concentration of 2DEG13 in the channel layer 11 below the cap structure 14 is reduced, so that the high withstand voltage semiconductor device 10C Is realized. A semiconductor device 10C having excellent device characteristics is realized, which relaxes the electric field generated between the gate electrode 15 and the drain electrode 17 and operates properly even when a condition in which a high drain voltage is applied is used.

In the semiconductor device 10C, the InGaN of the cap layer 14a is protected by the GaN of the cap layer 14b formed on the InGaN of the cap layer 14a, as described for the semiconductor device 10A. As a result, a highly reliable semiconductor device 10C is realized in which damage such as desorption of In from InGaN of the cap layer 14a is suppressed and generation of leakage current is suppressed.

Table 2 shows an example of the results of a simulation performed on the semiconductor device 10C having the above configuration.

Table 2 shows the concentration [× 10 ¹² cm ^-3 ] of 2DEG13 of the channel layer 11 and the sheet resistance [Ω] on the “drain side” where the cap structure 14 is provided and the “source side” where the cap structure 14 is not provided. / □] shows an example of the simulation result. From Table 2, the concentration of 2DEG13 in the “drain side” channel layer 11 is lower than the concentration of 2DEG13 in the “source side” channel layer 11. Further, the sheet resistance of the “drain side” channel layer 11 is higher than the sheet resistance of the “source side” channel layer 11.

As described above, in the semiconductor device 10C, the cap structure 14 modulates the 2DEG 13 generated in the channel layer 11 so as to have a low concentration below the region between the gate electrode 15 and the drain electrode 17, and the concentration is high. The pressure resistance is increased. By providing the cap structure 14 between the gate electrode 15 and the drain electrode 17, a semiconductor device 10C having a high withstand voltage and excellent device characteristics is realized.

In the semiconductor device 10C as well, as described for the semiconductor device 10A, the InGaN of the cap layer 14a preferably has a thickness of 2 nm or less, and its In composition x is 0.05 or more and 0. The range is preferably 20 or less. Further, the thickness of the GaN of the cap layer 14b is preferably 2 nm or more. The thickness of the cap structure 14 having the InGaN cap layer 14a and the GaN cap layer 14b that protects the cap layer 14a can be set to, for example, 5 nm or less.

FIG. 6 is a diagram illustrating a first modification of the semiconductor device according to the second embodiment. FIG. 6 schematically shows a cross-sectional view of a main part of an example of a semiconductor device.
The semiconductor device 10D shown in FIG. 6 differs from the semiconductor device 10C (FIG. 5) in that the entire gate electrode 15 is provided on the upper surface 14c of the cap structure 14 (cap layer 14b thereof).

Also in the semiconductor device 10D, the cap structure 14 reduces the concentration of 2DEG13 in the channel layer 11 below the gate electrode 15 (the whole thereof) to the drain electrode 17, and realizes high withstand voltage.

FIG. 7 is a diagram illustrating a second modification of the semiconductor device according to the second embodiment. FIG. 7 schematically shows a cross-sectional view of a main part of an example of a semiconductor device.
The semiconductor device 10E shown in FIG. 7 has an asymmetric structure in which the gate electrode 15 is provided unevenly toward the source electrode 16 and the distance between the gate electrode 15 and the drain electrode 17 is wider than the distance between the gate electrode 15 and the source electrode. It is different from the above-mentioned semiconductor device 10C in that it has.

The semiconductor device 10E has a cap structure having an InGaN cap layer 14a and a GaN cap layer 14b that protects the InGaN cap layer 14a on the barrier layer 12 between the gate electrode 15 and the drain electrode 17 that are spaced apart in this way. 14 is provided.

Also in the semiconductor device 10E, the cap structure 14 reduces the concentration of 2DEG13 in the channel layer 11 below the region between the gate electrode 15 and the drain electrode 17, and realizes a high withstand voltage. Further, in the semiconductor device 10E, by widening the distance between the gate electrode 15 and the drain electrode 17, the effect of relaxing the electric field generated between them is enhanced, and the withstand voltage is improved.

The semiconductor devices 10C, 10D, and 10E described in the second embodiment may be mixedly mounted on one substrate common to the semiconductor devices 10A and 10B described in the first embodiment. .. For example, it is possible to obtain a semiconductor device or the like in which a semiconductor device 10A and a semiconductor device 10C are mixedly mounted on one substrate.

[Third Embodiment]
FIG. 8 is a diagram illustrating an example of a semiconductor device according to the third embodiment. FIG. 8 schematically shows a cross-sectional view of a main part of an example of a semiconductor device.

The semiconductor device 10F shown in FIG. 8 is an example of a Schottky Barrier Diode (SBD). The semiconductor device 10F has a channel layer 11, a barrier layer 12, a cap structure 14, a cathode electrode 18 (ohmic electrode), and an anode electrode 19 (Schottky electrode).

For the channel layer 11 and the barrier layer 12 of the semiconductor device 10F, the same nitride semiconductor as described for the semiconductor device 10A (FIG. 2) and the like is used. The cap structure 14 of the semiconductor device 10F has an InGaN cap layer 14a and a GaN cap layer 14b that protects the surface thereof. The cap structure 14 of the semiconductor device 10F is provided in a part of the area near the anode electrode 19 on the barrier layer 12 between the cathode electrode 18 and the anode electrode 19. Metal is used for the cathode electrode 18 and the anode electrode 19 of the semiconductor device 10F. The cathode electrode 18 is provided on the barrier layer 12 so as to function as an ohmic electrode, and the anode electrode 19 is provided on the barrier layer 12 so as to function as a Schottky electrode.

Generally, in SBD, when a reverse bias is applied, the electric field tends to concentrate on the anode electrode side connected to the shot key. In the semiconductor device 10F, the cap structure 14 is provided in a part of the region near the anode electrode 19 on the barrier layer 12, and the concentration of 2DEG13 in the channel layer 11 below the region is reduced, so that a reverse bias is applied. The electric field on the anode electrode 19 side at that time is relaxed. As a result, SBD with high reverse pressure resistance is realized.

The semiconductor device 10F described in the third embodiment includes the semiconductor devices 10A and 10B described in the first embodiment and the semiconductor devices 10C, 10D and 10E described in the second embodiment. , May be mixedly mounted on one common substrate. For example, obtaining a semiconductor device in which a semiconductor device 10A and a semiconductor device 10F are mixedly mounted on one substrate, a semiconductor device in which a semiconductor device 10C and a semiconductor device 10F are mixedly mounted on one substrate, or the like is obtained. You can also. Alternatively, it is also possible to obtain a semiconductor device or the like in which the semiconductor device 10A, the semiconductor device 10C, and the semiconductor device 10F are mixedly mounted on one substrate.

[Fourth Embodiment]
Here, an example of a semiconductor device including the configuration as described in the first embodiment and a method for forming the semiconductor device will be described.

FIG. 9 is a diagram illustrating an example of the semiconductor device according to the fourth embodiment. FIG. 9 schematically shows a cross-sectional view of a main part of an example of a semiconductor device.
The semiconductor device 10G shown in FIG. 9 is an example of HEMT. The semiconductor device 10G has a substrate 20 and a nucleation layer 21 provided on the substrate 20. For the substrate 20, for example, a semi-insulating SiC substrate is used. A nitride semiconductor, for example, AlN, is used for the nucleation layer 21. The nucleation layer 21 is formed, for example, by using the MOVPE method.

The channel layer 11 and the barrier layer 12 as described in the first embodiment are provided on the nucleation layer 21 provided on the substrate 20. For the channel layer 11 and the barrier layer 12, nitride semiconductors similar to those described for the semiconductor device 10A (FIG. 2) and the like are used. For example, GaN is used for the channel layer 11 and AlGaN is used for the barrier layer 12. A cap structure 14 having an InGaN cap layer 14a and a GaN cap layer 14b that protects the surface thereof is provided in a part of the region on the barrier layer 12. The gate electrode 15 is provided on the cap structure 14, and the source electrode 16 and the drain electrode 17 are provided on the barrier layers 12 on both sides of the gate electrode 15. A passivation film 22 is provided on the barrier layers 12 on both sides of the gate electrode 15, and on the source electrode 16 and the drain electrode 17.

In the semiconductor device 10G, the cap structure 14 is provided on the barrier layer 12 in the region where the gate electrode 15 is provided. The conduction band is pushed up by the piezo polarization generated in the InGaN cap layer 14a of the cap structure 14 provided on the barrier layer 12, and the concentration of 2DEG13 of the channel layer 11 corresponding to the region where the gate electrode 15 is provided is reduced. Will be done. As a result, a semiconductor device 10G that functions as a normally-off type HEMT is realized. Further, in the semiconductor device 10G, a GaN cap layer 14b for protecting the InGaN cap layer 14a is provided on the InGaN cap layer 14a. As a result, a highly reliable semiconductor device 10G that functions as a normally-off type HEMT is realized.

Subsequently, an example of a method for forming the semiconductor device 10G having the above configuration will be described.
10 to 14 are views for explaining an example of a method for forming a semiconductor device according to the fourth embodiment. 10 to 14 schematically show a cross-sectional view of a main part of an example of each process of forming a semiconductor device.

First, as shown in FIG. 10, the nucleation layer 21, the channel layer 11, the barrier layer 12, the cap layer 14a, and the cap layer 14b are sequentially grown on the substrate 20 by using the MOVPE method. Here, a semi-insulating SiC substrate is used as the substrate 20, and an AlN nucleation layer 21, a GaN channel layer 11, and a barrier layer 12 of Al _y Ga _1-y N (0 <y <1) are used on the substrate 20. , In _x Ga _1-x N (0 <x <1) cap layer 14a and GaN cap layer 14b are grown as an example. For example, an AlN nucleation layer 21 having a thickness of 100 nm is grown on the substrate 20, a GaN channel layer 11 having a thickness of 3 μm is grown on the nucleation layer 21, and an Al _0.4 having a thickness of 6 nm is grown on the channel layer 11. The barrier layer 12 of Ga _0.6 N is grown. For example, a cap layer 14a of In _0.2 Ga _0.8 N having a thickness of 1 nm is grown on the barrier layer 12, and a GaN cap layer 14b having a thickness of 3 nm is grown on the cap layer 14a.

In the growth of each layer using the MOVPE method, a mixed gas of trimethylaluminum (Tri-Methyl-Aluminum; TMAl), which is an Al source, and ammonia (NH ₃ ) is used for the growth of AlN. A mixed gas of trimethylgallium (Tri-Methyl-Gallium; TMGa), which is a gallium (Ga) source, and NH ₃ is used for the growth of GaN. A mixed gas of TMAl, TMGa, and NH ₃ is used for the growth of AlGaN. For the growth of InGaN, a mixed gas of trimethylindium (Tri-Methyl-Indium; TMIn), which is an In source, TMGa, and NH ₃ is used. Depending on the growing nitride semiconductor, the supply and stop (switching) of TMAl, TMGa, and TMIn, and the flow rate at the time of supply (mixing ratio with other raw materials) are appropriately set. The growth pressure is about 1 kPa to 100 kPa, and the growth temperature is about 600 ° C. to 1200 ° C.

In the step shown in FIG. 10, after the growth of the InGaN cap layer 14a, the GaN cap layer 14b can be continuously grown. As a result, InGaN is protected by GaN. By protecting InGaN with GaN in this way, it is possible to avoid exposure of InGaN to a high temperature while being exposed to the surface in the subsequent steps described later. As a result, desorption of In from InGaN is suppressed, and the semiconductor device 10G including the cap layer 14a containing InGaN having a predetermined composition is formed.

After the growth of each layer, the InGaN cap layer 14a and the GaN cap layer 14b are patterned so as to be provided in a part of the region (the region forming the gate electrode 15) on the barrier layer 12 as shown in FIG. , The cap structure 14 is formed.

At that time, first, a protective film (not shown) is formed on the grown uppermost GaN cap layer 14b by using a plasma CVD (Chemical Vapor Deposition) method. Atomic layer deposition (ALD) method, sputtering method and the like may be used for forming the protective film. As the protective film, for example, oxides, nitrides or oxynitrides containing silicon (Si), Al, hafnium (Hf), zirconium (Zr), titanium (Ti), Ta or tungsten (W) are used. For example, silicon oxide (SiO ₂ ) is formed as a protective film. On the formed protective film, a resist having an opening is formed in a portion other than the region where the gate electrode 15 is formed by using photolithography technology, and etching using this as a mask, for example, fluorine-based or chlorine-based gas. The dry etching used is performed. By this etching, the protective film exposed from the opening of the resist, the GaN cap layer 14b under the protective film, and the InGaN cap layer 14a are removed. By such a method, a state in which a cap structure 14 having an InGaN cap layer 14a and a GaN cap layer 14b is formed on the barrier layer 12 in the region forming the gate electrode 15 as shown in FIG. can get. The protective film may remain on the cap structure 14 (not shown) or may be removed from the cap structure 14.

After the cap structure 14 is formed, a resist having an opening is provided in the inter-element separation region using photolithography technology, and the inter-element separation region (FIG. 6) is formed by etching (dry etching using chlorine-based gas, etc.) or ion implantation. (Not shown) may be formed.

Next, as shown in FIG. 12, the source electrode 16 and the drain electrode 17 are formed on the barrier layers 12 on both sides of the cap structure 14. In that case, first, using a photolithography technique, a vapor deposition technique, and a lift-off technique, an electrode metal, for example, Ta having a thickness of 20 nm and a thickness on the barrier layer 12 in the region where the source electrode 16 and the drain electrode 17 are formed. A laminate with Al having a diameter of 200 nm is formed. Then, heat treatment is performed at 400 ° C. to 1000 ° C., for example, 550 ° C. in a nitrogen atmosphere, and the electrode metal is ohmic-connected. By such a method, a state in which the source electrode 16 and the drain electrode 17 are formed on the barrier layers 12 on both sides of the cap structure 14 as shown in FIG. 12 can be obtained.

Next, as shown in FIG. 13, the passivation film 22 is formed on the barrier layer 12 on which the cap structure 14, the source electrode 16, and the drain electrode 17 are formed. For example, a passivation film 22 having a thickness of 2 nm to 500 nm, for example, a thickness of 100 nm is formed by using a plasma CVD method. An ALD method, a sputtering method, or the like may be used for forming the passivation film 22. For the passivation film 22, for example, an oxide, a nitride or an acid nitride containing Si, Al, Hf, Zr, Ti, Ta or W is used. For example, silicon nitride (SiN) is formed as the passivation film 22. By such a method, a state in which the passivation film 22 is formed on the barrier layer 12 on which the cap structure 14, the source electrode 16 and the drain electrode 17 are formed as shown in FIG. 13 can be obtained.

Next, as shown in FIG. 14, the passivation film 22 in the region forming the gate electrode 15 is removed, and the cap structure 14 is exposed. At that time, first, a resist having an opening is formed in the region forming the gate electrode 15 by using a photolithography technique, and etching is performed using this as a mask. By this etching, the passivation film 22 exposed from the opening of the resist is removed. Etching of the passivation film 22 is performed by, for example, dry etching using a fluorine-based or chlorine-based gas. In addition, the passivation film 22 may be etched by wet etching using hydrofluoric acid, buffered hydrofluoric acid, or the like. By such a method, as shown in FIG. 14, the passivation film 22 in the region forming the gate electrode 15 is removed, and the cap structure 14 is exposed.

The opening position and opening size of the resist used as a mask when etching the passivation film 22 can be appropriately set. For example, a state in which all or part of the cap structure 14 and a part of the barrier layer 12 are exposed from the portion where the passivation film 22 is removed by etching using a resist as a mask, or only a part of the upper surface of the cap structure 14. It is also possible to obtain an exposed state or the like.

Then, using a photolithography technique, a vapor deposition technique, and a lift-off technique, a laminate of an electrode metal, for example, Ni having a thickness of 30 nm and Au having a thickness of 400 nm is formed on the cap structure 14 exposed from the passivation film 22. The gate electrode 15 is formed. As a result, the semiconductor device 10G as shown in FIG. 9 is obtained.

Here, an example is shown in which GaN having a single layer structure is used for the channel layer 11 of the semiconductor device 10G and AlGaN having a single layer structure is used for the barrier layer 12, but the configuration of the channel layer 11 and the barrier layer 12 is this example. It is not limited to. For example, in the semiconductor device 10G, a nitride semiconductor such as InGaN, AlGaN, or InAlGaN may be used for the channel layer 11, or a single layer structure of one kind of nitride semiconductor may be used, or one kind. Alternatively, a laminated structure of two or more types of nitride semiconductors may be used. Further, in the semiconductor device 10G, a nitride semiconductor such as InAlN, InAlGaN, or AlN may be used for the barrier layer 12, or a single layer structure of one kind of nitride semiconductor may be used, or one kind. Alternatively, a laminated structure of two or more types of nitride semiconductors may be used.

Further, the types and layer structures of the metals used for the gate electrode 15, the source electrode 16 and the drain electrode 17 of the semiconductor device 10G are not limited to the above examples, and their forming methods are also limited to the above examples. is not. A single-layer structure or a laminated structure may be used for the gate electrode 15, the source electrode 16, and the drain electrode 17, respectively. When forming the source electrode 16 and the drain electrode 17, it is not always necessary to perform the above heat treatment as long as ohmic connection is realized by forming the metal for the electrode. When forming the gate electrode 15, further heat treatment may be performed after the metal for the electrode is formed.

Further, although an example in which a semi-insulating SiC substrate is used for the substrate 20 of the semiconductor device 10G is shown here, if a nitride semiconductor is used for the structural portion having the function of a field effect transistor, another substrate material can be used. May be done. The substrate 20 may be semi-insulating or conductive. As the substrate 20, in addition to the semi-insulating SiC substrate, a conductive SiC substrate, a sapphire substrate, a GaN substrate, a Si substrate, a diamond substrate and the like may be used.

[Fifth Embodiment]
Here, an example of a semiconductor device including the configuration as described in the second embodiment and a method for forming the semiconductor device will be described.

FIG. 15 is a diagram illustrating an example of a semiconductor device according to the fifth embodiment. FIG. 15 schematically shows a cross-sectional view of a main part of an example of a semiconductor device.
The semiconductor device 10H shown in FIG. 15 is an example of HEMT. The semiconductor device 10H has a substrate 20 and a nucleation layer 21 provided on the substrate 20. For the substrate 20, for example, a semi-insulating SiC substrate is used. A nitride semiconductor, for example, AlN, is used for the nucleation layer 21. The channel layer 11 and the barrier layer 12 are provided on the nucleation layer 21 provided on the substrate 20. For example, GaN is used for the channel layer 11 and AlGaN is used for the barrier layer 12. On the barrier layer 12, a cap structure 14 having an InGaN cap layer 14a and a GaN cap layer 14b that protects the surface thereof, and a gate electrode 15, a source electrode 16, and a drain electrode 17 are provided. The cap structure 14 is provided on the barrier layer 12 between the gate electrode 15 and the drain electrode 17. A passivation film 22 is provided on the barrier layers 12 on both sides of the gate electrode 15, on the source electrode 16 and the drain electrode 17, and on the cap structure 14 between the gate electrode 15 and the drain electrode 17.

In the semiconductor device 10H, the cap structure 14 is provided in the region between the gate electrode 15 and the drain electrode 17 on the barrier layer 12. The conduction band is pushed up by the piezo polarization generated in the InGaN cap layer 14a of the cap structure 14 provided on the barrier layer 12, and corresponds to the region between the gate electrode 15 and the drain electrode 17. The concentration of 2DEG13 in the lower channel layer 11 is reduced. As a result, a high withstand voltage semiconductor device 10H that functions as a HEMT is realized. Further, in the semiconductor device 10H, a GaN cap layer 14b for protecting the InGaN cap layer 14a is provided on the InGaN cap layer 14a. As a result, a highly reliable semiconductor device 10H that functions as a HEMT is realized.

Subsequently, an example of a method for forming the semiconductor device 10H having the above configuration will be described.
16 to 19 are views for explaining an example of a method for forming a semiconductor device according to the fifth embodiment. 16 to 19 schematically show a cross-sectional view of a main part of an example of each process of forming a semiconductor device.

In the formation of the semiconductor device 10H, first, as in the formation of the semiconductor device 10G described in the fourth embodiment, the nucleation layer 21, the channel layer 11, and the barrier layer are formed on the substrate 20 by using the MOVPE method. 12. The cap layer 14a and the cap layer 14b are sequentially grown (FIG. 10). For example, a semi-insulating SiC substrate is used for the substrate 20, an AlN cambium 21 having a thickness of 100 nm is grown on the substrate 20, and a GaN channel layer 11 having a thickness of 3 μm is grown on the nucleation layer 21. On top of this, a 6 nm-thick Al _0.5 Ga _0.5 N barrier layer 12 is grown. For example, a cap layer 14a of In _0.2 Ga _0.8 N having a thickness of 1 nm is grown on the barrier layer 12, and a GaN cap layer 14b having a thickness of 3 nm is grown on the cap layer 14a.

After the growth of the InGaN cap layer 14a, the GaN cap layer 14b is subsequently grown, and the InGaN is protected by GaN, so that the InGaN is exposed to a high temperature in a state of being exposed to the surface in the subsequent steps described later. Is avoided. As a result, the desorption of In from InGaN is suppressed, and the semiconductor device 10H including the cap layer 14a containing InGaN having a predetermined composition is formed.

After the growth of each layer, the InGaN cap layer 14a and the GaN cap layer 14b are formed in a part of the barrier layer 12 (the region between the gate electrode 15 and the drain electrode 17) as shown in FIG. The cap structure 14 is formed by being patterned so as to be provided. In that case, a protective film (not shown) is formed on the uppermost GaN cap layer 14b, and protection other than the region between the gate electrode 15 and the drain electrode 17 is performed by using photolithography technology and etching technology. The film, cap layer 14b and cap layer 14a are removed. As a result, as shown in FIG. 16, a state in which the cap structure 14 is formed in a part of the region on the barrier layer 12 can be obtained. The protective film may remain on the cap structure 14 (not shown) or may be removed from the cap structure 14.

After the formation of the cap structure 14, an inter-element separation region (not shown) may be formed.
Next, as shown in FIG. 17, the source electrode 16 and the drain electrode 17 are formed on the barrier layer 12. In that case, first, using a photolithography technique, a vapor deposition technique, and a lift-off technique, an electrode metal, for example, Ta having a thickness of 20 nm and a thickness on the barrier layer 12 in the region forming the source electrode 16 and the drain electrode 17 A laminate with Al having a diameter of 200 nm is formed. Then, heat treatment is performed at 400 ° C. to 1000 ° C., for example, 550 ° C. in a nitrogen atmosphere, and the electrode metal is ohmic-connected. As a result, a state in which the source electrode 16 and the drain electrode 17 are formed on the barrier layer 12 as shown in FIG. 17 can be obtained.

Next, as shown in FIG. 18, the passivation film 22 is formed on the barrier layer 12 on which the cap structure 14, the source electrode 16, and the drain electrode 17 are formed. For example, a passivation film 22 having a thickness of 2 nm to 500 nm, for example, a thickness of 100 nm is formed by using a plasma CVD method, an ALD method, a sputtering method, or the like. For the passivation film 22, for example, an oxide, a nitride or an acid nitride containing Si, Al, Hf, Zr, Ti, Ta or W is used. For example, SiN is formed as the passivation film 22. As a result, as shown in FIG. 18, a state in which the passivation film 22 is formed on the barrier layer 12 on which the cap structure 14, the source electrode 16 and the drain electrode 17 are formed can be obtained.

Then, as shown in FIG. 19, the passivation film 22 in the region forming the gate electrode 15 is removed. At that time, first, a resist having an opening is formed in a region forming the gate electrode 15 by using a photolithography technique, and etching is performed using this as a mask. By this etching, the passivation film 22 exposed from the opening of the resist is removed. The passivation film 22 is etched, for example, by dry etching using a fluorine-based or chlorine-based gas, or wet etching using hydrofluoric acid, buffered hydrofluoric acid, or the like. As a result, as shown in FIG. 19, a state in which the passivation film 22 in the region forming the gate electrode 15 is removed can be obtained. The end portion of the cap structure 14 may be exposed in the region where the passivation film 22 has been removed.

The opening position and opening size of the resist used as a mask when etching the passivation film 22 can be appropriately set. For example, from the portion where the passivation film 22 is removed by etching using a resist as a mask, a state in which only the cap structure 14 is exposed or a state in which only the barrier layer 12 is exposed is obtained among the cap structure 14 and the barrier layer 12. You can also do it.

Then, using a photolithography technique, a vapor deposition technique, and a lift-off technique, a laminate of an electrode metal, for example, Ni having a thickness of 30 nm and Au having a thickness of 400 nm is formed in the region where the passivation film 22 has been removed. The gate electrode 15 is formed. As a result, the semiconductor device 10H as shown in FIG. 15 is obtained.

Here, an example is shown in which GaN having a single layer structure is used for the channel layer 11 of the semiconductor device 10H and AlGaN having a single layer structure is used for the barrier layer 12, but the configuration of the channel layer 11 and the barrier layer 12 is this example. It is not limited to. For example, in the semiconductor device 10H, a nitride semiconductor such as InGaN, AlGaN, or InAlGaN may be used for the channel layer 11, or a single layer structure of one kind of nitride semiconductor may be used, or one kind. Alternatively, a laminated structure of two or more types of nitride semiconductors may be used. Further, in the semiconductor device 10H, a nitride semiconductor such as InAlN, InAlGaN, or AlN may be used for the barrier layer 12, or a single layer structure of one kind of nitride semiconductor may be used, or one kind. Alternatively, a laminated structure of two or more types of nitride semiconductors may be used.

Further, the types and layer structures of the metals used for the gate electrode 15, the source electrode 16 and the drain electrode 17 of the semiconductor device 10H are not limited to the above examples, and their forming methods are also limited to the above examples. is not. A single-layer structure or a laminated structure may be used for the gate electrode 15, the source electrode 16, and the drain electrode 17, respectively. When forming the source electrode 16 and the drain electrode 17, it is not always necessary to perform the above heat treatment as long as ohmic connection is realized by forming the metal for the electrode. When forming the gate electrode 15, further heat treatment may be performed after the metal for the electrode is formed.

Further, although an example in which a semi-insulating SiC substrate is used for the substrate 20 of the semiconductor device 10H is shown here, if a nitride semiconductor is used for the structural portion having the function of a field effect transistor, another substrate material can be used. May be done. The substrate 20 may be semi-insulating or conductive. As the substrate 20, in addition to the semi-insulating SiC substrate, a conductive SiC substrate, a sapphire substrate, a GaN substrate, a Si substrate, a diamond substrate and the like may be used.

[Sixth Embodiment]
Here, an example of a semiconductor device including the configuration as described in the third embodiment and a method for forming the semiconductor device will be described.

FIG. 20 is a diagram illustrating an example of a semiconductor device according to the sixth embodiment. FIG. 20 schematically shows a cross-sectional view of a main part of an example of a semiconductor device.
The semiconductor device 10I shown in FIG. 20 is an example of SBD. The semiconductor device 10I has a substrate 20 and a nucleation layer 21 provided on the substrate 20. For the substrate 20, for example, a semi-insulating SiC substrate is used. A nitride semiconductor, for example, AlN, is used for the nucleation layer 21. The channel layer 11 and the barrier layer 12 are provided on the nucleation layer 21 provided on the substrate 20. For example, GaN is used for the channel layer 11 and AlGaN is used for the barrier layer 12. On the barrier layer 12, a cap structure 14 having an InGaN cap layer 14a and a GaN cap layer 14b that protects the surface thereof, and a cathode electrode 18 (ohmic electrode) and an anode electrode 19 (Schottky electrode) are provided. The cap structure 14 is provided in a part of the barrier layer 12 between the cathode electrode 18 and the anode electrode 19 near the anode electrode 19. The cathode electrode 18 is provided on the barrier layer 12 so as to function as an ohmic electrode, and the anode electrode 19 is provided on the barrier layer 12 so as to function as a Schottky electrode. A passivation film 22 is provided on the barrier layer 12 provided with the cap structure 14, the cathode electrode 18, and the anode electrode 19.

In the semiconductor device 10I, the cap structure 14 is provided in a part of the region near the anode electrode 19 on the barrier layer 12, and the channel layer 11 below the region is provided by the action of the piezo polarization generated in the cap layer 14a of the InGaN. 2DEG13 is reduced in concentration. As a result, the electric field on the anode electrode 19 side when the reverse bias is applied is relaxed, and the semiconductor device 10I having a high reverse withstand voltage that functions as an SBD is realized. Further, in the semiconductor device 10I, a GaN cap layer 14b for protecting the InGaN cap layer 14a is provided on the InGaN cap layer 14a. As a result, a highly reliable semiconductor device 10I that functions as an SBD is realized.

The semiconductor device 10I having the above configuration can be formed by using the methods described with respect to FIGS. 10 and 16 to 18 in the fourth and fifth embodiments.
That is, first, according to the example of FIG. 10, the nucleation layer 21, the channel layer 11, the barrier layer 12, the cap layer 14a and the cap layer 14b are sequentially grown on the substrate 20 by using the MOVPE method. At this time, after the growth of the InGaN cap layer 14a, the GaN cap layer 14b is continuously grown to protect the InGaN with GaN.

Then, according to the example of FIG. 16, the InGaN cap layer 14a and the GaN cap layer 14b are patterned to form the cap structure 14.
Next, according to the example of FIG. 17, the electrode metal is formed on the barrier layer 12, and the cathode electrode 18 and the anode electrode 19 are formed. At that time, the cathode electrode 18 is formed on the barrier layer 12 so as to function as an ohmic electrode, and the anode electrode 19 is formed on the barrier layer 12 so as to function as a Schottky electrode. In the formation of the semiconductor device 10I, the formation may be performed in separate steps so that ohmic connection and shotkey connection are realized for the cathode electrode 18 and the anode electrode 19, respectively, and different types of electrode metals are formed. May be used.

Next, the passivation film 22 is formed on the barrier layer 12 on which the cap structure 14, the cathode electrode 18, and the anode electrode 19 are formed according to the example of FIG.
For example, such a method is used to form a semiconductor device 10I having a configuration as shown in FIG.

In the semiconductor device 10I as well, in addition to GaN, a nitride semiconductor such as InGaN, AlGaN, or InAlGaN may be used for the channel layer 11, or a single layer structure of one type of nitride semiconductor may be used. Alternatively, a laminated structure of one or more types of nitride semiconductors may be used. In addition to AlGaN, a nitride semiconductor such as InAlN, InAlGaN, or AlN may be used for the barrier layer 12, or a single-layer structure of one type of nitride semiconductor may be used, or one or two types. The above-mentioned laminated structure of nitride semiconductor may be used. Further, as the substrate 20, in addition to the semi-insulating SiC substrate, a conductive SiC substrate, a sapphire substrate, a GaN substrate, a Si substrate, a diamond substrate and the like may be used.

As described above, the semiconductor devices 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10I and the like having the configurations as described in the first to sixth embodiments can be applied to various electronic devices. .. As an example, a case where a semiconductor device having the above configuration is applied to a semiconductor package, a power factor improving circuit, a power supply device, and an amplifier will be described below.

[7th Embodiment]
Here, an example of application of the semiconductor device having the above configuration to a semiconductor package will be described as a seventh embodiment.

FIG. 21 is a diagram illustrating an example of a semiconductor package according to the seventh embodiment. FIG. 21 schematically shows a plan view of a main part of an example of a semiconductor package.
The semiconductor package 200 shown in FIG. 21 is an example of a discrete package. The semiconductor package 200 includes, for example, the semiconductor device 10A described in the first embodiment, the lead frame 210 on which the semiconductor device 10A is mounted, and the resin 220 that seals them.

The semiconductor device 10A is mounted on the die pad 210a of the lead frame 210 using a die attach material or the like (not shown). The semiconductor device 10A is provided with a pad 15a connected to the gate electrode 15, a pad 16a connected to the source electrode 16, and a pad 17a connected to the drain electrode 17. The pads 15a, 16a, and 17a are respectively connected to the gate lead 211, the source lead 212, and the drain lead 213 of the lead frame 210 by using a wire 230 such as Al. The lead frame 210, the semiconductor device 10A mounted therein, and the wire 230 connecting them are sealed with the resin 220 so that each part of the gate lead 211, the source lead 212, and the drain lead 213 is exposed.

For example, the semiconductor device 10A described in the first embodiment is used, and a semiconductor package 200 having such a configuration can be obtained. Here, the semiconductor device 10A is taken as an example, but it is possible to obtain a similarly high-performance semiconductor package by using other semiconductor devices 10B, 10C, 10D, 10E, 10G, 10H, etc. that function as HEMTs. ..

As described above, in the semiconductor devices 10A, 10B, 10C, 10D, 10E, 10G, 10H and the like, the InGaN cap layer 14a and the GaN cap layer 14b that protects the surface thereof are formed in a part of the region on the barrier layer 12. A cap structure 14 having the above is provided. Then, the concentration of 2DEG13 in the channel layer 11 below the cap structure 14 is reduced. By providing the cap structure 14 under the gate electrode 15, normalization of HEMT is realized. By providing the cap structure 14 between the gate electrode 15 and the drain electrode 17, a high withstand voltage of HEMT is realized. By protecting the InGaN cap layer 14a with the GaN cap layer 14b, a highly reliable HEMT is realized. Semiconductor devices 10A, 10B, 10C, 10D, 10E, 10G, 10H and the like having such excellent characteristics are used, and a high-performance semiconductor package 200 is realized.

Further, a discrete package can be obtained by using semiconductor devices 10F, 10I, etc. that function as SBDs. As described above, in the semiconductor devices 10F, 10I, etc., the cap structure 14 is provided in a part of the region between the cathode electrode 18 and the anode electrode 19 near the anode electrode 19, so that the SBD has a reverse pressure resistance. Improvements are realized. By protecting the InGaN cap layer 14a with the GaN cap layer 14b, highly reliable SBD is realized. Semiconductor devices 10F, 10I and the like having such excellent characteristics are used, and a high-performance semiconductor package is realized.

[Eighth Embodiment]
Here, an example of application of the semiconductor device having the above configuration to the power factor improving circuit will be described as the eighth embodiment.

FIG. 22 is a diagram illustrating an example of a power factor improving circuit according to the eighth embodiment. FIG. 22 shows an equivalent circuit diagram of an example of the power factor improving circuit.
The power factor correction (PFC) circuit 300 shown in FIG. 22 includes a switch element 310, a diode 320, a choke coil 330, a capacitor 340, a capacitor 350, a diode bridge 360, and an AC power supply 370 (AC).

In the PFC circuit 300, the drain electrode of the switch element 310, the anode terminal of the diode 320, and one terminal of the choke coil 330 are connected. The source electrode of the switch element 310 is connected to one terminal of the capacitor 340 and one terminal of the capacitor 350. The other terminal of the capacitor 340 and the other terminal of the choke coil 330 are connected. The other terminal of the capacitor 350 and the cathode terminal of the diode 320 are connected. A gate driver is connected to the gate electrode of the switch element 310. An AC power supply 370 is connected between both terminals of the capacitor 340 via a diode bridge 360, and a direct current power supply (DC) is taken out from both terminals of the capacitor 350.

For example, the semiconductor devices 10A, 10B, 10C, 10D, 10E, 10G, 10H and the like that function as HEMTs are used for the switch element 310 of the PFC circuit 300 having such a configuration.

As described above, in the semiconductor devices 10A, 10B, 10C, 10D, 10E, 10G, 10H and the like, the InGaN cap layer 14a and the GaN cap layer 14b that protects the surface thereof are formed in a part of the region on the barrier layer 12. A cap structure 14 having the above is provided. Then, the concentration of 2DEG13 in the channel layer 11 below the cap structure 14 is reduced. By providing the cap structure 14 under the gate electrode 15, normalization of HEMT is realized. By providing the cap structure 14 between the gate electrode 15 and the drain electrode 17, a high withstand voltage of HEMT is realized. By protecting the InGaN cap layer 14a with the GaN cap layer 14b, a highly reliable HEMT is realized. Semiconductor devices 10A, 10B, 10C, 10D, 10E, 10G, 10H and the like having such excellent characteristics are used, and a high-performance PFC circuit 300 is realized.

Further, the semiconductor devices 10F, 10I and the like that function as SBDs may be used for the diode 320 and the diode bridge 360 of the PFC circuit 300. As described above, in the semiconductor devices 10F, 10I, etc., the cap structure 14 is provided in a part of the region between the cathode electrode 18 and the anode electrode 19 near the anode electrode 19, so that the SBD has a reverse pressure resistance. Improvements are realized. By protecting the InGaN cap layer 14a with the GaN cap layer 14b, highly reliable SBD is realized. Semiconductor devices 10F, 10I and the like having such excellent characteristics are used, and a high-performance PFC circuit 300 is realized.

[9th Embodiment]
Here, an example of application of the semiconductor device having the above configuration to the power supply device will be described as a ninth embodiment.

FIG. 23 is a diagram illustrating an example of the power supply device according to the ninth embodiment. FIG. 23 shows an equivalent circuit diagram of an example of the power supply device.
The power supply device 400 shown in FIG. 23 includes a high-voltage primary circuit 410, a low-voltage secondary circuit 420, and a transformer 430 provided between the primary circuit 410 and the secondary circuit 420.

The primary side circuit 410 includes an inverter circuit connected between both terminals of the PFC circuit 300 and the capacitor 350 of the PFC circuit 300 as described in the eighth embodiment, for example, a full bridge inverter circuit 440. Is done. The full bridge inverter circuit 440 includes a plurality of (four as an example here) switch element 441, switch element 442, switch element 443, and switch element 444.

The secondary circuit 420 includes a plurality of (three as an example here) switch elements 421, switch elements 422, and switch elements 423.
For example, the semiconductor device 10A that functions as HEMT in the switch element 310 of the PFC circuit 300 included in the primary side circuit 410 and the switch elements 441 to 444 of the full bridge inverter circuit 440 of the power supply device 400 having such a configuration. , 10B, 10C, 10D, 10E, 10G, 10H and the like are used. For example, a normal MIS (Metal Insulator Semiconductor) type field effect transistor using silicon is used for the switch elements 421 to 423 of the secondary circuit 420 of the power supply device 400.

As described above, in the semiconductor devices 10A, 10B, 10C, 10D, 10E, 10G, 10H and the like, the InGaN cap layer 14a and the GaN cap layer 14b that protects the surface thereof are formed in a part of the region on the barrier layer 12. A cap structure 14 having the above is provided. Then, the concentration of 2DEG13 in the channel layer 11 below the cap structure 14 is reduced. By providing the cap structure 14 under the gate electrode 15, normalization of HEMT is realized. By providing the cap structure 14 between the gate electrode 15 and the drain electrode 17, a high withstand voltage of HEMT is realized. By protecting the InGaN cap layer 14a with the GaN cap layer 14b, a highly reliable HEMT is realized. Semiconductor devices 10A, 10B, 10C, 10D, 10E, 10G, 10H and the like having such excellent characteristics are used, and a high-performance power supply device 400 is realized.

Further, as the diode 320 and the diode bridge 360 of the PFC circuit 300 included in the primary side circuit 410, as described in the eighth embodiment, the semiconductor devices 10F, 10I and the like functioning as SBDs are used. May be good. Semiconductor devices 10F, 10I and the like having excellent characteristics are used to realize a high-performance PFC circuit 300, and such a PFC circuit 300 is used to realize a high-performance power supply device 400.

[10th Embodiment]
Here, an example of application of the semiconductor device having the above configuration to an amplifier will be described as a tenth embodiment.

FIG. 24 is a diagram illustrating an example of an amplifier according to the tenth embodiment. FIG. 24 shows an equivalent circuit diagram of an example of an amplifier.
The amplifier 500 shown in FIG. 24 includes a digital pre-distortion circuit 510, a mixer 520, a mixer 530, and a power amplifier 540.

The digital predistortion circuit 510 compensates for the non-linear distortion of the input signal. The mixer 520 mixes the input signal SI and the AC signal in which the non-linear distortion is compensated. The power amplifier 540 amplifies the signal in which the input signal SI is mixed with the AC signal. In the amplifier 500, for example, the output signal SO can be mixed with the AC signal by the mixer 530 and transmitted to the digital predistortion circuit 510 by switching the switch. The amplifier 500 can be used as a high frequency amplifier or a high output amplifier.

The semiconductor devices 10A, 10B, 10C, 10D, 10E, 10G, 10H and the like that function as HEMTs are used as the power amplifier 540 of the amplifier 500 having such a configuration.

As described above, in the semiconductor devices 10A, 10B, 10C, 10D, 10E, 10G, 10H and the like, the InGaN cap layer 14a and the GaN cap layer 14b that protects the surface thereof are formed in a part of the region on the barrier layer 12. A cap structure 14 having the above is provided. Then, the concentration of 2DEG13 in the channel layer 11 below the cap structure 14 is reduced. By providing the cap structure 14 under the gate electrode 15, normalization of HEMT is realized. By providing the cap structure 14 between the gate electrode 15 and the drain electrode 17, a high withstand voltage of HEMT is realized. By protecting the InGaN cap layer 14a with the GaN cap layer 14b, a highly reliable HEMT is realized. Semiconductor devices 10A, 10B, 10C, 10D, 10E, 10G, 10H and the like having such excellent characteristics are used, and a high-performance amplifier 500 is realized.

When a diode is used for the amplifier 500, an SBD such as a semiconductor device 10F or 10I may be used for the diode. As described above, in the semiconductor devices 10F, 10I, etc., the cap structure 14 is provided in a part of the region between the cathode electrode 18 and the anode electrode 19 near the anode electrode 19, so that the SBD has a reverse pressure resistance. Improvements are realized. By protecting the InGaN cap layer 14a with the GaN cap layer 14b, highly reliable SBD is realized. Semiconductor devices 10F, 10I and the like having such excellent characteristics are used, and a high-performance amplifier 500 is realized.

Various electronic devices to which the semiconductor devices 10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10I, etc. are applied (semiconductor package 200, PFC circuit 300, power supply described in the seventh to tenth embodiments above). The device 400, the amplifier 500, etc.) can be mounted on various electronic devices. For example, it can be installed in various electronic devices such as computers (personal computers, supercomputers, servers, etc.), smartphones, mobile phones, tablet terminals, sensors, cameras, audio devices, measuring devices, inspection devices, manufacturing devices, etc. ..

10A, 10B, 10C, 10D, 10E, 10F, 10G, 10H, 10I, 100A, 100B Semiconductor device 11,101 Channel layer 12,102 Barrier layer 12c, 14c Top surface 13,103 2DEG
14 Cap structure 14a, 14b, 104A, 104B Cap layer 15,105 Gate electrode 15a, 16a, 17a Pad 16,106 Source electrode 17,107 Drain electrode 18 Cathode electrode 19 Anopole electrode 20 Substrate 21 Nucleation layer 22 Passion film 200 Semiconductor Package 210 Lead frame 210a Die pad 211 Gate lead 212 Source lead 213 Drain lead 220 Resin 230 Wire 300 PFC circuit 310,421,422,423,441,442,443,444 Switch element 320 Diode 330 Choke coil 340,350 Condenser 360 Diode Bridge 370 AC power supply 400 Power supply unit 410 Primary side circuit 420 Secondary side circuit 430 Transformer 440 Full bridge Inverter circuit 500 Amplifier 510 Digital predistortion circuit 520, 530 Mixer 540 Power amplifier

Claims (11)

A channel layer containing a first nitride semiconductor and
A barrier layer provided on the channel layer and containing a second nitride semiconductor,
Including a cap structure provided in the first region on the barrier layer
The cap structure
The first layer containing In _x Ga _1-x N (0 <x <1) and
A semiconductor device provided on the first layer and having a second layer containing GaN. Two-dimensional electron gas is generated in the vicinity of the interface between the channel layer and the barrier layer.
The semiconductor device according to claim 1, wherein the first layer of the cap structure provided on the barrier layer has a compressive strain. A higher concentration of two-dimensional electron gas is generated in the channel layer below the second region different from the first region on the barrier layer than in the channel layer below the first region. The semiconductor device according to claim 1 or 2. A gate electrode provided on the second layer of the cap structure and
The semiconductor device according to any one of claims 1 to 3, further comprising a source electrode and a drain electrode provided on the barrier layer on both sides of the gate electrode. The gate electrode provided on the barrier layer and
The source electrode and the drain electrode provided on the barrier layer on both sides of the gate electrode are included.
The semiconductor device according to any one of claims 1 to 3, wherein the first region provided with the cap structure is a region on the barrier layer between the gate electrode and the drain electrode. Including an ohmic electrode and a Schottky electrode provided on the barrier layer,
The first region in which the cap structure is provided is a region on the barrier layer between the ohmic electrode and the Schottky electrode, which is closer to the Schottky electrode, according to claims 1 to 3. The semiconductor device according to any one. The semiconductor device according to any one of claims 1 to 6, wherein the first layer has a film thickness of 2 nm or less. The semiconductor device according to any one of claims 1 to 7, wherein the first layer has an In composition x of 0.20 or less. The semiconductor device according to any one of claims 1 to 8, wherein the second layer has a film thickness of 2 nm or more. A step of forming a barrier layer containing a second nitride semiconductor on a channel layer containing a first nitride semiconductor, and a step of forming a barrier layer containing the second nitride semiconductor.
The first region on the barrier layer includes a step of forming a cap structure.
The step of forming the cap structure is
A step of forming a first layer containing In _x Ga _1-x N (0 <x <1) and
A method for manufacturing a semiconductor device, which comprises a step of forming a second layer containing GaN on the first layer. A channel layer containing a first nitride semiconductor and
A barrier layer provided on the channel layer and containing a second nitride semiconductor,
Including a cap structure provided in the first region on the barrier layer
The cap structure
The first layer containing In _x Ga _1-x N (0 <x <1) and
An electronic device provided on the first layer and including a semiconductor device having a second layer containing GaN.

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