JP2008218813A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2008218813A
JP2008218813A JP2007055918A JP2007055918A JP2008218813A JP 2008218813 A JP2008218813 A JP 2008218813A JP 2007055918 A JP2007055918 A JP 2007055918A JP 2007055918 A JP2007055918 A JP 2007055918A JP 2008218813 A JP2008218813 A JP 2008218813A
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semiconductor
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nitride semiconductor
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JP5134265B2 (en
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Kenji Ito
Masahiro Sugimoto
Tsutomu Uesugi
勉 上杉
健治 伊藤
雅裕 杉本
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Toyota Central R&D Labs Inc
Toyota Motor Corp
トヨタ自動車株式会社
株式会社豊田中央研究所
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/778Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7788Vertical transistors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66446Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623Buried supplementary region, e.g. buried guard ring
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003Nitride compounds

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for actualizing stable normally-off operation for a semiconductor device using a heterojunction surface for a channel. <P>SOLUTION: The semiconductor device has a nitride semiconductor crystal and a gate electrode opposed to a top surface of the nitride semiconductor crystal with an insulating layer interposed. The nitride semiconductor crystal has a first layer made of a nitride semiconductor of first kind and a second layer laminated on the first layer and made of a nitride semiconductor of second kind. A p-type semiconductor region containing p-typ impurities is formed in at least part of the first layer. A heterojunction surface formed on the boundary surface between the first layer and second layer is disposed on a crystal surface perpendicular to a (0001) crystal surface. Then the gate electrode is opposed to at least part of the heterojunction surface from above and the p-type semiconductor region is opposed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、窒化物半導体結晶を用いた半導体装置に関する。   The present invention relates to a semiconductor device using a nitride semiconductor crystal.

特許文献1に、窒化物半導体結晶を用いた半導体装置が開示されている。この半導体装置は、窒化物半導体結晶と、その窒化物半導体結晶の上側表面に絶縁層を介して対向するゲート電極を有している。窒化物半導体結晶は、第1種類の窒化物半導体(窒化ガリウム)で構成された第1層と、第1層の上側に積層されているとともに第2種類の窒化物半導体(窒化ガリウム・アルミニウム)で構成された第2層を有している。第1層と第2層はバンドギャップが互いに異なることから、両者の境界面はヘテロ接合面となっている。第1層と第2層とのヘテロ接合面の一部には、ゲート電極が一方側から対向している。特許文献1の半導体装置は、ヘテロ接合面をチャネルに用いる横型の電界効果トランジスタであり、いわゆるヘテロ接合電界効果トランジスタと称されるものである。   Patent Document 1 discloses a semiconductor device using a nitride semiconductor crystal. This semiconductor device has a nitride semiconductor crystal and a gate electrode facing the upper surface of the nitride semiconductor crystal via an insulating layer. The nitride semiconductor crystal includes a first layer composed of a first type nitride semiconductor (gallium nitride) and a second type nitride semiconductor (gallium nitride / aluminum) laminated on the upper side of the first layer. It has the 2nd layer comprised by these. Since the first layer and the second layer have different band gaps, the interface between them is a heterojunction surface. A gate electrode is opposed to a part of the heterojunction surface between the first layer and the second layer from one side. The semiconductor device of Patent Document 1 is a lateral field effect transistor that uses a heterojunction plane as a channel, and is called a so-called heterojunction field effect transistor.

ヘテロ接合電界効果トランジスタでは、チャネルとなるヘテロ接合面を(0001)結晶面上に形成すると、自発分極及びピエゾ分極に起因する内部電界の発生によって、ヘテロ接合面に高密度の2次元電子ガス層が形成される。ヘテロ接合面に高密度の2次元電子ガス層が形成されると、ゲート電極に電圧を印加していない時でも、ヘテロ接合面は多数の電子が走行可能な状態となる。従って、チャネルとなるヘテロ接合面を(0001)結晶面上に形成した半導体装置は、ノーマリオン型の挙動を示すこととなる。
それに対して、特許文献1の半導体装置では、チャネルとなるヘテロ接合面を(11−20)結晶面上に形成している。 On the other hand, in the semiconductor device of Patent Document 1, a heterojunction surface serving as a channel is formed on the (11-20) crystal plane. (11−20)結晶面は、厚み方向に極性が変化しない無極性面である。 The (11-20) crystal plane is a non-polar plane whose polarity does not change in the thickness direction. そのことから、(11−20)結晶面上に形成したヘテロ接合面では、自発分極及びピエゾ分極が発生せず、2次元電子ガス層の密度は比較的に低くなる。 Therefore, spontaneous polarization and piezo polarization do not occur in the heterojunction plane formed on the (11-20) crystal plane, and the density of the two-dimensional electron gas layer is relatively low. その結果、ゲート電極に電圧を印加しない状態では、ヘテロ接合面における電子の走行が抑制される。 As a result, when no voltage is applied to the gate electrode, the traveling of electrons on the heterojunction surface is suppressed. 特許文献1によれば、しきい値電圧は−0.4Vに上昇し、ほぼノーマリオフ型の動作特性を得ることができるという。 According to Patent Document 1, the threshold voltage rises to -0.4V, and almost normal-off type operating characteristics can be obtained. In a heterojunction field effect transistor, when a heterojunction plane serving as a channel is formed on a (0001) crystal plane, a high-density two-dimensional electron gas layer is formed on the heterojunction plane due to the generation of an internal electric field due to spontaneous polarization and piezoelectric polarization. Is formed. When a high-density two-dimensional electron gas layer is formed on the heterojunction surface, even when no voltage is applied to the gate electrode, the heterojunction surface is in a state where a large number of electrons can travel. Therefore, a semiconductor device in which a heterojunction plane serving as a channel is formed on a (0001) crystal plane exhibits normally-on behavior. In a heterojunction field effect transistor, when a heterojunction plane serving as a channel is formed on a (0001) crystal plane, a high-density two-dimensional electron gas layer is formed on the heterojunction plane due to the generation of an internal electric field Due to spontaneous polarization and piezoelectric polarization. Is formed. When a high-density two-dimensional electron gas layer is formed on the heterojunction surface, even when no voltage is applied to the gate electrode, the heterojunction surface is in a state where a large number of electrons can travel. Therefore, a country device in which a heterojunction plane serving as a channel is formed on a (0001) crystal plane exhibits normally-on behavior.
On the other hand, in the semiconductor device of Patent Document 1, a heterojunction surface to be a channel is formed on the (11-20) crystal plane. The (11-20) crystal plane is a nonpolar plane whose polarity does not change in the thickness direction. Therefore, spontaneous polarization and piezoelectric polarization do not occur at the heterojunction plane formed on the (11-20) crystal plane, and the density of the two-dimensional electron gas layer is relatively low. As a result, in the state where no voltage is applied to the gate electrode, the traveling of electrons on the heterojunction surface is suppressed. According to Patent Document 1, the threshold voltage rises to −0.4 V, and almost normally-off operation characteristics can be obtained. On the other hand, in the semiconductor device of Patent Document 1, a heterojunction surface to be a channel is formed on the (11-20) crystal plane. The (11-20) crystal plane is a nonpolar plane whose polarity does not change in the thickness direction. Therefore, spontaneous polarization and piezoelectric polarization do not occur at the heterojunction plane formed on the (11-20) crystal plane, and the density of the two-dimensional electron gas layer is relatively low. As a result, in The state where no voltage is applied to the gate electrode, the traveling of electrons on the heterojunction surface is suppressed. According to Patent Document 1, the threshold voltage rises to −0.4 V, and almost normally-off operation characteristics can be obtained.

ここで、(11−20)という表記の「2」の前に付された「−」は、一般に「2」の上部に付すべき「バー」を示すものである。本願の明細書及び特許請求の範囲では、結晶面や結晶軸の表記を同様に行う。また、特に言及しない限り、例えば(10−10)結晶面という表記は、(10−10)結晶面とそれに等価な結晶面を含むものとする。同様に、例えば<10−10>結晶軸という表記は、<10−10>結晶軸とそれに等価な結晶軸を含むものとする。   Here, “-” added before “2” in the notation of (11-20) generally indicates “bar” to be added to the upper part of “2”. In the specification and claims of the present application, the crystal plane and the crystal axis are indicated in the same manner. Unless otherwise specified, for example, the notation (10-10) crystal plane includes a (10-10) crystal plane and an equivalent crystal plane. Similarly, for example, the expression <10-10> crystal axis includes a <10-10> crystal axis and an equivalent crystal axis.

特開2006−324465号公報JP 2006-324465 A

特許文献1の半導体装置は、しきい値電圧が依然として負の値のままであり、安定したノーマリオフ動作を実現するには不十分といえる。安定したノーマリオフ動作を実現するためには、ゲート電極に電圧を印加しない状態で、ヘテロ接合面における電子の走行をより強く禁止する必要がある。
本発明は、上記の課題を解決する。 The present invention solves the above problems. 本発明は、ヘテロ接合面をチャネルに用いる半導体装置において、安定したノーマリオフ動作を可能とする技術を提供する。 The present invention provides a technique that enables stable normal-off operation in a semiconductor device that uses a heterojunction surface as a channel. The semiconductor device of Patent Document 1 still has a negative threshold voltage, which is insufficient for realizing a stable normally-off operation. In order to realize a stable normally-off operation, it is necessary to more strongly inhibit the traveling of electrons on the heterojunction surface without applying a voltage to the gate electrode. The semiconductor device of Patent Document 1 still has a negative threshold voltage, which is insufficient for realizing a stable normally-off operation. In order to realize a stable normally-off operation, it is necessary to more strongly inhibit the traveling of electrons on the heterojunction surface without applying a voltage to the gate electrode.
The present invention solves the above problems. The present invention provides a technique that enables a stable normally-off operation in a semiconductor device using a heterojunction plane as a channel. The present invention solves the above problems. The present invention provides a technique that enables a stable normally-off operation in a semiconductor device using a heterojunction plane as a channel.

本発明によって具現化される半導体装置は、窒化物半導体結晶と、前記窒化物半導体結晶の上側表面に絶縁層を介して対向するゲート電極を備えている。前記窒化物半導体結晶は、第1種類の窒化物半導体で構成された第1層と、前記第1層の上方に積層されているとともに第2種類の窒化物半導体で構成された第2層を備えている。前記第1層の少なくとも一部には、p型の不純物を含むp型半導体領域が形成されている。前記第1層と前記第2層との境界面に形成されたヘテロ接合面は、(0001)結晶面に垂直な結晶面上に位置している。そして、前記へテロ接合面の少なくとも一部には、前記ゲート電極が上方から対向しているとともに、前記p型半導体領域が下方から対向している。
ここで、窒化物半導体結晶の上側表面とは、鉛直上方に位置する表面を意図するものではなく、半導体装置の各構成の位置関係を明確にするために便宜上定めるものである。 Here, the upper surface of the nitride semiconductor crystal is not intended to be a surface located vertically above, but is defined for convenience in order to clarify the positional relationship of each configuration of the semiconductor device. 本明細書および特許請求の範囲では、窒化物半導体結晶の複数の表面のうち、ゲート電極が配設された表面を上側表面と定め、上側表面に対向する表面を下側表面と定める。 In the present specification and claims, among a plurality of surfaces of a nitride semiconductor crystal, the surface on which the gate electrode is arranged is defined as the upper surface, and the surface facing the upper surface is defined as the lower surface. そして、下側表面から上側表面に向かう方向を上方と表現し、上側表面から下側表面に向かう方向を下方と表現し、上側表面及び下側表面に平行な方向を側方と表現する。 The direction from the lower surface to the upper surface is expressed as upward, the direction from the upper surface to the lower surface is expressed as lower, and the direction parallel to the upper surface and the lower surface is expressed as lateral. A semiconductor device embodied by the present invention includes a nitride semiconductor crystal and a gate electrode facing the upper surface of the nitride semiconductor crystal via an insulating layer. The nitride semiconductor crystal includes a first layer composed of a first type of nitride semiconductor and a second layer composed of a second type of nitride semiconductor and stacked above the first layer. I have. A p-type semiconductor region containing a p-type impurity is formed in at least a part of the first layer. The heterojunction plane formed at the interface between the first layer and the second layer is located on a crystal plane perpendicular to the (0001) crystal plane. The gate electrode is opposed to at least a part of the heterojunction surface from above, and the p-type semiconductor region is opposed from below. A semiconductor device embodied by the present invention includes a nitride semiconductor crystal and a gate electrode facing the upper surface of the nitride semiconductor crystal via an insulating layer. The nitride semiconductor crystal includes a first layer composed of a first type of nitride semiconductor and a second Layer composed of a second type of nitride semiconductor and stacked above the first layer. I have. A p-type semiconductor region containing a p-type impurity is formed in at least a part of the first layer. The heterojunction plane formed at the interface between the first layer and the second layer is located on a crystal plane perpendicular to the (0001) crystal plane. The gate electrode is opposed to at least a part of the heterojunction surface from above, and the p-type semiconductor region is opposed from below.
Here, the upper surface of the nitride semiconductor crystal is not intended to be a surface positioned vertically upward, but is defined for the sake of convenience in order to clarify the positional relationship of each component of the semiconductor device. In the present specification and claims, of the plurality of surfaces of the nitride semiconductor crystal, the surface on which the gate electrode is disposed is defined as the upper surface, and the surface facing the upper surface is defined as the lower surface. A direction from the lower surface to the upper surface is expressed as upward, a direction from the upper surface to the lower surface is expressed as downward, and a direction parallel to the upper surface and the lower surface is expressed as side. Here, the upper surface of the nitride semiconductor crystal is not intended to be a surface positioned vertically upward, but is defined for the sake of convenience in order to clarify the positional relationship of each component of the semiconductor device. In the present specification and claims A direction from the lower surface to the, of the plurality of surfaces of the nitride semiconductor crystal, the surface on which the gate electrode is disposed is defined as the upper surface, and the surface facing the upper surface is defined as the lower surface. upper surface is expressed as upward, a direction from the upper surface to the lower surface is expressed as downward, and a direction parallel to the upper surface and the lower surface is expressed as side.

この半導体装置では、チャネルとなるヘテロ接合面が、(0001)結晶面に垂直な結晶面上に形成されている。(0001)結晶面に垂直な結晶面は、厚み方向に極性が変化しない無極性面である。そのことから、(0001)結晶面に垂直な結晶面上に形成されたヘテロ接合面では、ヘテロ接合面に垂直な自発分極及びピエゾ分極は発生せず、2次元電子ガス層の密度は比較的に低くなる。
上記に加えて、この半導体装置では、p型の不純物を含むp型半導体領域が、チャネルとなるヘテロ接合面に対向している。それにより、ゲート電極に電圧を印加していない状態では、p型半導体領域から伸びる空乏層が、ヘテロ接合面における2次元電子ガス層の形成を抑制する。
以上により、ゲート電極に電圧を印加していない状態では、ヘテロ接合面における2次元電子ガス層の形成が十分に抑制され、ヘテロ接合面における電子の走行を禁止することができる。 As described above, when no voltage is applied to the gate electrode, the formation of the two-dimensional electron gas layer on the heterojunction surface is sufficiently suppressed, and the traveling of electrons on the heterojunction surface can be prohibited. この半導体装置は、安定したノーマリオフ動作が可能である。 This semiconductor device is capable of stable normal-off operation. In this semiconductor device, a heterojunction plane that becomes a channel is formed on a crystal plane perpendicular to the (0001) crystal plane. The crystal plane perpendicular to the (0001) crystal plane is a nonpolar plane whose polarity does not change in the thickness direction. Therefore, in the heterojunction plane formed on the crystal plane perpendicular to the (0001) crystal plane, spontaneous polarization and piezopolarization perpendicular to the heterojunction plane do not occur, and the density of the two-dimensional electron gas layer is relatively low. It becomes low. In this semiconductor device, a heterojunction plane that becomes a channel is formed on a crystal plane perpendicular to the (0001) crystal plane. The crystal plane perpendicular to the (0001) crystal plane is a nonpolar plane whose polarity does not change in the thickness. direction. Therefore, in the heterojunction plane formed on the crystal plane perpendicular to the (0001) crystal plane, spontaneous polarization and piezopolarization perpendicular to the heterojunction plane do not occur, and the density of the two-dimensional electron gas layer is relatively low. It becomes low.
In addition to the above, in this semiconductor device, a p-type semiconductor region containing a p-type impurity is opposed to a heterojunction surface serving as a channel. Thereby, when no voltage is applied to the gate electrode, the depletion layer extending from the p-type semiconductor region suppresses the formation of the two-dimensional electron gas layer at the heterojunction surface. In addition to the above, in this semiconductor device, a p-type semiconductor region containing a p-type impurities is opposed to a heterojunction surface serving as a channel. Accordingly, when no voltage is applied to the gate electrode, the depletion layer extending from the p-type semiconductor region suppresses the formation of the two-dimensional electron gas layer at the heterojunction surface.
As described above, in the state where no voltage is applied to the gate electrode, the formation of the two-dimensional electron gas layer on the heterojunction surface is sufficiently suppressed, and the traveling of electrons on the heterojunction surface can be prohibited. This semiconductor device can perform a stable normally-off operation. As described above, in the state where no voltage is applied to the gate electrode, the formation of the two-dimensional electron gas layer on the heterojunction surface is sufficiently suppressed, and the traveling of electrons on the heterojunction surface can be prohibited. This semiconductor device can perform a stable normally-off operation.

上記の半導体装置では、前記p型半導体領域が、前記へテロ接合面から所定距離だけ離れた位置に形成されていることが好ましい。
それにより、p型半導体領域とへテロ接合面との距離を適宜設定することによって、しきい値電圧を所望の値に設定した半導体装置を容易に具現化することが可能となる。
In the above semiconductor device, it is preferable that the p-type semiconductor region is formed at a position separated from the heterojunction surface by a predetermined distance.
Thus, by appropriately setting the distance between the p-type semiconductor region and the heterojunction surface, a semiconductor device in which the threshold voltage is set to a desired value can be easily realized.

上記の半導体装置では、前記へテロ接合面と前記p型半導体領域との間に、n型の不純物を含むn型半導体領域が形成されていることが好ましい。
それにより、そのn型半導体領域の不純物濃度を適宜設定することによって、しきい値電圧を所望の値に設定した半導体装置を容易に具現化することが可能となる。
In the above semiconductor device, an n-type semiconductor region containing an n-type impurity is preferably formed between the heterojunction surface and the p-type semiconductor region.
Thereby, by appropriately setting the impurity concentration of the n-type semiconductor region, it is possible to easily embody a semiconductor device in which the threshold voltage is set to a desired value.

上記の半導体装置に、窒化物半導体結晶の上側表面に形成されているソース電極と、窒化物半導体結晶の下側表面に形成されているコレクタ電極を付加することによって、縦型の半導体装置を具現化することができる。この場合、前記p型半導体領域は、前記ゲート電極の一部に前記ヘテロ接合面を介して対向していることが好ましい。そして、前記ゲート電極の他の一部の下方には、前記ヘテロ接合面から前記p型半導体領域の側方を通過して前記窒化物半導体結晶の下側表面に到る領域に、n型の不純物を含むn型半導体領域が形成されていることが好ましい。
それにより、平面型の半導体装置に比して、優れたオフ耐圧及びオン抵抗を有する半導体装置を具現化することができる。 As a result, it is possible to embody a semiconductor device having excellent off-voltage and on-resistance as compared with a planar semiconductor device. A vertical semiconductor device is realized by adding a source electrode formed on the upper surface of the nitride semiconductor crystal and a collector electrode formed on the lower surface of the nitride semiconductor crystal to the above semiconductor device. Can be In this case, it is preferable that the p-type semiconductor region is opposed to a part of the gate electrode through the heterojunction surface. Under the other part of the gate electrode, an n-type region extends from the heterojunction surface to a region that passes from the side of the p-type semiconductor region to the lower surface of the nitride semiconductor crystal. An n-type semiconductor region containing impurities is preferably formed. A vertical semiconductor device is realized by adding a source electrode formed on the upper surface of the nitride semiconductor crystal and a collector electrode formed on the lower surface of the nitride semiconductor crystal to the above semiconductor device. Can be In this case, it is preferred. That the p-type semiconductor region is opposed to a part of the gate electrode through the heterojunction surface. Under the other part of the gate electrode, an n-type region extends from the heterojunction surface to a region that passes from the side of the p-type semiconductor region to the lower surface of the nitride semiconductor crystal. Ann-type semiconductor region containing impurities is preferably formed.
Thereby, a semiconductor device having an excellent off breakdown voltage and on resistance as compared with a planar semiconductor device can be realized. Thus, a semiconductor device having an excellent off breakdown voltage and on resistance as compared with a planar semiconductor device can be realized.

上記した縦型の半導体装置では、前記p型半導体領域と前記n型半導体領域が側方から互いに隣接する境界面の大部分が、(0001)結晶面と角度を成す結晶面上に位置していることが好ましい。ここで、大部分とは全体の半分を超える部分を意味する。
この特徴を具備する半導体装置は、結晶成長を利用して製造する際に、均質な結晶を成長させることができる。 A semiconductor device having this feature can grow a homogeneous crystal when it is manufactured by utilizing crystal growth. その結果、この特徴を具備する半導体装置は、均質な窒化物半導体結晶で構成することが容易であり、安定したノーマリオフ動作を実現することができる。 As a result, the semiconductor device having this feature can be easily composed of a homogeneous nitride semiconductor crystal, and a stable normal-off operation can be realized. In the above vertical semiconductor device, most of the boundary surface where the p-type semiconductor region and the n-type semiconductor region are adjacent to each other from the side is located on the crystal plane forming an angle with the (0001) crystal plane. Preferably it is. Here, the majority means more than half of the whole. In the above vertical semiconductor device, most of the boundary surface where the p-type semiconductor region and the n-type semiconductor region are adjacent to each other from the side is located on the crystal plane forming an angle with the (0001) crystal plane Here, the majority means more than half of the whole.
A semiconductor device having this feature can grow a homogeneous crystal when manufactured using crystal growth. As a result, a semiconductor device having this feature can be easily formed of a homogeneous nitride semiconductor crystal, and a stable normally-off operation can be realized. A semiconductor device having this feature can grow a homogeneous crystal when manufactured using crystal growth. As a result, a semiconductor device having this feature can be easily formed of a homogeneous nitride semiconductor crystal, and a stable normally-off operation can be realized.

さらに、前記p型半導体領域と前記n型半導体領域が側方から互いに隣接する境界面の大部分は、(0001)結晶面に垂直な結晶面上に位置していることが好ましい。
この特徴を具備する半導体装置は、結晶成長を利用して製造する際に、より均質な結晶を容易に成長させることができる。 A semiconductor device having this feature can easily grow a more homogeneous crystal when it is manufactured by utilizing crystal growth. その結果、この特徴を具備する半導体装置は、より安定したノーマリオフ動作を実現することができる。 As a result, the semiconductor device having this feature can realize a more stable normal-off operation. Furthermore, it is preferable that most of the boundary surface where the p-type semiconductor region and the n-type semiconductor region are adjacent to each other from the side is located on a crystal plane perpendicular to the (0001) crystal plane. Furthermore, it is preferred that most of the boundary surface where the p-type semiconductor region and the n-type semiconductor region are adjacent to each other from the side is located on a crystal plane perpendicular to the (0001) crystal plane.
A semiconductor device having this feature can easily grow a more homogeneous crystal when manufactured using crystal growth. As a result, a semiconductor device having this feature can realize a more stable normally-off operation. A semiconductor device having this feature can easily grow a more homogeneous crystal when manufactured using crystal growth. As a result, a semiconductor device having this feature can realize a more stable normally-off operation.

本発明の技術は、新規で有用な半導体装置の製造方法を提供する。この製造方法は、主材料が第1種類の窒化物半導体であり、表面が(0001)結晶面に垂直な結晶面であり、少なくとも一部にp型の不純物を含むp型半導体領域が形成されている窒化物半導体結晶を用意する工程と、前記窒化物半導体結晶の表面に、(0001)結晶面と角度を成す方向に伸びるトレンチを、前記p型半導体領域を貫通する深さで形成するトレンチ形成工程と、少なくとも前記トレンチの内部に、第1種類の窒化物半導体を結晶成長させる第1結晶成長工程と、第1結晶成長工程後の窒化物半導体結晶の表面に、第2種類の窒化物半導体を結晶成長させる第2結晶成長工程と、第2結晶成長工程後の窒化物半導体結晶の表面にゲート絶縁膜を介して対向するゲート電極を、前記p型半導体領域の少なくとも一部と対向する範囲に形成するゲート電極形成工程を備える。   The technology of the present invention provides a novel and useful method for manufacturing a semiconductor device. In this manufacturing method, a main material is a first type nitride semiconductor, a surface is a crystal plane perpendicular to the (0001) crystal plane, and a p-type semiconductor region containing a p-type impurity is formed at least partially. A step of preparing a nitride semiconductor crystal, and a trench formed at a depth penetrating the p-type semiconductor region on the surface of the nitride semiconductor crystal and extending in a direction that forms an angle with a (0001) crystal plane A first crystal growth step for crystal growth of a first type nitride semiconductor at least inside the trench; and a second type nitride on the surface of the nitride semiconductor crystal after the first crystal growth step. A second crystal growth step for crystal growth of the semiconductor, and a gate electrode facing the surface of the nitride semiconductor crystal after the second crystal growth step via a gate insulating film faces at least a part of the p-type semiconductor region A gate electrode forming step of forming a range.

この製造方法は、先に説明した縦型の半導体装置を好適に製造することができる。この製造方法では、(0001)結晶面に垂直な結晶面である窒化物半導体結晶の表面に、(0001)結晶面と角度を成す方向に伸びるトレンチを形成する。それにより、トレンチの長手方向に伸びる一対の側面は、(0001)結晶面と角度を成す結晶面となり、III族元素の原子と窒素原子が混在する結晶面となる。従って、後の結晶成長において、一対の側面のそれぞれから結晶成長が略等しい速度で進行し、トレンチの内部に均質な結晶を形成することができる。
それに対して、例えば(0001)結晶面と平行に伸びるトレンチを形成すると、トレンチの長手方向に伸びる一対の側面は(0001)結晶面となる。 On the other hand, for example, when a trench extending parallel to the (0001) crystal plane is formed, the pair of side surfaces extending in the longitudinal direction of the trench becomes the (0001) crystal plane. この場合、一方の側面はIII族元素の原子のみが存在する(0001)結晶面となり、他方の側面は窒素原子のみが存在する(0001)結晶面となる。 In this case, one side surface is a (0001) crystal plane in which only group III element atoms are present, and the other side surface is a (0001) crystal plane in which only nitrogen atoms are present. III元素の原子のみが存在する(0001)結晶面からの結晶成長は、窒素原子のみが存在する(0001)結晶面からの結晶成長よりも、その進行速度が顕著に遅くなる。 The crystal growth from the (0001) crystal plane in which only the atom of element III is present is significantly slower than the crystal growth from the (0001) crystal plane in which only the nitrogen atom is present. その結果、トレンチの内部に均質な結晶を形成することが困難となる。 As a result, it becomes difficult to form homogeneous crystals inside the trench.
本発明に係る製造方法によれば、トレンチの内部に均質な結晶を形成し、安定したノーマリオフ動作を実現する半導体装置を製造することが可能となる。 According to the manufacturing method according to the present invention, it is possible to manufacture a semiconductor device that forms homogeneous crystals inside the trench and realizes a stable normalization operation. This manufacturing method can preferably manufacture the vertical semiconductor device described above. In this manufacturing method, a trench extending in a direction that forms an angle with the (0001) crystal plane is formed on the surface of the nitride semiconductor crystal that is a crystal plane perpendicular to the (0001) crystal plane. As a result, the pair of side surfaces extending in the longitudinal direction of the trench become a crystal plane that forms an angle with the (0001) crystal plane, and becomes a crystal plane in which atoms of group III elements and nitrogen atoms are mixed. Therefore, in the subsequent crystal growth, the crystal growth proceeds from each of the pair of side surfaces at substantially the same speed, and a homogeneous crystal can be formed inside the trench. This manufacturing method can preferably manufacture the vertical semiconductor device described above. In this manufacturing method, a trench extending in a direction that forms an angle with the (0001) crystal plane is formed on the surface of the nitride semiconductor crystal that is a crystal plane. perpendicular to the (0001) crystal plane. As a result, the pair of side surfaces extending in the longitudinal direction of the trench become a crystal plane that forms an angle with the (0001) crystal plane, and becomes a crystal plane in which atoms Of group III elements and nitrogen atoms are mixed. Therefore, in the subsequent crystal growth, the crystal growth proceeds from each of the pair of side surfaces at substantially the same speed, and a homogeneous crystal can be formed inside the trench.
On the other hand, for example, when a trench extending parallel to the (0001) crystal plane is formed, a pair of side surfaces extending in the longitudinal direction of the trench becomes a (0001) crystal plane. In this case, one side surface is a (0001) crystal plane in which only group III element atoms are present, and the other side surface is a (0001) crystal plane in which only nitrogen atoms are present. The crystal growth from the (0001) crystal plane in which only the atoms of the III element are present is significantly slower than the crystal growth from the (0001) crystal plane in which only the nitrogen atoms are present. As a result, it becomes difficult to form a homogeneous crystal inside the trench. On the other hand, for example, when a trench extending parallel to the (0001) crystal plane is formed, a pair of side surfaces extending in the longitudinal direction of the trench becomes a (0001) crystal plane. In this case, one side surface is a (0001) crystal plane in which only group III element atoms are present, and the other side surface is a (0001) crystal plane in which only nitrogen atoms are present. The crystal growth from the (0001) crystal plane in which only the atoms of the III element are present is significantly slower than the crystal growth from the (0001) crystal plane in which only the nitrogen atoms are present. As a result, it becomes difficult to form a homogeneous crystal inside the trench.
According to the manufacturing method of the present invention, it is possible to manufacture a semiconductor device that forms a homogeneous crystal inside a trench and realizes a stable normally-off operation. According to the manufacturing method of the present invention, it is possible to manufacture a semiconductor device that forms a homogeneous crystal inside a trench and realizes a stable normally-off operation.

上記した製造方法において、前記トレンチ形成工程では、(0001)結晶面に垂直に伸びるトレンチを形成することが好ましい。
この製造方法によれば、トレンチの長手方向に伸びる側面を、(0001)結晶面に垂直な結晶面とすることができる。それにより、それぞれの側面から結晶成長をより等しい速度で進行させ、トレンチの内部により均質な結晶を形成することができる。
In the manufacturing method described above, it is preferable to form a trench extending perpendicular to the (0001) crystal plane in the trench forming step.
According to this manufacturing method, the side surface extending in the longitudinal direction of the trench can be a crystal plane perpendicular to the (0001) crystal plane. Thereby, crystal growth can proceed from each side surface at a more equal speed, and a more uniform crystal can be formed inside the trench. According to this manufacturing method, the side surface extending in the longitudinal direction of the trench can be a crystal plane perpendicular to the (0001) crystal plane. Therefore, crystal growth can proceed from each side surface at a more equal speed, and a more uniform crystal can be formed inside the trench.

本発明により、ヘテロ接合面をチャネルに用いる半導体装置において、安定したノーマリオフ動作を実現することが可能となる。高いオフ耐圧と低いオン抵抗を有するノーマリオフ型の半導体装置を具現化することが可能となる。 According to the present invention, a stable normally-off operation can be realized in a semiconductor device using a heterojunction surface for a channel. A normally-off semiconductor device having a high off breakdown voltage and a low on-resistance can be realized.

最初に、以下に説明する実施例の主要な特徴を列記する。
(特徴1) 窒化物半導体結晶の上側表面は(10−10)結晶面に垂直な結晶面である。

(特徴2) 窒化物半導体結晶は、ドレイン領域を備えている。 (Feature 2) The nitride semiconductor crystal has a drain region. ドレイン領域は、n型の不純物を比較的に高濃度に含むn型の半導体領域である。 The drain region is an n-type semiconductor region containing n-type impurities at a relatively high concentration. ドレイン領域は、第1種類の窒化物半導体で構成された第1層の最下層部に形成されており、窒化物半導体結晶の下側表面に露出している。 The drain region is formed in the lowermost layer portion of the first layer composed of the first type nitride semiconductor, and is exposed on the lower surface of the nitride semiconductor crystal. ドレイン領域には、ドレイン電極がオーミック接触している。 The drain electrode is in ohmic contact with the drain region.
(特徴3) 窒化物半導体結晶は、ソース領域を備えている。 (Feature 3) The nitride semiconductor crystal has a source region. ソース領域は、n型の不純物を比較的に高濃度に含むn型の半導体領域である。 The source region is an n-type semiconductor region containing n-type impurities at a relatively high concentration. ソース領域は、第1種類の窒化物半導体で構成された第1層と第2種類の窒化物半導体で構成された第2層の両層に亘って形成されており、両層の境界面であるヘテロ接合面が通過している。 The source region is formed over both the first layer composed of the first type nitride semiconductor and the second layer composed of the second type nitride semiconductor, and is formed at the interface between the two layers. A heterojunction surface is passing through. ソース領域は、窒化物半導体結晶の上側表面に露出しており、ソース電極がオーミック接触している。 The source region is exposed on the upper surface of the nitride semiconductor crystal, and the source electrodes are in ohmic contact. First, the main features of the embodiments described below are listed. First, the main features of the embodiments described below are listed.
(Feature 1) The upper surface of the nitride semiconductor crystal is a crystal plane perpendicular to the (10-10) crystal plane. (Feature 1) The upper surface of the nitride semiconductor crystal is a crystal plane perpendicular to the (10-10) crystal plane.
(Feature 2) The nitride semiconductor crystal includes a drain region. The drain region is an n-type semiconductor region containing a relatively high concentration of n-type impurities. The drain region is formed in the lowermost layer portion of the first layer made of the first type nitride semiconductor, and is exposed on the lower surface of the nitride semiconductor crystal. A drain electrode is in ohmic contact with the drain region. (Feature 2) The nitride semiconductor crystal includes a drain region. The drain region is an n-type semiconductor region containing a relatively high concentration of n-type impurities. The drain region is formed in the lowermost layer portion of the first layer made of A drain electrode is in ohmic contact with the drain region. The first type nitride semiconductor, and is exposed on the lower surface of the nitride semiconductor crystal.
(Feature 3) The nitride semiconductor crystal has a source region. The source region is an n-type semiconductor region containing a relatively high concentration of n-type impurities. The source region is formed over both the first layer composed of the first type nitride semiconductor and the second layer composed of the second type nitride semiconductor, and at the boundary surface between the two layers. A heterojunction plane passes through. The source region is exposed on the upper surface of the nitride semiconductor crystal, and the source electrode is in ohmic contact. (Feature 3) The source region crystal has a source region. The source region is an n-type semiconductor region containing a relatively high concentration of n-type impurities. The source region is formed over both the first layer composed of the first type nitride. The source region is exposed on the upper surface of the nitride semiconductor crystal, and the source electrode is in. Semiconductor and the second layer composed of the second type nitride semiconductor, and at the boundary surface between the two layers. A heterojunction plane passes through. ohmic contact.

(実施例1)
図1は、実施例1の半導体装置10の要部断面図を模式的に示している。 FIG. 1 schematically shows a cross-sectional view of a main part of the semiconductor device 10 of the first embodiment. 図2は、図1中のII−II線における断面図を示している。 FIG. 2 shows a cross-sectional view taken along the line II-II in FIG. 図1、図2は、半導体装置10の単位構造を模式的に示すものである。 1 and 2 schematically show the unit structure of the semiconductor device 10. 半導体装置10には、図1、図2に示す単位構造が、図1、図2の左右方向に繰返し形成されている。 In the semiconductor device 10, the unit structures shown in FIGS. 1 and 2 are repeatedly formed in the left-right directions of FIGS. 1 and 2.
半導体装置10は、窒化物半導体結晶20と、ソース電極28と、ドレイン電極30と、ゲート電極32を備えている。 The semiconductor device 10 includes a nitride semiconductor crystal 20, a source electrode 28, a drain electrode 30, and a gate electrode 32. ソース電極28は、窒化物半導体結晶20の上側表面20aに形成されている。 The source electrode 28 is formed on the upper surface 20a of the nitride semiconductor crystal 20. ドレイン電極30は、窒化物半導体結晶20の下側表面20bに形成されている。 The drain electrode 30 is formed on the lower surface 20b of the nitride semiconductor crystal 20. ゲート電極32は、窒化物半導体結晶20の上側表面20aにゲート絶縁膜34を介して形成されている。 The gate electrode 32 is formed on the upper surface 20a of the nitride semiconductor crystal 20 via a gate insulating film 34. ソース電極28とドレイン電極30とゲート電極32は金属電極である。 The source electrode 28, the drain electrode 30, and the gate electrode 32 are metal electrodes. ソース電極28とドレイン電極30は、チタン(Ti)とアルミニウム(Al)が積層された積層体によって構成されている。 The source electrode 28 and the drain electrode 30 are composed of a laminated body in which titanium (Ti) and aluminum (Al) are laminated. ゲート電極32は、主にチタン(Ti)によって形成されている。 The gate electrode 32 is mainly made of titanium (Ti). ゲート絶縁膜34は、酸化シリコン(SiO )によって構成されている。 The gate insulating film 34 is made of silicon oxide (SiO 2 ). ソース電極28とドレイン電極30はオーミック電極であり、窒化物半導体結晶20の上下の表面20a、20bにそれぞれオーミック接触している。 The source electrode 28 and the drain electrode 30 are ohmic electrodes, and are in ohmic contact with the upper and lower surfaces 20a and 20b of the nitride semiconductor crystal 20, respectively. (Example 1) (Example 1)
FIG. 1 schematically shows a cross-sectional view of a main part of a semiconductor device 10 according to the first embodiment. FIG. 2 shows a cross-sectional view taken along line II-II in FIG. 1 and 2 schematically show the unit structure of the semiconductor device 10. In the semiconductor device 10, the unit structure shown in FIGS. 1 and 2 is repeatedly formed in the left-right direction of FIGS. FIG. 1 representing shows a cross-sectional view of a main part of a semiconductor device 10 according to the first embodiment. FIG. 2 shows a cross-sectional view taken along line II-II in FIG. 1 and 2 efficiently show the unit. structure of the semiconductor device 10. In the semiconductor device 10, the unit structure shown in FIGS. 1 and 2 is repeatedly formed in the left-right direction of FIGS.
The semiconductor device 10 includes a nitride semiconductor crystal 20, a source electrode 28, a drain electrode 30, and a gate electrode 32. The source electrode 28 is formed on the upper surface 20 a of the nitride semiconductor crystal 20. The drain electrode 30 is formed on the lower surface 20 b of the nitride semiconductor crystal 20. The gate electrode 32 is formed on the upper surface 20 a of the nitride semiconductor crystal 20 via a gate insulating film 34. The source electrode 28, the drain electrode 30, and the gate electrode 32 are metal electrodes. The source electrode 28 and the drain electrode 30 are constituted by a laminate in which titanium (Ti) and aluminum (Al) are laminated. The gate electrode 32 is mainly formed of titanium (Ti). The gate insulating film 34 is made of silicon oxide (SiO 2 ). The source electrode 28 and the drain electrode 30 are ohmic electrodes, and are in ohmic contact with the upper and lower surfaces 20a and 20b of the nitride semiconductor The semiconductor device 10 includes a nitride semiconductor crystal 20, a source electrode 28, a drain electrode 30, and a gate electrode 32. The source electrode 28 is formed on the upper surface 20 a of the nitride semiconductor crystal 20. The drain electrode 30 is formed on the lower surface 20 b of the nitride semiconductor crystal 20. The gate electrode 32 is formed on the upper surface 20 a of the nitride semiconductor crystal 20 via a gate insulating film 34. The source electrode 28, the drain electrode 30, The gate electrode 32 is mainly formed of titanium (Ti). The gate electrode 32 is mainly formed of titanium (Ti). And the gate electrode 32 are mainly formed of titanium (Ti). The gate electrode 32 is mainly formed of titanium (Ti). The gate insulating film 34 is made of silicon oxide (SiO 2 ). The source electrode 28 and the drain electrode 30 are ohmic electrodes, and are in ohmic contact with the upper and lower surfaces 20a and 20b of the nitride semiconductor crystal 20, respectively. crystal 20, respectively.

窒化物半導体結晶20は、六方晶の構造を有する結晶体である。窒化物半導体結晶20の上側表面20aは、(0001)結晶面に垂直な(10−10)結晶面である。窒化物半導体結晶20は、窒化ガリウム(GaN)で構成されたGaN層22(第1層)と、窒化ガリウム・アルミニウム(Al0.3Ga0.7N)で構成されたAlGaN層24(第2層)を備えている。AlGaN層24は、GaN層22の上側に積層されている。窒化ガリウムと窒化ガリウム・アルミニウムのバンドギャップは互いに異なることから、GaN層22とAlGaN層24との境界面26はヘテロ接合面となっている。なお、窒化ガリウムのバンドギャップは、窒化ガリウム・アルミニウムのバンドギャップよりも狭い。以下、GaN層22とAlGaN層24との境界面26を単にヘテロ接合面26と記すことがある。ヘテロ接合面26は、窒化物半導体結晶20の上側表面20aに平行であり、(0001)結晶面に垂直な(10−10)結晶面上に形成されている。ヘテロ接合面26の一部には、ゲート電極32がゲート絶縁膜34及びAlGaN層24を介して対向している。 The nitride semiconductor crystal 20 is a crystal body having a hexagonal crystal structure. The upper surface 20a of the nitride semiconductor crystal 20 is a (10-10) crystal plane perpendicular to the (0001) crystal plane. The nitride semiconductor crystal 20 includes a GaN layer 22 (first layer) composed of gallium nitride (GaN) and an AlGaN layer 24 (first layer) composed of gallium nitride / aluminum (Al 0.3 Ga 0.7 N). 2 layers). The AlGaN layer 24 is stacked on the upper side of the GaN layer 22. Since the band gaps of gallium nitride and gallium nitride / aluminum are different from each other, the boundary surface 26 between the GaN layer 22 and the AlGaN layer 24 is a heterojunction surface. The band gap of gallium nitride is narrower than that of gallium nitride / aluminum. Hereinafter, the boundary surface 26 between the GaN layer 22 and the AlGaN layer 24 may be simply referred to as a heterojunction surface 26. The heterojunction surface 26 is formed on a (10-10) crystal plane that is parallel to the upper surface 20a of the nitride semiconductor crystal 20 and perpendicular to the (0001) crystal plane. A gate electrode 32 faces a part of the heterojunction surface 26 with the gate insulating film 34 and the AlGaN layer 24 therebetween.

GaN層22は、導入した不純物の種類や濃度に応じて、ドレイン領域42と、低濃度半導体領域44、48、50と、p型半導体領域46と、ソース領域54に区分することができる。同様に、AlGaN層24は、i型半導体領域52とソース領域54に区分することができる。ソース領域54は、GaN層22とAlGaN層24に亘って形成されており、その内部をヘテロ接合面が26通過している。また、低濃度半導体領域44、48、50は、窒化物半導体結晶20の上下方向(厚み方向)に関して、p型半導体領域46よりも上方に位置する第1低濃度半導体領域50と、p型半導体領域46の側方(上下位置が等しい)に位置する第2低濃度半導体領域48と、p型半導体領域46よりも下方に位置する第3低濃度半導体領域44に区分することができる。   The GaN layer 22 can be divided into a drain region 42, low-concentration semiconductor regions 44, 48, 50, a p-type semiconductor region 46, and a source region 54 according to the type and concentration of the introduced impurity. Similarly, the AlGaN layer 24 can be divided into an i-type semiconductor region 52 and a source region 54. The source region 54 is formed across the GaN layer 22 and the AlGaN layer 24, and 26 heterojunction surfaces pass through the source region 54. The low-concentration semiconductor regions 44, 48, and 50 are the first low-concentration semiconductor region 50 located above the p-type semiconductor region 46 and the p-type semiconductor in the vertical direction (thickness direction) of the nitride semiconductor crystal 20. The region can be divided into a second low-concentration semiconductor region 48 located on the side of the region 46 (upper and lower positions are equal) and a third low-concentration semiconductor region 44 located below the p-type semiconductor region 46.

ドレイン領域42は、窒化ガリウムを主材料とする領域であり、n型の不純物を比較的に高濃度に含むn型の領域である。n型の不純物にはシリコン(Si)が用いられており、その濃度は約3×1018cm−3に調整されている。ドレイン領域42は、GaN層22の最下層部に形成されている。ドレイン領域42には、ドレイン電極30がオーミック接触している。
低濃度半導体領域44、48、50は、窒化ガリウムを主材料とする領域であり、n型の不純物を比較的に低濃度に含むn型の領域である。n型の不純物にはシリコン(Si)が用いられており、その濃度は約1×1016cm−3に調整されている。
第1低濃度半導体領域50は、ヘテロ接合面26の下側に形成されており、その一部がヘテロ接合面26とp型半導体領域46の間に介在している。 The first low-concentration semiconductor region 50 is formed below the heterojunction surface 26, and a part thereof is interposed between the heterojunction surface 26 and the p-type semiconductor region 46.
第2低濃度半導体領域48は、第1低濃度半導体領域50と第3低濃度半導体領域44の間に形成されている。 The second low-concentration semiconductor region 48 is formed between the first low-concentration semiconductor region 50 and the third low-concentration semiconductor region 44. 第2低濃度半導体領域48は、ゲート電極32の中間部の下方に形成されている。 The second low-concentration semiconductor region 48 is formed below the intermediate portion of the gate electrode 32.
第3低濃度半導体領域44は、ドレイン領域42の上側に形成されており、その一部がドレイン領域42とp型半導体領域46の間に介在している。 The third low-concentration semiconductor region 44 is formed above the drain region 42, and a part thereof is interposed between the drain region 42 and the p-type semiconductor region 46. 低濃度半導体領域44、48、50は、ゲート電極32の中間部の下方に、ヘテロ接合面26からドレイン領域42まで伸びる一連のn 領域を形成している。 The low-concentration semiconductor regions 44, 48, and 50 form a series of n regions extending from the heterojunction surface 26 to the drain region 42 below the intermediate portion of the gate electrode 32. The drain region 42 is a region mainly composed of gallium nitride, and is an n + type region containing a relatively high concentration of n-type impurities. Silicon (Si) is used as the n-type impurity, and its concentration is adjusted to about 3 × 10 18 cm −3 . The drain region 42 is formed in the lowermost layer portion of the GaN layer 22. The drain electrode 30 is in ohmic contact with the drain region 42. The drain region 42 is a region mainly composed of gallium nitride, and is an n + type region containing a relatively high concentration of n-type impurities. Silicon (Si) is used as the n-type impurities, and its concentration is adjusted to about 3 × 10 18 cm −3 . The drain region 42 is formed in the lowermost layer portion of the GaN layer 22. The drain electrode 30 is in ohmic contact with the drain region 42.
The low-concentration semiconductor regions 44, 48, and 50 are regions containing gallium nitride as a main material, and are n -type regions containing an n-type impurity at a relatively low concentration. Silicon (Si) is used as the n-type impurity, and its concentration is adjusted to about 1 × 10 16 cm −3 . The low-concentration semiconductor regions 44, 48, and 50 are regions containing gallium nitride as a main material, and are n -type regions containing an n-type impurities at a relatively low concentration. Silicon (Si) is used as the n -type impurities, and its concentration is adjusted to about 1 × 10 16 cm −3 .
The first low-concentration semiconductor region 50 is formed below the heterojunction surface 26, and a part of the first low-concentration semiconductor region 50 is interposed between the heterojunction surface 26 and the p-type semiconductor region 46. The first low-concentration semiconductor region 50 is formed below the heterojunction surface 26, and a part of the first low-concentration semiconductor region 50 is involved between the heterojunction surface 26 and the p-type semiconductor region 46.
The second low concentration semiconductor region 48 is formed between the first low concentration semiconductor region 50 and the third low concentration semiconductor region 44. The second low concentration semiconductor region 48 is formed below the middle portion of the gate electrode 32. The second low concentration semiconductor region 48 is formed between the first low concentration semiconductor region 50 and the third low concentration semiconductor region 44. The second low concentration semiconductor region 48 is formed below the middle portion of the gate electrode 32.
The third low-concentration semiconductor region 44 is formed above the drain region 42, and a part thereof is interposed between the drain region 42 and the p-type semiconductor region 46. The low concentration semiconductor regions 44, 48, 50 form a series of n regions extending from the heterojunction surface 26 to the drain region 42 below the intermediate portion of the gate electrode 32. The third low-concentration semiconductor region 44 is formed above the drain region 42, and a part thereof is involved between the drain region 42 and the p-type semiconductor region 46. The low concentration semiconductor regions 44, 48, 50 form a series of n regions extending from the heterojunction surface 26 to the drain region 42 below the intermediate portion of the gate electrode 32.

p型半導体領域46は、窒化ガリウムを主材料とする領域であり、p型の不純物を含むp型の領域である。p型の不純物にはマグネシウム(Mg)が用いられており、その濃度は約5×1019cm−3に調整されている。p型半導体領域46は、ソース電極28とゲート電極32の一部に対向する範囲に形成されている。図1に示すように、p型半導体領域46は、ヘテロ接合面26を介してゲート電極32の端部のみに対向しており、ゲート電極32の中間部の下方にp型半導体領域46は形成されていない。ゲート電極32の中間部の下方には、低濃度半導体領域44、48、50及びドレイン領域42によって、ヘテロ接合面26からp型半導体領域46の側方を通過して窒化物半導体結晶20の下側表面20bに到るn型の半導体領域が形成されている。このn型の半導体領域42、44、48、50は、ゲート電極32に電圧が印加されたときに電子が走行するチャネルの一部を構成する。 The p-type semiconductor region 46 is a region mainly composed of gallium nitride and is a p-type region containing p-type impurities. Magnesium (Mg) is used as the p-type impurity, and its concentration is adjusted to about 5 × 10 19 cm −3 . The p-type semiconductor region 46 is formed in a range facing a part of the source electrode 28 and the gate electrode 32. As shown in FIG. 1, the p-type semiconductor region 46 faces only the end portion of the gate electrode 32 through the heterojunction surface 26, and the p-type semiconductor region 46 is formed below the intermediate portion of the gate electrode 32. It has not been. Below the intermediate portion of the gate electrode 32, the lightly doped semiconductor regions 44, 48, 50 and the drain region 42 pass through the side of the p-type semiconductor region 46 from the heterojunction surface 26 and below the nitride semiconductor crystal 20. An n-type semiconductor region reaching the side surface 20b is formed. The n-type semiconductor regions 42, 44, 48, and 50 constitute a part of a channel through which electrons travel when a voltage is applied to the gate electrode 32.

ソース領域54は、GaN層22とAlGaN層24に亘って形成されており、窒化物半導体結晶20の上側表面20aに露出している。ソース領域54は、n型の不純物を比較的に高濃度に含むn型の領域である。n型の不純物にはシリコン(Si)が用いられており、その濃度は約3×1018cm−3に調整されている。ソース領域54は、ソース電極28の下に形成されており、ゲート電極32の端部に対向する位置まで伸びている。
i型半導体領域52は、窒化ガリウム・アルミニウムを主材料とする領域であり、不純物が導入されていないi型の領域である。 The i-type semiconductor region 52 is a region mainly made of gallium nitride / aluminum and is an i-type region in which impurities are not introduced. i型半導体領域52は、ゲート電極32の中間部と第1低濃度半導体領域50の間に位置している。 The i-type semiconductor region 52 is located between the intermediate portion of the gate electrode 32 and the first low-concentration semiconductor region 50. i型半導体領域52と上部低濃度半導体領域50との間に形成されたヘテロ接合面26の一部には、ゲート電極32が上方から対向しているとともに、p型半導体領域46が下方から対向している。 The gate electrode 32 faces a part of the heterojunction surface 26 formed between the i-type semiconductor region 52 and the upper low-concentration semiconductor region 50 from above, and the p-type semiconductor region 46 faces from below. are doing. なお、i型半導体領域52は、n型の不純物を導入することによってn型の半導体領域とすることもできる。 The i-type semiconductor region 52 can also be made into an n-type semiconductor region by introducing an n-type impurity. The source region 54 is formed across the GaN layer 22 and the AlGaN layer 24, and is exposed on the upper surface 20 a of the nitride semiconductor crystal 20. The source region 54 is an n + type region containing an n type impurity at a relatively high concentration. Silicon (Si) is used as the n-type impurity, and its concentration is adjusted to about 3 × 10 18 cm −3 . The source region 54 is formed under the source electrode 28 and extends to a position facing the end of the gate electrode 32. The source region 54 is formed across the GaN layer 22 and the AlGaN layer 24, and is exposed on the upper surface 20 a of the nitride semiconductor crystal 20. The source region 54 is an n + type region containing an n type impurities at a Silicon (Si) is used as the n-type impurities, and its concentration is adjusted to about 3 × 10 18 cm −3 . The source region 54 is formed under the source electrode 28 and extends to a position facing the end of the gate electrode 32.
The i-type semiconductor region 52 is a region mainly composed of gallium nitride / aluminum, and is an i-type region into which no impurity is introduced. The i-type semiconductor region 52 is located between the intermediate portion of the gate electrode 32 and the first low concentration semiconductor region 50. A part of the heterojunction surface 26 formed between the i-type semiconductor region 52 and the upper low-concentration semiconductor region 50 is opposed to the gate electrode 32 from above, and the p-type semiconductor region 46 is opposed from below. is doing. Note that the i-type semiconductor region 52 may be an n-type semiconductor region by introducing an n-type impurity. The i-type semiconductor region 52 is a region mainly composed of gallium nitride / aluminum, and is an i-type region into which no impurity is introduced. The i-type semiconductor region 52 is located between the intermediate portion of the gate electrode 32 and the first low concentration semiconductor region 50. A part of the heterojunction surface 26 formed between the i-type semiconductor region 52 and the upper low-concentration semiconductor region 50 is opposed to the gate electrode 32 from above, and the p-type semiconductor region region 46 is opposed from below. Is doing. Note that the i-type semiconductor region 52 may be an n-type semiconductor region by introducing an n-type impurities.

図2に示すように、第2低濃度半導体領域48は、(10−10)結晶面に平行な断面形状が矩形形状を有しており、その長手方向が<0001>結晶軸方向に伸びている。第2低濃度半導体領域48とp型半導体領域46との境界面46a、46bは、両領域46、48が側方から互いに隣接していることから、(10−10)結晶面であるヘテロ接合面に垂直である。また、その境界面46a、46bのうち、第2低濃度半導体領域48の長手方向に伸びる境界面46aは、(0001)結晶面に垂直な(11−20)結晶面内に広がっている。即ち、第2低濃度半導体領域48とp型半導体領域46との境界面46a、46bの大部分(半分を超える部分)46bは、(10−10)結晶面であるヘテロ接合面に垂直であるとともに、(0001)結晶面に垂直な(11−20)結晶面内に広がっている。
第2低濃度半導体領域48の幅寸法L1は、その長手寸法L2よりも十分に短く、本実施例ではL1=2〜6μm、L2=1.0mmに設定されている。 The width dimension L1 of the second low-concentration semiconductor region 48 is sufficiently shorter than the longitudinal dimension L2 thereof, and is set to L1 = 2 to 6 μm and L2 = 1.0 mm in this embodiment. As shown in FIG. 2, the second low-concentration semiconductor region 48 has a rectangular shape in cross section parallel to the (10-10) crystal plane, and its longitudinal direction extends in the <0001> crystal axis direction. Yes. The boundary surfaces 46a and 46b between the second low-concentration semiconductor region 48 and the p-type semiconductor region 46 are heterojunctions having a (10-10) crystal plane because both the regions 46 and 48 are adjacent to each other from the side. Perpendicular to the surface. Of the boundary surfaces 46a and 46b, the boundary surface 46a extending in the longitudinal direction of the second low-concentration semiconductor region 48 extends in the (11-20) crystal plane perpendicular to the (0001) crystal plane. That is, most (more than half) of the boundary surfaces 46a and 46b between the second low-concentration semiconductor region 48 and the p-type semiconductor region 46 are perpendicular to the heterojunction surface which is a (10-10) As shown in FIG. 2, the second low-concentration semiconductor region 48 has a rectangular shape in cross section parallel to the (10-10) crystal plane, and its longitudinal direction extends in the <0001> crystal axis direction. Yes. The boundary surfaces 46a and 46b between the second low-concentration semiconductor region 48 and the p-type semiconductor region 46 are heterojunctions having a (10-10) crystal plane because both the regions 46 and 48 are adjacent to each other from the side. Perpendicular to the surface. Of the boundary surfaces 46a and 46b, the boundary surface 46a extending in the longitudinal direction of the second low-concentration semiconductor region 48 extends in the (11-20) crystal plane perpendicular to the (0001) crystal plane. That is, most (more than half) of the boundary surfaces 46a and 46b between the second low-concentration semiconductor region 48 and the p-type semiconductor region 46 are perpendicular to the heterojunction surface which is a (10-10) crystal plane. At the same time, it extends in the (11-20) crystal plane perpendicular to the (0001) crystal plane. crystal plane. At the same time, it extends in the (11-20) crystal plane perpendicular to the (0001) crystal plane.
The width dimension L1 of the second low-concentration semiconductor region 48 is sufficiently shorter than the longitudinal dimension L2, and in this embodiment, L1 = 2 to 6 μm and L2 = 1.0 mm. The width dimension L1 of the second low-concentration semiconductor region 48 is sufficiently shorter than the longitudinal dimension L2, and in this embodiment, L1 = 2 to 6 μm and L2 = 1.0 mm.

次に、半導体装置10の動作を説明する。半導体装置10では、ヘテロ接合面26が(10−10)結晶面上に形成されている。(10−10)結晶面は、その垂直方向に極性が変化しない無極性面である。そのことから、ヘテロ接合面26に垂直な方向には、自発分極及びピエゾ分極が生じない。さらに、p型半導体領域46が、第2低濃度半導体領域50を介してヘテロ接合面26に対向している。それにより、ゲート電極32に電圧を印加していない状態では、低濃度半導体領域44、48、50に空乏層が形成され、その空乏層はヘテロ接合面26まで伸びている。その結果、ゲート電極32に電圧を印加していない状態では、低濃度半導体領域44、48、50が空乏化されるとともに、ヘテロ接合面26における2次元電子ガス層の形成が禁止される。半導体装置10では、ゲート電極32に電圧が印加されていない状態で、ソース電極28とドレイン電極30の間の通電が禁止される。
一方、ゲート電極32に正の電圧を印加した状態では、低濃度半導体領域44、48、50に形成されていた空乏層が縮小するとともに、ヘテロ接合面26に2次元電子ガス層が形成される。 On the other hand, when a positive voltage is applied to the gate electrode 32, the depletion layer formed in the low-concentration semiconductor regions 44, 48, and 50 shrinks, and a two-dimensional electron gas layer is formed on the heterojunction surface 26. .. 換言すれば、低濃度半導体領域44、48、50に形成されていた空乏層を縮小させ、ヘテロ接合面26に2次元電子ガス層を形成させるためには、ゲート電極32に比較的に大きな正の電圧を印加する必要がある。 In other words, in order to reduce the depletion layer formed in the low-concentration semiconductor regions 44, 48, 50 and to form a two-dimensional electron gas layer on the heterojunction surface 26, the gate electrode 32 has a relatively large positive electrode. It is necessary to apply the voltage of. ゲート電極32に正の電圧を印加すると、ヘテロ接合面26や低濃度半導体領域44、48、50は多数の電子が走行可能な状態となり、ソース電極28とドレイン電極30の間が通電可能な状態となる。 When a positive voltage is applied to the gate electrode 32, the heterojunction surface 26 and the low-concentration semiconductor regions 44, 48, and 50 are in a state in which a large number of electrons can travel, and a state in which the source electrode 28 and the drain electrode 30 can be energized. It becomes. このように、半導体装置10は、安定したノーマリオフ動作を実現することができる。 In this way, the semiconductor device 10 can realize a stable normal-off operation. Next, the operation of the semiconductor device 10 will be described. In the semiconductor device 10, the heterojunction surface 26 is formed on the (10-10) crystal plane. The (10-10) crystal plane is a nonpolar plane whose polarity does not change in the vertical direction. Therefore, spontaneous polarization and piezo polarization do not occur in the direction perpendicular to the heterojunction plane 26. Further, the p-type semiconductor region 46 is opposed to the heterojunction surface 26 with the second low-concentration semiconductor region 50 interposed therebetween. As a result, when no voltage is applied to the gate electrode 32, a depletion layer is formed in the low concentration semiconductor regions 44, 48, and 50, and the depletion layer extends to the heterojunction surface 26. As a result, in a state where no voltage is applied to the gate electrode 32, the low concentration semiconductor regions 44, 48 and 50 are depleted and the formation of the two-dimensional elect Next, the operation of the semiconductor device 10 will be described. In the semiconductor device 10, the heterojunction surface 26 is formed on the (10-10) crystal plane. The (10-10) crystal plane is a nonpolar plane whose polarity does Not change in the vertical direction. Therefore, spontaneous polarization and piezo polarization do not occur in the direction perpendicular to the heterojunction plane 26. Further, the p-type semiconductor region 46 is opposed to the heterojunction surface 26 with the second low-concentration semiconductor As a result, when no voltage is applied to the gate electrode 32, a depletion layer is formed in the low concentration semiconductor regions 44, 48, and 50, and the depletion layer extends to the heterojunction surface 26. As a result, in a state where no voltage is applied to the gate electrode 32, the low concentration semiconductor regions 44, 48 and 50 are depleted and the formation of the two-dimensional elect ron gas layer on the heterojunction surface 26 is prohibited. In the semiconductor device 10, energization between the source electrode 28 and the drain electrode 30 is prohibited while no voltage is applied to the gate electrode 32. ron gas layer on the heterojunction surface 26 is prohibited. In the semiconductor device 10, energization between the source electrode 28 and the drain electrode 30 is prohibited while no voltage is applied to the gate electrode 32.
On the other hand, when a positive voltage is applied to the gate electrode 32, the depletion layer formed in the low concentration semiconductor regions 44, 48, 50 is reduced and a two-dimensional electron gas layer is formed on the heterojunction surface 26. . In other words, in order to reduce the depletion layer formed in the low-concentration semiconductor regions 44, 48, 50 and form a two-dimensional electron gas layer on the heterojunction surface 26, a relatively large positive electrode is formed on the gate electrode 32. Must be applied. When a positive voltage is applied to the gate electrode 32, the heterojunction surface 26 and the low-concentration semiconductor regions 44, 48, and 50 are in a state in which a large number of electrons can travel, and the source electrode 28 and the drain electrode 30 can be energized. It becomes. Thus, the semiconductor device 10 can realize a stable normally-off operation. On the other hand, when a positive voltage is applied to the gate electrode 32, the depletion layer formed in the low concentration semiconductor regions 44, 48, 50 is reduced and a two-dimensional electron gas layer is formed on the heterojunction surface 26. In other words, in order to reduce the depletion layer formed in the low-concentration semiconductor regions 44, 48, 50 and form a two-dimensional electron gas layer on the heterojunction surface 26, a relatively large positive electrode is formed on the gate electrode 32. Must be applied. When a positive voltage is applied to the gate electrode 32, the heterojunction surface 26 and the low-concentration semiconductor regions 44, 48, and 50 are in a state in which a large number of electrons can travel, And the source electrode 28 and the drain electrode 30 can be energized. It becomes. Thus, the semiconductor device 10 can realize a stable normally-off operation.

半導体装置10のしきい値電圧(オンするのに要するゲート電圧)は、低濃度半導体領域44、48、50の不純物濃度、p型半導体領域48の不純物濃度、第1低濃度半導体領域50の厚みt(図1参照)等によって変化する。あるいは、i型半導体領域52に例えばn型の不純物を導入することによっても変化する。従って、これらの設定を適宜変更することによって、所望のしきい値電圧を有する半導体装置10を具現化することができる。   The threshold voltage (gate voltage required for turning on) of the semiconductor device 10 is such that the impurity concentration of the low concentration semiconductor regions 44, 48 and 50, the impurity concentration of the p-type semiconductor region 48, and the thickness of the first low concentration semiconductor region 50. It varies depending on t (see FIG. 1) and the like. Alternatively, it is changed by introducing an n-type impurity into the i-type semiconductor region 52, for example. Therefore, the semiconductor device 10 having a desired threshold voltage can be realized by appropriately changing these settings.

ヘテロ接合面26は、特定の(10−10)結晶面上に限られず、(10−10)結晶面に等価な結晶面に形成することができる。あるいは、ヘテロ接合面26は、例えば(11−20)結晶面等のように、(0001)結晶面に垂直な結晶面上に形成してもよい。(0001)結晶面に垂直な結晶面は、その垂直方向に極性が変化しない無極性面である。そのことから、ヘテロ接合面26を、(0001)結晶面上は避け、(0001)結晶面に垂直な結晶面上に形成することによって、ヘテロ接合面26に垂直な方向の自発分極及びピエゾ分極の発生を抑制することができる。それにより、ヘテロ接合面26に発生する二次元電子ガスの密度を適度に抑制することができる。   The heterojunction plane 26 is not limited to a specific (10-10) crystal plane, and can be formed on a crystal plane equivalent to the (10-10) crystal plane. Alternatively, the heterojunction surface 26 may be formed on a crystal plane perpendicular to the (0001) crystal plane, such as a (11-20) crystal plane. The crystal plane perpendicular to the (0001) crystal plane is a nonpolar plane whose polarity does not change in the vertical direction. Therefore, by forming the heterojunction plane 26 on a crystal plane perpendicular to the (0001) crystal plane, avoiding the (0001) crystal plane, spontaneous polarization and piezoelectric polarization in the direction perpendicular to the heterojunction plane 26 are achieved. Can be suppressed. Thereby, the density of the two-dimensional electron gas generated on the heterojunction surface 26 can be moderately suppressed.

(半導体装置10の製造方法)
次に半導体装置10の製造方法を説明する。
先ず、図3に示すように、n型の窒化ガリウムを主材料とするとともに、その主表面が(10−10)結晶面である半導体基板42(後にドレイン領域42となる)を用意する。次に、MOCVD(Metal Organic Chemical Vapor Deposition)法を利用して、半導体基板42上にn型の窒化ガリウム層44(後に第3低濃度半導体領域44となる)を結晶成長させる。次に、MOCVD法を利用して、n型の窒化ガリウム層44上に、p型の窒化ガリウム層46(後にp型半導体領域46となる)を結晶成長させる。
次に、図4に示すように、リソグラフィー技術とRIE技術を利用して、p型の窒化ガリウム層46を貫通し、n 型の窒化ガリウム層44に達するトレンチ47を形成する。 Next, as shown in FIG. 4, a trench 47 is formed by using the lithography technique and the RIE technique to penetrate the p-type gallium nitride layer 46 and reach the n - type gallium nitride layer 44. トレンチ47は、図4の奥行き方向に伸びる筋状に形成する。 The trench 47 is formed in a streak shape extending in the depth direction of FIG. 即ち、トレンチ47は、<0001>結晶軸に平行に形成する。 That is, the trench 47 is formed parallel to the <0001> crystal axis. その結果、トレンチ47の対向する一対の側面47aは、(10−10)結晶面及び(0001)結晶面に垂直な(11−20)結晶面となる。 As a result, the pair of side surfaces 47a of the trench 47 facing each other become a (10-10) crystal plane and a (11-20) crystal plane perpendicular to the (0001) crystal plane. (Manufacturing method of the semiconductor device 10) (Manufacturing method of the semiconductor device 10)
Next, a method for manufacturing the semiconductor device 10 will be described. Next, a method for manufacturing the semiconductor device 10 will be described.
First, as shown in FIG. 3, a semiconductor substrate 42 (which will later become a drain region 42) whose main surface is n + -type gallium nitride and whose main surface is a (10-10) crystal plane is prepared. Next, using an MOCVD (Metal Organic Chemical Vapor Deposition) method, an n -type gallium nitride layer 44 (which later becomes the third low-concentration semiconductor region 44) is crystal-grown on the semiconductor substrate 42. Next, a p-type gallium nitride layer 46 (which will later become a p-type semiconductor region 46) is grown on the n -type gallium nitride layer 44 by MOCVD. First, as shown in FIG. 3, a semiconductor substrate 42 (which will later become a drain region 42) whose main surface is n + -type gallium nitride and whose main surface is a (10-10) crystal plane is prepared. Next , using an MOCVD (Metal Organic Chemical Vapor Deposition) method, an n -type gallium nitride layer 44 (which later becomes the third low-concentration semiconductor region 44) is crystal-grown on the semiconductor substrate 42. Next, a p- type gallium nitride layer 46 (which will later become a p-type semiconductor region 46) is grown on the n -type gallium nitride layer 44 by MOCVD.
Next, as shown in FIG. 4, using the lithography technique and the RIE technique, a trench 47 that penetrates the p-type gallium nitride layer 46 and reaches the n -type gallium nitride layer 44 is formed. The trench 47 is formed in a streak shape extending in the depth direction of FIG. That is, the trench 47 is formed parallel to the <0001> crystal axis. As a result, the pair of side surfaces 47a opposite to each other in the trench 47 become a (10-10) crystal plane and a (11-20) crystal plane perpendicular to the (0001) crystal plane. Next, as shown in FIG. 4, using the lithograph technique and the RIE technique, a trench 47 that penetrates the p-type gallium nitride layer 46 and reaches the n -type gallium nitride layer 44 is formed. The trench 47 is formed. in a streak shape extending in the depth direction of FIG. That is, the trench 47 is formed parallel to the <0001> crystal axis. As a result, the pair of side surfaces 47a opposite to each other in the trench 47 become a ( 10-10) crystal plane and a (11-20) crystal plane perpendicular to the (0001) crystal plane.

次に、図5に示すように、MOCVD法を利用して、n型の窒化ガリウム層44及びp型の窒化ガリウム層46の上に、n型の窒化ガリウム層48、50(後に第2低濃度半導体領域48と第1低濃度半導体領域50となる)を結晶成長させる。このとき、トレンチ47の内部では、一対の側面47aのそれぞれから結晶成長が進行する。先に説明したように、一対の側面47aは、(0001)結晶面に垂直な(11−20)結晶面である。そのことから、結晶成長がそれぞれの側面47aから略等しい速度で進行する。それぞれの側面47aから結晶成長が略等しい速度で進行することにより、トレンチ47の内部にn型の窒化ガリウム層48を均質に形成することができる。 Next, as shown in FIG. 5, using the MOCVD method, n - on the type gallium nitride layer 44 and p-type gallium nitride layer 46, n - first the type gallium nitride layer 48, 50 (after 2) a low-concentration semiconductor region 48 and a first low-concentration semiconductor region 50) are grown. At this time, in the trench 47, crystal growth proceeds from each of the pair of side surfaces 47a. As described above, the pair of side surfaces 47a are (11-20) crystal planes perpendicular to the (0001) crystal plane. Therefore, crystal growth proceeds from each side surface 47a at a substantially equal speed. Crystal growth proceeds from each side surface 47 a at a substantially equal speed, so that the n -type gallium nitride layer 48 can be formed uniformly in the trench 47.

上記に対して、例えばトレンチ47を<11−20>結晶軸に平行に形成した場合、トレンチ47の対向する一対の側面47aは(0001)結晶面となる。この場合、一方の側面47aはガリウム原子のみが存在する(0001)結晶面となり、他方の側面47aは窒素原子のみが存在する(0001)結晶面となる。ガリウム原子のみが存在する(0001)結晶面からの結晶成長は、窒素原子のみが存在する(0001)結晶面からの結晶成長よりも、その進行速度が顕著に遅くなる。そのことから、トレンチ47を<11−20>結晶軸に平行に形成してしまうと、トレンチ47の内部における結晶成長に非対称性が生じ、トレンチ47の内部にn型の窒化ガリウム層48を均質に形成することができなくなる。そのことから、トレンチ47を形成する場合は、一対の側面47aが(0001)結晶面と角度を成す結晶面となるように、トレンチ47の伸びる方向を定めるとよい。結果的に、製造された半導体装置10では、p型半導体領域46と第2低濃度半導体領域48との境界面46a、46bの大部分46aが、(0001)結晶面と角度を成す結晶面上に形成される。上記の観点から、実施例1の半導体装置10では、p型半導体領域46と第2低濃度半導体領域48との境界面46a、46bの大部分46aが、必ずしも(0001)結晶面に垂直な(11−20)結晶面上に形成されていなくともよく、(0001)結晶面と角度を成す結晶面上に形成されていればよい。 In contrast, for example, when the trench 47 is formed in parallel to the <11-20> crystal axis, the pair of side surfaces 47a opposed to the trench 47 is a (0001) crystal plane. In this case, one side 47a is a (0001) crystal plane in which only gallium atoms are present, and the other side 47a is a (0001) crystal plane in which only nitrogen atoms are present. Crystal growth from a (0001) crystal plane in which only gallium atoms are present has a significantly slower progression rate than crystal growth from a (0001) crystal plane in which only nitrogen atoms are present. Therefore, if the trench 47 is formed in parallel to the <11-20> crystal axis, the crystal growth inside the trench 47 becomes asymmetric, and the n -type gallium nitride layer 48 is formed inside the trench 47. It becomes impossible to form homogeneously. Therefore, when forming the trench 47, it is preferable to determine the direction in which the trench 47 extends so that the pair of side surfaces 47a is a crystal plane forming an angle with the (0001) crystal plane. As a result, in the manufactured semiconductor device 10, most of the boundary surfaces 46 a and 46 b between the p-type semiconductor region 46 and the second low-concentration semiconductor region 48 are on the crystal plane forming an angle with the (0001) crystal plane. Formed. From the above viewpoint, in the semiconductor device 10 of Example 1, most of the boundary surfaces 46a and 46b between the p-type semiconductor region 46 and the second low-concentration semiconductor region 48 are not necessarily perpendicular to the (0001) crystal plane ( 11-20) It does not need to be formed on the crystal plane, and may be formed on the crystal plane forming an angle with the (0001) crystal plane.

次に、図6に示すように、MOCVD法を利用して、n型の窒化ガリウム層50の上に、i型の窒化ガリウム・アルミニウム層52(後にi型半導体領域52となる)を結晶成長させる。
次に、図7に示すように、イオン注入を実施してソース領域52を形成する。このイオン注入時には、i型の窒化ガリウム・アルミニウム層52の上側表面に、ソース領域52の形成範囲に開口が形成されたマスク(図示省略)を形成する。
以上までの工程によって、半導体装置10の窒化物半導体結晶20の成形が完了する。 By the above steps, the molding of the nitride semiconductor crystal 20 of the semiconductor device 10 is completed. 成形が完了した窒化物半導体結晶20は、必要に応じて表面に保護層を形成した後、アニール処理が実施される。 The nitride semiconductor crystal 20 that has been molded is subjected to an annealing treatment after forming a protective layer on the surface as needed. Next, as shown in FIG. 6, an i-type gallium nitride / aluminum layer 52 (which later becomes an i-type semiconductor region 52) is crystallized on the n -type gallium nitride layer 50 using MOCVD. Grow. Next, as shown in FIG. 6, an i-type gallium nitride layer 52 (which later becomes an i-type semiconductor region 52) is crystallized on the n -type gallium nitride layer 50 using MOCVD. Grow.
Next, as shown in FIG. 7, ion implantation is performed to form the source region 52. At the time of this ion implantation, a mask (not shown) having an opening in the formation region of the source region 52 is formed on the upper surface of the i-type gallium nitride / aluminum layer 52. Next, as shown in FIG. 7, ion implantation is performed to form the source region 52. At the time of this ion implantation, a mask (not shown) having an opening in the formation region of the source region 52 is formed on the upper surface of the i-type gallium nitride / aluminum layer 52.
Through the above steps, the formation of the nitride semiconductor crystal 20 of the semiconductor device 10 is completed. The nitride semiconductor crystal 20 that has been formed is annealed after forming a protective layer on the surface as necessary. Through the above steps, the formation of the nitride semiconductor crystal 20 of the semiconductor device 10 is completed. The nitride semiconductor crystal 20 that has been formed is annealed after forming a protective layer on the surface as necessary.

次に、図8に示すように、CVD法を利用して、i型の窒化ガリウム・アルミニウム層52の上に、酸化シリコン層34(後にゲート絶縁膜34となる)を成膜する。
次に、図9に示すように、リソグラフィー技術とエッチング技術を利用して、酸化シリコン層34の一部を除去し、ソース領域54の一部を露出させる。

次いで、ソース電極28とドレイン電極30とゲート電極32を形成する。 Next, the source electrode 28, the drain electrode 30, and the gate electrode 32 are formed. ソース電極28はドレイン領域54の上に形成し、ドレイン電極30はドレイン領域42の下に形成し、ゲート電極32はゲート絶縁膜34の上に形成する。 The source electrode 28 is formed above the drain region 54, the drain electrode 30 is formed below the drain region 42, and the gate electrode 32 is formed above the gate insulating film 34. 以上の工程によって、図1に示す半導体装置10を製造することができる。 By the above steps, the semiconductor device 10 shown in FIG. 1 can be manufactured. Next, as shown in FIG. 8, a silicon oxide layer 34 (which will later become the gate insulating film 34) is formed on the i-type gallium nitride / aluminum layer 52 using the CVD method. Next, as shown in FIG. 8, a silicon oxide layer 34 (which will later become the gate insulating film 34) is formed on the i-type gallium nitride / aluminum layer 52 using the CVD method.
Next, as shown in FIG. 9, a part of the silicon oxide layer 34 is removed and a part of the source region 54 is exposed using a lithography technique and an etching technique. Next, as shown in FIG. 9, a part of the silicon oxide layer 34 is removed and a part of the source region 54 is exposed using a lithograph technique and an etching technique.
Next, the source electrode 28, the drain electrode 30, and the gate electrode 32 are formed. The source electrode 28 is formed on the drain region 54, the drain electrode 30 is formed on the drain region 42, and the gate electrode 32 is formed on the gate insulating film 34. Through the above steps, the semiconductor device 10 shown in FIG. 1 can be manufactured. Next, the source electrode 28, the drain electrode 30, and the gate electrode 32 are formed. The source electrode 28 is formed on the drain region 54, the drain electrode 30 is formed on the drain region 42, and the gate electrode 32 is formed on the gate insulating film 34. Through the above steps, the semiconductor device 10 shown in FIG. 1 can be manufactured.

(実施例2)
図10は、実施例2の半導体装置100の要部断面図を模式的に示している。実施例2の半導体装置100は、横型のヘテロ接合電界効果トランジスタである。

半導体装置100は、窒化物半導体結晶120と、ソース電極128と、ドレイン電極130と、ゲート電極132を備えている。 The semiconductor device 100 includes a nitride semiconductor crystal 120, a source electrode 128, a drain electrode 130, and a gate electrode 132. ソース電極128は、窒化物半導体結晶120の上側表面120aに形成されている。 The source electrode 128 is formed on the upper surface 120a of the nitride semiconductor crystal 120. ドレイン電極130は、窒化物半導体結晶120の上側表面120aに形成されている。 The drain electrode 130 is formed on the upper surface 120a of the nitride semiconductor crystal 120. ゲート電極132は、窒化物半導体結晶120の上側表面120aにゲート絶縁膜34を介して形成されている。 The gate electrode 132 is formed on the upper surface 120a of the nitride semiconductor crystal 120 via a gate insulating film 34. ゲート電極132は、ソース電極128とドレイン電極130の間に位置している。 The gate electrode 132 is located between the source electrode 128 and the drain electrode 130. (Example 2) (Example 2)
FIG. 10 schematically illustrates a cross-sectional view of a main part of the semiconductor device 100 according to the second embodiment. The semiconductor device 100 according to the second embodiment is a lateral heterojunction field effect transistor. FIG. 10 accurately illustrates a cross-sectional view of a main part of the semiconductor device 100 according to the second embodiment. The semiconductor device 100 according to the second embodiment is a lateral heterojunction field effect transistor.
The semiconductor device 100 includes a nitride semiconductor crystal 120, a source electrode 128, a drain electrode 130, and a gate electrode 132. The source electrode 128 is formed on the upper surface 120 a of the nitride semiconductor crystal 120. The drain electrode 130 is formed on the upper surface 120 a of the nitride semiconductor crystal 120. The gate electrode 132 is formed on the upper surface 120 a of the nitride semiconductor crystal 120 via the gate insulating film 34. The gate electrode 132 is located between the source electrode 128 and the drain electrode 130. The semiconductor device 100 includes a nitride semiconductor crystal 120, a source electrode 128, a drain electrode 130, and a gate electrode 132. The source electrode 128 is formed on the upper surface 120 a of the semiconductor semiconductor crystal 120. The drain electrode 130 is formed on the upper surface 120 a of the nitride semiconductor crystal 120. The gate electrode 132 is formed on the upper surface 120 a of the nitride semiconductor crystal 120 via the gate insulating film 34. The gate electrode 132 is located between the source electrode 128 and the drain electrode 130.

窒化物半導体結晶120は、六方晶の構造を有する単結晶体であり、上側表面120aが(0001)結晶面に垂直な(10−10)結晶面となっている。窒化物半導体結晶120は、窒化ガリウム(GaN)で構成されたGaN層122(第1層)と、窒化ガリウム・アルミニウム(Al0.3Ga0.7N)で構成されたAlGaN層124(第2層)を備えている。AlGaN層124は、GaN層122の上側に積層されている。窒化ガリウムと窒化ガリウム・アルミニウムのバンドギャップは互いに異なることから、GaN層122とAlGaN層124との境界面126はヘテロ接合面となっている。以下、GaN層122とAlGaN層124との境界面126を単にヘテロ接合面126と記すことがある。ヘテロ接合面126は、窒化物半導体結晶120の上側表面120aに平行であり、(0001)結晶面に垂直な(10−10)結晶面上に形成されている。ヘテロ接合面126の一部には、ゲート電極132がゲート絶縁膜134及びAlGaN層124を介して対向している。 The nitride semiconductor crystal 120 is a single crystal having a hexagonal crystal structure, and the upper surface 120a is a (10-10) crystal plane perpendicular to the (0001) crystal plane. The nitride semiconductor crystal 120 includes a GaN layer 122 (first layer) composed of gallium nitride (GaN) and an AlGaN layer 124 (first layer) composed of gallium nitride / aluminum (Al 0.3 Ga 0.7 N). 2 layers). The AlGaN layer 124 is stacked on the upper side of the GaN layer 122. Since the band gaps of gallium nitride and gallium nitride / aluminum are different from each other, the boundary surface 126 between the GaN layer 122 and the AlGaN layer 124 is a heterojunction surface. Hereinafter, the boundary surface 126 between the GaN layer 122 and the AlGaN layer 124 may be simply referred to as a heterojunction surface 126. The heterojunction surface 126 is formed on a (10-10) crystal plane that is parallel to the upper surface 120a of the nitride semiconductor crystal 120 and perpendicular to the (0001) crystal plane. The gate electrode 132 is opposed to a part of the heterojunction surface 126 with the gate insulating film 134 and the AlGaN layer 124 interposed therebetween.

GaN層122は、導入した不純物の種類や濃度に応じて、p型半導体領域146と、低濃度半導体領域150と、ソース領域154と、ドレイン領域154に区分することができる。同様に、AlGaN層124は、i型半導体領域152とソース領域154とドレイン領域142に区分することができる。ソース領域154とドレイン領域142は、GaN層122とAlGaN層124に亘って形成されており、その内部をヘテロ接合面126が通過している。   The GaN layer 122 can be divided into a p-type semiconductor region 146, a low-concentration semiconductor region 150, a source region 154, and a drain region 154 according to the type and concentration of the introduced impurity. Similarly, the AlGaN layer 124 can be divided into an i-type semiconductor region 152, a source region 154, and a drain region 142. The source region 154 and the drain region 142 are formed across the GaN layer 122 and the AlGaN layer 124, and the heterojunction surface 126 passes through the inside.

p型半導体領域146は、窒化ガリウムを主材料とする領域であり、p型の不純物を含むp型の領域である。
低濃度半導体領域150は、窒化ガリウムを主材料とする領域であり、n型の不純物を比較的に低濃度に含むn型の領域である。低濃度半導体領域150は、p型半導体領域146の上に形成されている。低濃度半導体領域150は、ヘテロ接合面126とp型半導体領域146の間に介在している。
ソース領域154は、GaN層122とAlGaN層124に亘って形成されており、窒化物半導体結晶120の上側表面120aに露出している。 The source region 154 is formed over the GaN layer 122 and the AlGaN layer 124, and is exposed on the upper surface 120a of the nitride semiconductor crystal 120. ソース領域154は、n型の不純物を比較的に高濃度に含むn 型の領域である。 The source region 154 is an n + type region containing n-type impurities at a relatively high concentration. ソース領域154は、ソース電極128の下に形成されており、ゲート電極32の一方の端部に対向する位置まで伸びている。 The source region 154 is formed below the source electrode 128 and extends to a position facing one end of the gate electrode 32.
ドレイン領域142は、GaN層122とAlGaN層124に亘って形成されており、窒化物半導体結晶120の上側表面120aに露出している。 The drain region 142 is formed over the GaN layer 122 and the AlGaN layer 124, and is exposed on the upper surface 120a of the nitride semiconductor crystal 120. ドレイン領域142は、n型の不純物を比較的に高濃度に含むn 型の領域である。 The drain region 142 is an n + type region containing n-type impurities at a relatively high concentration. ドレイン領域142は、ドレイン電極130の下に形成されており、ゲート電極132の他方の端部に対向する位置まで伸びている。 The drain region 142 is formed below the drain electrode 130 and extends to a position facing the other end of the gate electrode 132. The p-type semiconductor region 146 is a region containing gallium nitride as a main material, and is a p-type region containing a p-type impurity. The p-type semiconductor region 146 is a region containing gallium nitride as a main material, and is a p-type region containing a p-type impurities.
The low-concentration semiconductor region 150 is a region mainly composed of gallium nitride, and is an n -type region containing an n-type impurity at a relatively low concentration. The low concentration semiconductor region 150 is formed on the p-type semiconductor region 146. The low concentration semiconductor region 150 is interposed between the heterojunction surface 126 and the p-type semiconductor region 146. The low-concentration semiconductor region 150 is a region mainly composed of gallium nitride, and is an n -type region containing an n-type impurities at a relatively low concentration. The low concentration semiconductor region 150 is formed on the p-type semiconductor region 146. The low concentration semiconductor region 150 is involved between the heterojunction surface 126 and the p-type semiconductor region 146.
The source region 154 is formed across the GaN layer 122 and the AlGaN layer 124 and is exposed on the upper surface 120 a of the nitride semiconductor crystal 120. The source region 154 is an n + type region containing an n type impurity at a relatively high concentration. The source region 154 is formed under the source electrode 128 and extends to a position facing one end of the gate electrode 32. The source region 154 is formed across the GaN layer 122 and the AlGaN layer 124 and is exposed on the upper surface 120 a of the nitride semiconductor crystal 120. The source region 154 is an n + type region containing an n type impurities at a relatively high concentration. The source region 154 is formed under the source electrode 128 and extends to a position facing one end of the gate electrode 32.
The drain region 142 is formed across the GaN layer 122 and the AlGaN layer 124, and is exposed on the upper surface 120 a of the nitride semiconductor crystal 120. The drain region 142 is an n + type region containing an n type impurity at a relatively high concentration. The drain region 142 is formed under the drain electrode 130 and extends to a position facing the other end of the gate electrode 132. The drain region 142 is formed across the GaN layer 122 and the AlGaN layer 124, and is exposed on the upper surface 120 a of the nitride semiconductor crystal 120. The drain region 142 is an n + type region containing an n type impurity at a The drain region 142 is formed under the drain electrode 130 and extends to a position facing the other end of the gate electrode 132.

i型半導体領域152は、窒化ガリウム・アルミニウムを主材料とする領域であり、不純物が導入されていないi型の領域である。i型半導体領域152は、ゲート電極132の中間部と低濃度半導体領域150の間に位置している。i型半導体領域152と低濃度半導体領域150との間に位置するヘテロ接合面126には、ゲート電極132が上方から対向しているとともに、p型半導体領域146が下方から対向している。   The i-type semiconductor region 152 is a region mainly composed of gallium nitride / aluminum and is an i-type region into which no impurity is introduced. The i-type semiconductor region 152 is located between the intermediate portion of the gate electrode 132 and the low concentration semiconductor region 150. A gate electrode 132 faces the heterojunction surface 126 located between the i-type semiconductor region 152 and the low-concentration semiconductor region 150 from above, and a p-type semiconductor region 146 faces from below.

次に、半導体装置100の動作を説明する。半導体装置100では、ヘテロ接合面126が(10−10)結晶面上に形成されている。(10−10)結晶面は、その垂直方向に極性が変化しない無極性面である。そのことから、ヘテロ接合面126では、自発分極及びピエゾ分極が生じない。さらに、p型半導体領域146が、低濃度半導体領域150を介してヘテロ接合面126に対向している。それにより、ゲート電極132に電圧を印加していない状態では、低濃度半導体領域150に空乏層が形成され、その空乏層はヘテロ接合面126まで伸びている。その結果、ゲート電極132に電圧を印加していない状態では、ヘテロ接合面126における2次元電子ガス層の形成が禁止される。半導体装置100では、ゲート電極132に電圧が印加されていない状態で、ソース電極128とドレイン電極130の間の通電が禁止される。
一方、ゲート電極132に正の電圧を印加した状態では、低濃度半導体領域150に形成されていた空乏層が縮小し、ヘテロ接合面126に2次元電子ガス層が形成される。 On the other hand, when a positive voltage is applied to the gate electrode 132, the depletion layer formed in the low-concentration semiconductor region 150 shrinks, and a two-dimensional electron gas layer is formed on the heterojunction surface 126. ゲート電極132に正の電圧を印加すると、ヘテロ接合面126は多数の電子が走行可能な状態となり、ソース電極128とドレイン電極130の間が通電可能な状態となる。 When a positive voltage is applied to the gate electrode 132, the heterojunction surface 126 is in a state in which a large number of electrons can travel, and a state in which electricity can be passed between the source electrode 128 and the drain electrode 130. このように、半導体装置100は、安定したノーマリオフ動作を実現することができる。 In this way, the semiconductor device 100 can realize a stable normal-off operation. Next, the operation of the semiconductor device 100 will be described. In the semiconductor device 100, the heterojunction surface 126 is formed on the (10-10) crystal plane. The (10-10) crystal plane is a nonpolar plane whose polarity does not change in the vertical direction. Therefore, spontaneous polarization and piezoelectric polarization do not occur at the heterojunction surface 126. Further, the p-type semiconductor region 146 faces the heterojunction surface 126 with the low-concentration semiconductor region 150 interposed therebetween. Thereby, when no voltage is applied to the gate electrode 132, a depletion layer is formed in the low-concentration semiconductor region 150, and the depletion layer extends to the heterojunction surface 126. As a result, in the state where no voltage is applied to the gate electrode 132, the formation of the two-dimensional electron gas layer at the heterojunction surface 126 is prohibited. In the semiconductor device 100, energization betwee Next, the operation of the semiconductor device 100 will be described. In the semiconductor device 100, the heterojunction surface 126 is formed on the (10-10) crystal plane. The (10-10) crystal plane is a nonpolar plane whose polarity does Therefore, spontaneous polarization and piezoelectric polarization do not occur at the heterojunction surface 126. Further, the p-type semiconductor region 146 faces the heterojunction surface 126 with the low-concentration semiconductor region 150 respectively. When no voltage is applied to the gate electrode 132, a depletion layer is formed in the low-concentration semiconductor region 150, and the depletion layer extends to the heterojunction surface 126. As a result, in the state where no voltage is applied to the gate electrode 132, the formation of the two-dimensional electron gas layer at the heterojunction surface 126 is prohibited. In the semiconductor device 100, energization betwee n the source electrode 128 and the drain electrode 130 is prohibited while no voltage is applied to the gate electrode 132. n the source electrode 128 and the drain electrode 130 is prohibited while no voltage is applied to the gate electrode 132.
On the other hand, when a positive voltage is applied to the gate electrode 132, the depletion layer formed in the low concentration semiconductor region 150 is reduced, and a two-dimensional electron gas layer is formed on the heterojunction surface 126. When a positive voltage is applied to the gate electrode 132, the heterojunction surface 126 is in a state where a large number of electrons can travel, and the source electrode 128 and the drain electrode 130 can be energized. As described above, the semiconductor device 100 can realize a stable normally-off operation. On the other hand, when a positive voltage is applied to the gate electrode 132, the depletion layer formed in the low concentration semiconductor region 150 is reduced, and a two-dimensional electron gas layer is formed on the heterojunction surface 126. When a positive voltage is applied to the gate electrode 132, the heterojunction surface 126 is in a state where a large number of electrons can travel, and the source electrode 128 and the drain electrode 130 can be energized. As described above, the semiconductor device 100 can realize. a stable normally-off operation.

本明細書または図面に説明した技術要素は、単独であるいは各種の組み合わせによって技術的有用性を発揮するものであり、出願時の請求項に記載の組み合わせに限定されるものではない。
本明細書または図面に例示した技術は複数の目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 The techniques illustrated in this specification or drawings achieve a plurality of objectives at the same time, and achieving one of the objectives itself has technical usefulness. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing.
The technology illustrated in this specification or the drawings achieves a plurality of objects at the same time, and achieving one of the objects itself has technical utility. The technology illustrated in this specification or the drawings achieves a plurality of objects at the same time, and achieving one of the objects itself has technical utility.

実施例1の半導体装置の単位構造を示す模式図。 FIG. 3 is a schematic diagram illustrating a unit structure of the semiconductor device according to the first embodiment. 図1中のII−II線断面図。 II-II sectional view taken on the line in FIG. 実施例1の半導体装置の第1の製造過程を示す図。 FIG. 6 is a diagram showing a first manufacturing process of the semiconductor device of Example 1; 実施例1の半導体装置の第2の製造過程を示す図。 FIG. 6 is a diagram showing a second manufacturing process of the semiconductor device of Example 1; 実施例1の半導体装置の第3の製造過程を示す図。 FIG. 6 is a diagram showing a third manufacturing process of the semiconductor device of Example 1; 実施例1の半導体装置の第4の製造過程を示す図。 FIG. 6 is a diagram showing a fourth manufacturing process of the semiconductor device of Example 1; 実施例1の半導体装置の第5の製造過程を示す図。 FIG. 10 is a diagram showing a fifth manufacturing process of the semiconductor device of Example 1; 実施例1の半導体装置の第6の製造過程を示す図。 FIG. 10 is a diagram showing a sixth manufacturing process of the semiconductor device of Example 1; 実施例1の半導体装置の第7の製造過程を示す図。 FIG. 10 is a diagram showing a seventh manufacturing process of the semiconductor device of Example 1; 実施例2の半導体装置の単位構造を示す模式図。 FIG. 6 is a schematic diagram showing a unit structure of a semiconductor device of Example 2.

符号の説明Explanation of symbols

・10、100:半導体装置・20、120:窒化物半導体結晶・22、122:GaN層(第1層)
・24、124:AlGaN層・26、126:ヘテロ接合面・28、128:ソース電極・30、130:ドレイン電極・32、132:ゲート電極・34、134:ゲート絶縁膜・42、142:ドレイン領域・44、48、50、150:低濃度半導体領域・46、146:p型半導体領域・52、152:i型半導体領域・54、154:ソース領域10, 100: semiconductor device 20, 120: nitride semiconductor crystal 22, 122: GaN layer (first layer) 24, 124: AlGaN layer 26, 126: Heterojunction surface 28, 128: Source electrode 30, 130: Drain electrode 32, 132: Gate electrode 34, 134: Gate insulating film 42, 142: Drain Regions 44, 48, 50, 150: Low concentration semiconductor region 46, 146: p-type semiconductor region 52, 152: i-type semiconductor region 54, 154: Source region 10, 100: semiconductor device 20, 120: nitride semiconductor crystal 22, 122: GaN layer (first layer)
・ 24, 124: AlGaN layer ・ 26, 126: Heterojunction surface ・ 28, 128: Source electrode ・ 30, 130: Drain electrode ・ 32, 132: Gate electrode ・ 34, 134: Gate insulating film ・ 42, 142: Drain Region 44, 48, 50, 150: Low concentration semiconductor region 46, 146: p-type semiconductor region 52, 152: i-type semiconductor region 54, 154: Source region・ 24, 124: AlGaN layer ・ 26, 126: Heterojunction surface ・ 28, 128: Source electrode ・ 30, 130: Drain electrode ・ 32, 132: Gate electrode ・ 34, 134: Gate insulating film ・ 42, 142: Drain Region 44, 48, 50, 150: Low concentration semiconductor region 46, 146: p-type semiconductor region 52, 152: i-type semiconductor region 54, 154: Source region

Claims (8)

  1. 窒化物半導体結晶と、前記窒化物半導体結晶の上側表面に絶縁層を介して対向するゲート電極を備え、
    前記窒化物半導体結晶は、第1種類の窒化物半導体で構成された第1層と、前記第1層の上方に積層されているとともに第2種類の窒化物半導体で構成された第2層を備え、
    前記第1層の少なくとも一部には、p型の不純物を含むp型半導体領域が形成されており、
    前記第1層と前記第2層との境界面に形成されたヘテロ接合面は、(0001)結晶面に垂直な結晶面上に位置しており、
    前記へテロ接合面の少なくとも一部には、前記ゲート電極が上方から対向しているとともに、前記p型半導体領域が下方から対向していることを特徴とする半導体装置。 A semiconductor device characterized in that the gate electrode faces at least a part of the heterojunction surface from above, and the p-type semiconductor region faces from below. A nitride semiconductor crystal, and a gate electrode facing the upper surface of the nitride semiconductor crystal via an insulating layer, A nitride semiconductor crystal, and a gate electrode facing the upper surface of the nitride semiconductor crystal via an insulating layer,
    The nitride semiconductor crystal includes a first layer composed of a first type of nitride semiconductor and a second layer composed of a second type of nitride semiconductor and stacked above the first layer. Prepared, The nitride semiconductor crystal includes a first layer composed of a first type of nitride semiconductor and a second layer composed of a second type of nitride semiconductor and stacked above the first layer. Prepared,
    A p-type semiconductor region containing a p-type impurity is formed in at least a part of the first layer, A p-type semiconductor region containing a p-type impurities is formed in at least a part of the first layer,
    The heterojunction plane formed at the interface between the first layer and the second layer is located on a crystal plane perpendicular to the (0001) crystal plane, The heterojunction plane formed at the interface between the first layer and the second layer is located on a crystal plane perpendicular to the (0001) crystal plane,
    The semiconductor device according to claim 1, wherein the gate electrode is opposed to at least a part of the heterojunction surface from above and the p-type semiconductor region is opposed from below. The semiconductor device according to claim 1, wherein the gate electrode is opposed to at least a part of the heterojunction surface from above and the p-type semiconductor region is opposed from below.
  2. 前記p型半導体領域は、前記へテロ接合面から所定距離だけ離れた位置に形成されていることを特徴とする請求項1に記載の半導体装置。 The semiconductor device according to claim 1, wherein the p-type semiconductor region is formed at a position separated from the heterojunction surface by a predetermined distance.
  3. 前記へテロ接合面と前記p型半導体領域との間に、n型の不純物を含むn型半導体領域が形成されていることを特徴とする請求項2に記載の半導体装置。 The semiconductor device according to claim 2, wherein an n-type semiconductor region containing an n-type impurity is formed between the heterojunction surface and the p-type semiconductor region.
  4. 前記窒化物半導体結晶の上側表面に形成されているソース電極と、前記窒化物半導体結晶の下側表面に形成されているコレクタ電極をさらに備え、
    前記p型半導体領域は、前記ゲート電極の一部に前記ヘテロ接合面を介して対向しており、

    前記ゲート電極の他の一部の下方には、前記ヘテロ接合面から前記p型半導体領域の側方を通過して前記窒化物半導体結晶の下側表面に到る領域に、n型の不純物を含むn型半導体領域が形成されていることを特徴とする請求項3の半導体装置。 Below the other part of the gate electrode, an n-type impurity is placed in a region that passes from the heterojunction surface to the side of the p-type semiconductor region and reaches the lower surface of the nitride semiconductor crystal. The semiconductor device according to claim 3, wherein an n-type semiconductor region including the semiconductor region is formed. A source electrode formed on the upper surface of the nitride semiconductor crystal, and a collector electrode formed on the lower surface of the nitride semiconductor crystal, A source electrode formed on the upper surface of the nitride semiconductor crystal, and a collector electrode formed on the lower surface of the nitride semiconductor crystal,
    The p-type semiconductor region faces a part of the gate electrode via the heterojunction surface, The p-type semiconductor region faces a part of the gate electrode via the heterojunction surface,
    Under the other part of the gate electrode, an n-type impurity is introduced into a region that passes from the heterojunction surface to the side of the p-type semiconductor region and reaches the lower surface of the nitride semiconductor crystal. 4. The semiconductor device according to claim 3, wherein an n-type semiconductor region is formed. Under the other part of the gate electrode, an n-type excipient is introduced into a region that passes from the heterojunction surface to the side of the p-type semiconductor region and reaches the lower surface of the nitride semiconductor crystal. 4. The semiconductor device according to claim 3, wherein an n-type semiconductor region is formed.
  5. 前記p型半導体領域と前記n型半導体領域が側方から互いに隣接する境界面の大部分は、(0001)結晶面と角度を成す結晶面上に位置していることを特徴とする請求項4に記載の半導体装置。   5. The most part of the boundary surface where the p-type semiconductor region and the n-type semiconductor region are adjacent to each other from the side is located on a crystal plane that forms an angle with the (0001) crystal plane. A semiconductor device according to 1.
  6. 前記p型半導体領域と前記n型半導体領域が側方から互いに隣接する境界面の大部分は、(0001)結晶面に垂直な結晶面上に位置していることを特徴とする請求項5に記載の半導体装置。 6. The majority of a boundary surface where the p-type semiconductor region and the n-type semiconductor region are adjacent to each other from the side is located on a crystal plane perpendicular to the (0001) crystal plane. The semiconductor device described.
  7. 半導体装置の製造方法であって、
    主材料が第1種類の窒化物半導体であり、表面が(0001)結晶面に垂直な結晶面であり、少なくとも一部にp型の不純物を含むp型半導体領域が形成されている窒化物半導体結晶を用意する工程と、 A nitride semiconductor whose main material is a first-class nitride semiconductor, whose surface is a crystal plane perpendicular to the (0001) crystal plane, and in which a p-type semiconductor region containing p-type impurities is formed at least in part. The process of preparing crystals and
    前記窒化物半導体結晶の表面に、(0001)結晶面と角度を成す方向に伸びるトレンチを、前記p型半導体領域を貫通する深さで形成するトレンチ形成工程と、 A trench forming step of forming a trench extending in a direction forming an angle with the (0001) crystal plane on the surface of the nitride semiconductor crystal at a depth penetrating the p-type semiconductor region.
    少なくとも前記トレンチの内部に、第1種類の窒化物半導体を結晶成長させる第1結晶成長工程と、 A first crystal growth step in which a first type nitride semiconductor is crystal-grown at least inside the trench.
    第1結晶成長工程後の窒化物半導体結晶の表面に、第2種類の窒化物半導体を結晶成長させる第2結晶成長工程と、 A second crystal growth step of growing a second type of nitride semiconductor on the surface of the nitride semiconductor crystal after the first crystal growth step,
    第2結晶成長工程後の窒化物半導体結晶の表面に、p型半導体領域の少なくとも一部と対向するゲート電極を、ゲート絶縁膜を介在させて形成する工程と、 A step of forming a gate electrode facing at least a part of the p-type semiconductor region on the surface of the nitride semiconductor crystal after the second crystal growth step with a gate insulating film interposed therebetween.
    を備える半導体装置の製造方法。 A method for manufacturing a semiconductor device. A method for manufacturing a semiconductor device, comprising: A method for manufacturing a semiconductor device, comprising:
    A nitride semiconductor in which a main material is a first type nitride semiconductor, a surface is a crystal plane perpendicular to a (0001) crystal plane, and a p-type semiconductor region containing a p-type impurity is formed at least in part Preparing a crystal; A nitride semiconductor in which a main material is a first type nitride semiconductor, a surface is a crystal plane perpendicular to a (0001) crystal plane, and a p-type semiconductor region containing a p-type excipient is formed at least in part Preparing a crystal;
    Forming a trench extending on the surface of the nitride semiconductor crystal at a depth penetrating the p-type semiconductor region, the trench extending in a direction forming an angle with the (0001) crystal plane; Forming a trench extending on the surface of the nitride semiconductor crystal at a depth penetrating the p-type semiconductor region, the trench extending in a direction forming an angle with the (0001) crystal plane;
    A first crystal growth step for crystal growth of a first type nitride semiconductor at least inside the trench; A first crystal growth step for crystal growth of a first type nitride semiconductor at least inside the trench;
    A second crystal growth step of growing a second type of nitride semiconductor on the surface of the nitride semiconductor crystal after the first crystal growth step; A second crystal growth step of growing a second type of nitride semiconductor on the surface of the nitride semiconductor crystal after the first crystal growth step;
    Forming a gate electrode facing at least a part of the p-type semiconductor region on the surface of the nitride semiconductor crystal after the second crystal growth step with a gate insulating film interposed therebetween; Forming a gate electrode facing at least a part of the p-type semiconductor region on the surface of the nitride semiconductor crystal after the second crystal growth step with a gate insulating film involved crystal;
    A method for manufacturing a semiconductor device comprising: A method for manufacturing a semiconductor device comprising:
  8. 前記トレンチ形成工程では、(0001)結晶面に垂直に伸びるトレンチを形成することを特徴とする請求項7に記載の製造方法。 The manufacturing method according to claim 7, wherein in the trench formation step, a trench extending perpendicular to the (0001) crystal plane is formed.
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