JP5289818B2 - Group III nitride semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a group III nitride semiconductor device and a method for manufacturing the same. In particular, the present invention relates to a vertical group III nitride semiconductor device and a method for manufacturing the same.

  Patent Document 1 discloses a vertical group III nitride semiconductor device and a manufacturing method thereof. The semiconductor device includes an n-type group III nitride semiconductor layer and a p-type group III nitride semiconductor layer stacked on the surface thereof. A groove penetrating the p-type layer is formed in the p-type layer, and the n-type layer extends in the groove. The n-type layer extending in the groove of the p-type layer secures an n-channel current path extending in the vertical direction, and a vertical semiconductor device (a pair of electrodes are formed separately on both the front and back sides of the semiconductor substrate). Semiconductor device).

  In the technique of Patent Document 1, after forming a p-type group III nitride semiconductor layer over the entire surface of an n-type group III nitride semiconductor layer, a part of the surface of the p-type layer is etched to form an n-type layer A groove reaching the surface of the substrate is formed. Thereafter, an n-type group III nitride semiconductor layer is crystal-grown from the surface of the n-type layer exposed at the bottom of the groove, thereby forming an n-type layer extending in the p-type layer groove.

JP 2008-10781 A

  Group III nitrides tend to incorporate silicon (Si) and oxygen (O) into the crystal during crystal growth. At that time, silicon and oxygen are incorporated into the crystal when crystal growth is performed under the condition where the edge of the crystal growth layer is constrained, rather than when the crystal growth is performed under the condition where the edge of the crystal growth layer is not constrained. Cheap. That is, when an n-type group III nitride semiconductor layer existing below the p-type layer is grown, silicon and oxygen are not easily taken into the crystal, whereas the groove of the p-type layer When an n-type group III nitride semiconductor layer is grown in a crystal, silicon and oxygen are easily taken into the crystal. Silicon or oxygen taken into the crystal becomes an n-type impurity for the group III nitride.

In the manufacturing method of Patent Document 1, the n-type group III nitridation extending in the p-type groove is compared with the impurity concentration of the n-type group III nitride semiconductor layer existing below the p-type layer. The impurity concentration of the physical semiconductor layer is increased.
The n-type group III nitride semiconductor layer extending in the groove of the p-type layer is a region that becomes a current path when turned on, and is a region that is depleted and secured withstand voltage when turned off. If the impurity concentration of the n-type group III nitride semiconductor layer extending in the groove of the p-type layer is high, the depletion layer extending from the p-type layer into the n-type layer at the time of OFF is not sufficiently extended, An n-type layer that is not depleted remains. If a region that is not depleted remains, a potential difference cannot be secured in the depletion layer, and a reverse bias voltage is applied to the gate insulating film. A phenomenon that the gate insulating film is destroyed easily occurs.

  The present invention has been proposed to solve the above problems. That is, the present invention relates to an n-channel vertical group III nitride semiconductor device having an n-type group III nitride semiconductor layer penetrating a p-type layer, the n-type layer penetrating the p-type layer. Structure in which the depletion layer extends sufficiently from the p-type layer into the n-type layer at the time of off, and the depletion layer crosses the n-type layer that penetrates the p-type layer, and a method of manufacturing the structure I will provide a.

The present invention provides a n-type first group III nitride semiconductor layer having a first n-type impurity concentration and a surface of the surface of the first group III nitride semiconductor layer. out with are stacked in a range excluding the convex portion of the second group III nitride semiconductor layer of p-type are stacked to a position higher than the surface of the convex portion, with being laminated on the surface of the convex portion An n-type third group III nitride semiconductor layer that is stacked on the surface of the second group III nitride semiconductor layer and has a second n-type impurity concentration higher than the first n-type impurity concentration. The present invention relates to a method of manufacturing a vertical group III nitride semiconductor device. The p-type second group III nitride semiconductor layer has a recess that extends from the front surface to the back surface of the p-type second group III nitride semiconductor layer. The n-type first group is formed in the recess. The protrusion of the group III nitride semiconductor layer and the n-type third group III nitride semiconductor layer are filled , and the third group III nitride semiconductor is formed on the surface of the second group III nitride semiconductor layer. Layers are formed , and these n-type layers form an n-channel current path to realize a vertical semiconductor device.

The manufacturing method of the present invention includes a step of forming a convex portion by etching a range excluding a convex formation range on the surface of the first group III nitride semiconductor layer, and a first step in which the convex portion is formed. A step of forming a second group III nitride semiconductor layer on the surface of the group III nitride semiconductor layer, the second group formed on the surface of the first group III nitride semiconductor layer excluding the convex portion; Forming the group nitride semiconductor layer until the surface is higher than the surface of the convex portion, and etching the position where the convex portion is embedded in the surface of the second group III nitride semiconductor layer until the convex portion is exposed. Forming a recess, and forming a third group III nitride semiconductor layer in the recess of the second group III nitride semiconductor layer and on the surface of the second group III nitride semiconductor layer. The

When this method is used, an n-channel type current path includes an n-type first group III nitride semiconductor layer projecting portion and an n-type third group III nitride semiconductor layer formed in the recess. Formed with.
The convex portion of the n-type first group III nitride semiconductor layer can be grown under conditions where the end of the crystal growth layer is not constrained, and can be manufactured under conditions where impurities are not easily taken into the crystal. . The n-type third group III nitride semiconductor layer formed in the recess can be crystal-grown under the condition that the end of the crystal growth layer is constrained, and the impurity is easily taken into the crystal. Manufactured. Therefore, an n-channel current path can be formed by a structure in which two group III nitride semiconductor layers having different n-type impurity concentrations are stacked.

Of the n-type layer penetrating the p-type layer, in the region where the n-type impurity concentration is low, that is, the region formed by the convex portion of the first group III nitride semiconductor layer, the group III nitride semiconductor device is turned off. The depletion layer extends long and the depletion layer crosses. The depletion layer can handle the potential difference, and the potential difference acting on the gate insulating film is reduced. A region having a low n-type impurity concentration improves the insulation characteristics of the group III nitride semiconductor device.
Of the n-type layer penetrating the p-type layer, the region having a high n-type impurity concentration, that is, the third group III nitride semiconductor layer formed in the recess has a low resistance. Compensation for high resistance in a region where the n-type impurity concentration is low.
According to this method, it is possible to manufacture a vertical group III nitride semiconductor device having an n-channel current path that is depleted at the time of off and has a low resistance region.

According to the present invention, a semiconductor device comprising an n-type first group III nitride semiconductor layer, a p-type second group III nitride semiconductor layer, and an n-type third group III nitride semiconductor layer Is realized. Convex portions are formed on the surface of the n-type first group III nitride semiconductor layer. First group III nitride semiconductor layer of this has a first n-type impurity concentration. The p-type second group III nitride semiconductor layer is stacked in a range excluding the convex portion of the surface of the first group III nitride semiconductor layer, and is stacked up to a position higher than the surface of the convex portion. And a recess is formed. The surface of the convex portion of the n-type first group III nitride semiconductor layer is exposed at the bottom surface of the concave portion. The n-type third group III nitride semiconductor layer is stacked on the surface of the convex portion of the n-type first group III nitride semiconductor layer and on the surface of the second group III nitride semiconductor layer. The layers are stacked and have a second n-type impurity concentration higher than the first n-type impurity concentration.
In the group III nitride semiconductor device of the present invention, the third group III nitride semiconductor layer includes a first portion formed on the surface of the second group III nitride semiconductor layer, and a lower portion from the first portion. And a second portion formed in contact with the surface of the convex portion in the concave portion, and the second portion and the convex portion form a through layer penetrating the second group III nitride semiconductor layer. The width when the second portion of the third group III nitride semiconductor layer formed in the through layer is viewed in plan is different from the width when the projection is viewed in plan. Features.

In the semiconductor device of the present invention, the n-type first layer protrusion formed in the p-type second layer recess and the n-type first layer formed in the p-type second layer recess. An n-channel current path is formed by three layers. A vertical group III nitride semiconductor device having a current path that combines a region that is depleted when turned off and a region that has a low resistance when turned on is realized.
In addition, the width of the convex portion of the n-type first layer formed in the concave portion of the p-type second layer and the third layer of n-type formed in the concave portion of the p-type second layer Since the widths are different, the contact area between the first layer and the third layer does not change even if the relative position between the convex portion of the first layer and the third layer formed in the concave portion is shifted. Semiconductor devices with stable characteristics can be continuously manufactured.

If the width of the convex part of the first layer and the third layer formed in the concave part are the same, if the relative positions of the first layer and the third layer are shifted, the contact area between the first layer and the third layer is Change. For example, it is assumed that the width of both is 2 μm. When they are accurately overlapped, they come into contact with each other with a total length of 2 μm. On the other hand, when the relative positions of the first layer and the third layer are shifted by 1 μm, the contact length between the two is reduced to 1 μm. In contrast, it is assumed that one of the first layer and the third layer has a width of 4 μm and the other has a width of 2 μm. In this case, even if the two are accurately overlapped or shifted by 1 μm, the contact length between the two is always 2 μm and there is no change.
According to the semiconductor device of the present invention, semiconductor devices with stable characteristics can be mass-produced.

According to the present invention, in an n-channel vertical group III nitride semiconductor device having an n-type through layer penetrating a p-type layer, a low impurity concentration layer that is depleted when turned off, and a low on-resistance A through layer in which a high impurity concentration layer is stacked can be realized. A vertical group III nitride semiconductor device with high breakdown voltage and low resistance can be realized.
Further, the vertical group III nitride semiconductor in which the width of the convex portion of the first layer formed in the concave portion of the second layer and the width of the third layer can be made different and the characteristics are stabilized by making the width different. Mass production of equipment is possible.

Preferred features of the embodiments described below are listed.
(First Feature) The group III nitride semiconductor has a general formula of Al _X Ga _Y In _1-XY N (where 0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ 1-X−Y ≦ 1). Some aluminum gallium indium nitride is used.
(Second feature) After the electrode group is formed, heat treatment is performed.
(Third Feature) The n-type third group III nitride semiconductor layer is formed in the recess and on the surface of the p-type second group III nitride semiconductor layer. A fourth group III nitride semiconductor layer having a band gap larger than the band gap of the third group III nitride semiconductor layer is stacked on the top surface. A two-dimensional electron gas layer is formed at the interface of the group III nitride semiconductor layer.

(First embodiment)
1 to 6 show a method for manufacturing a vertical HEMT (High Electron Mobility Transistor) (Group III nitride semiconductor device) 100 of this embodiment.
First, as shown in FIG. 1, an n-type first gallium nitride layer (first group III nitride) is formed on the surface of an n-type gallium nitride substrate 2 by using a MOCVD (Metal Organic Chemical Vapor Deposition) method. The semiconductor layer 4 is crystal-grown. The first gallium nitride layer 4 is grown by heating the gallium nitride substrate 2 to 1050 ° C. in ammonia (NH ₃ ) and supplying trimethyl gallium ((CH ₃ ) ₃ Ga). The carrier concentration of the gallium nitride substrate 2 is 1 × 10 ¹⁸ cm ⁻³ . The carrier concentration of the first gallium nitride layer 4 is 2 × 10 ¹⁶ cm ⁻³ and the thickness is 5 μm.

  Next, as shown in FIG. 2, a first silicon oxide film 5 is formed in a range where the convex portions 4a are formed. Next, a part of the first gallium nitride layer 4 (a range that is not covered with the first silicon oxide film 5 and in which the second gallium nitride layer 6 exists after manufacture) is dry-etched, and a convex portion 4a is formed. The height of the convex portion is about 0.4 μm.

Next, as shown in FIG. 3, after removing the first silicon oxide film 5, a p-type second gallium nitride layer (second group III nitride is formed on the entire surface of the first gallium nitride layer 4. The semiconductor layer 6 is crystal-grown. The carrier concentration of the second gallium nitride layer 6 is 2 × 10 ¹⁷ cm ⁻³ and the thickness is 0.5 μm. The surface of the second gallium nitride layer 6 is higher than the convex portion 4 a, and the convex portion 4 a is embedded in the second gallium nitride layer 6.

Next, as shown in FIG. 4, the second silicon oxide film 7 is formed on a part of the surface of the second gallium nitride layer 6 and outside the range where the convex portions 4a are embedded. At this time, the width W2 of the opening 7a formed in the second silicon oxide film 7 is made wider than the width W1 of the convex portion 4a.
Next, the surface of the second gallium nitride layer 6 in a range where the second silicon oxide film 7 is not formed is dry-etched, and a concave portion 6a where the surface of the convex portion 4a of the first gallium nitride layer 4 is exposed on the bottom surface. Form. The etching depth is 0.2 μm. Since the width W2 of the opening 7a formed in the second silicon oxide film 7 is made wider than the width W1 of the convex portion 4a, the concave portion 6a is formed even if the horizontal positional relationship between the opening 7a and the convex portion 4a is shifted. The entire surface of the convex portion 4a is exposed on the bottom surface of.

Next, as shown in FIG. 5, after the second silicon oxide film 7 is removed, an n-type third gallium nitride layer is formed on the surface of the recess 6a and the second gallium nitride layer 6 using the MOCVD method. (Third group III nitride semiconductor layer) 8 is crystal-grown. The carrier concentration of the third gallium nitride layer 8 is 2 × 10 ¹⁶ cm ⁻³ . At this time, since the third gallium nitride layer 8a growing in the recess 6a grows under the condition that the end portion is constrained, silicon and oxygen are easily taken in, and the n-type carrier concentration is higher than that in other regions. An n-type through layer penetrating the p-type second gallium nitride layer 6 by the convex portion 4a and the third gallium nitride layer 8a formed in the concave portion 6a formed in the second gallium nitride layer 6 9 is formed.

Next, as shown in FIG. 6, an aluminum gallium indium nitride layer 10 is formed on the surface of the third gallium nitride layer 8. The general formula of the aluminum gallium indium nitride layer 10 is Al _X Ga _Y In _1-XY N (where 0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ 1-X−Y ≦ 1). Here, a material satisfying the relationship that the band gap of the aluminum gallium nitride indium layer 10 is wider than the band gap of the third gallium nitride layer 8 is selected. Next, a third silicon oxide film 11 is formed on the surface of the aluminum gallium indium nitride layer 10. The thickness of the third silicon oxide film 11 is 50 nm.

  Next, as shown in FIG. 7, after etching a part of the third silicon oxide film 11, a part of the aluminum gallium indium nitride layer 10, and a part of the third gallium nitride layer 8, a source electrode is formed on the etched part. 12 is formed. Further, the drain electrode 16 is formed on the back surface of the gallium nitride substrate 2. Further, the gate electrode 14 is formed on a part of the surface of the remaining third silicon oxide film 11 with a width larger than the width of the third gallium nitride layer 8a formed in the recess 6a. The remaining third silicon oxide film 11 is used as a gate insulating film. Furthermore, good ohmic contact can be obtained by performing heat treatment. As a result, the HEMT 100 can be manufactured.

Next, the operation of the HEMT 100 will be described.
In the HEMT 100, when a predetermined voltage is applied to the gate electrode 14, a two-dimensional electron gas layer (2DEG) is formed at the interface 8b between the third gallium nitride layer 8 and the aluminum gallium indium nitride layer 10. In the HEMT 100, by using the two-dimensional electron gas layer to move electrons, the electron mobility can be increased and high-speed operation can be realized.

  In the HEMT 100, two gallium nitride layers 4a and 8a having different n-type impurity concentrations are mixed in the through layer 9 serving as a current path. That is, the through layer 9 is formed by the convex portion 4 a of the first gallium nitride layer 4 and the third gallium nitride layer 8 a formed in the concave portion 6 a of the second gallium nitride layer 6. A region having a low n-type impurity concentration in the through layer 9, that is, the convex portion 4 a of the first gallium nitride layer 4 is depleted when the HEMT 100 is turned off. The through-layer 9 has a high n-type impurity concentration, that is, the third gallium nitride layer 8a formed in the recess 6a of the second gallium nitride layer 6 has a low on-resistance. In the HEMT 100, a part of the through layer 9 serving as a current path when de-energized is depleted, and the through layer 9 has a low resistance region that lowers the on-resistance.

As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
For example, although the vertical HEMT is described in the embodiment, a vertical FET (Field Effect Transistor) may be used.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

Step (1) of the method for producing HEMT 100 according to the first embodiment of the present invention is shown. The process (2) of the method of manufacturing HEMT100 is shown. The process (3) of the method of manufacturing HEMT100 is shown. The process (4) of the method of manufacturing HEMT100 is shown. The process (5) of the method of manufacturing HEMT100 is shown. The process (6) of the method of manufacturing HEMT100 is shown. The process (7) of the method of manufacturing HEMT100 is shown.

Explanation of symbols

2: Gallium nitride substrate 4: First gallium nitride layer (first group III nitride semiconductor layer)
4a: convex portion 5: first silicon oxide film 6: second gallium nitride layer (second group III nitride semiconductor layer)
6a: recess 7: second silicon oxide film 7a: opening 8: third gallium nitride layer (third group III nitride semiconductor layer)
8a: third gallium nitride layer 8b formed in the recess 6a: interface 9 between the third gallium nitride layer 8 and aluminum gallium indium nitride layer 10: through layer 10: aluminum gallium indium nitride layer 11: third Silicon oxide film 12: source electrode 14: gate electrode 16: drain electrode 100: HEMT (group III nitride semiconductor device)

Claims (2)

A n-type first group III nitride semiconductor layer having a convex portion formed on the surface and having a first n-type impurity concentration ;
The p-type second group III nitride is stacked in a range excluding the convex portion of the surface of the first group III nitride semiconductor layer and is stacked up to a position higher than the surface of the convex portion. A semiconductor layer,
The second n-type impurity concentration is higher than the first n-type impurity concentration. The second n-type impurity concentration is higher than the first n-type impurity concentration. A method of manufacturing a vertical group III nitride semiconductor device comprising an n-type third group III nitride semiconductor layer,
Etching the range of the surface of the first group III nitride semiconductor layer excluding the formation range of the protrusions to form the protrusions;
Forming the second group III nitride semiconductor layer on the surface of the first group III nitride semiconductor layer on which the convex portion is formed, the step of forming the first group III nitride semiconductor layer; Forming the second group III nitride semiconductor layer formed on the surface in a range excluding the convex portion until it is higher than the surface of the convex portion;
Etching the position where the convex portion is embedded in the surface of the second group III nitride semiconductor layer until the convex portion is exposed to form a concave portion;
Forming the third group III nitride semiconductor layer in the recess of the second group III nitride semiconductor layer and on the surface of the second group III nitride semiconductor layer. A method for manufacturing a vertical group III nitride semiconductor device. A n-type first group III nitride semiconductor layer having a convex portion formed on the surface and having a first n-type impurity concentration ;
The first group III nitride semiconductor layer is laminated in a range excluding the convex part, and is laminated to a position higher than the surface of the convex part, and the surface of the convex part is on the bottom surface. A p-type second group III nitride semiconductor layer in which an exposed recess is formed;
The second n-type impurity concentration is higher than the first n-type impurity concentration. The second n-type impurity concentration is higher than the first n-type impurity concentration. an n-type third group III nitride semiconductor layer,
The third group III nitride semiconductor layer includes a first portion formed on a surface of the second group III nitride semiconductor layer, and a convex portion extending downward from the first portion in the recess. A second part formed in contact with the surface of
The second portion and the convex portion form a through layer that penetrates the second group III nitride semiconductor layer,
A vertical group III nitride semiconductor device characterized in that a width when the second portion formed in the through layer is viewed in plan is different from a width when the projection is viewed in plan .

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