JP5252813B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device using a nitride semiconductor crystal.

  Patent Document 1 discloses a semiconductor device using a nitride semiconductor crystal. This semiconductor device has a nitride semiconductor crystal and a gate electrode facing the upper surface of the nitride semiconductor crystal via an insulating layer. The nitride semiconductor crystal includes a first layer composed of a first type nitride semiconductor (gallium nitride) and a second type nitride semiconductor (gallium nitride / aluminum) laminated on the upper side of the first layer. It has the 2nd layer comprised by these. Since the first layer and the second layer have different band gaps, the interface between them is a heterojunction surface. A gate electrode is opposed to a part of the heterojunction surface between the first layer and the second layer from one side.

In a heterojunction field effect transistor, when a heterojunction plane that becomes a channel is formed on a (0001) crystal plane, a high-density two-dimensional electron gas layer is formed on the heterojunction plane due to the generation of an electric field due to the piezoelectric effect and spontaneous polarization. It is formed. When a high-density two-dimensional electron gas layer is formed on the heterojunction surface, even when no voltage is applied to the gate electrode, the heterojunction surface is in a state where a large number of electrons can travel. Turns on. That is, the semiconductor device exhibits normally-on behavior.
On the other hand, in the semiconductor device of Patent Document 1, a heterojunction surface to be a channel is formed on the (11-20) crystal plane. The (11-20) crystal plane is a nonpolar plane whose polarity does not change in the thickness direction. Therefore, spontaneous polarization and piezoelectric polarization do not occur on the heterojunction plane formed on the (11-20) crystal plane, and the density of the two-dimensional electron gas layer is significantly reduced. As a result, in the state where no voltage is applied to the gate electrode, the traveling of electrons on the heterojunction surface is suppressed, and the semiconductor device is turned off. In Patent Document 1, it is reported that almost normally-off operation characteristics have been confirmed.

  Here, “-” added before “2” in the notation of (11-20) generally indicates “bar” to be added to the upper part of “2”. In the specification and claims of this application, the crystal plane and the crystal axis are represented in the same manner. Unless otherwise specified, for example, the expression (1-100) crystal plane includes a (1-100) crystal plane and an equivalent crystal plane. Similarly, for example, the expression <11-20> crystal axis includes a <11-20> crystal axis and a crystal axis equivalent thereto.

JP 2006-324465 A

In the manufacturing process of the semiconductor device of Patent Document 1, it is necessary to grow a (11-20) crystal axis oriented nitride semiconductor layer on a sapphire substrate whose main surface is a (1102) crystal plane. However, such crystal growth is very difficult, and a good (11-20) crystal plane does not always appear on the surface of the nitride semiconductor layer on which the crystal has been grown. Although the semiconductor device of Patent Document 1 has a structure that can be expected to be normally off, there is a problem that it is difficult to actually realize the structure.
The present invention solves the above problems. The present invention provides a technique for realizing a normally-off operation and realizing a semiconductor device that is relatively easy to manufacture.

A semiconductor device embodied by the present invention includes a nitride semiconductor crystal whose upper surface is a (0001) crystal plane and a gate electrode. At least one trench is formed on the upper surface of the nitride semiconductor crystal. The gate electrode is opposed to at least the side surface of the trench via an insulating layer. At least a part of the side surface of the trench is a (11-22) crystal plane or a (1-101) crystal plane.
Here, the upper surface of the nitride semiconductor crystal is not intended to be a surface positioned vertically upward, but is defined for the sake of convenience in order to clarify the positional relationship of each component of the semiconductor device. In the present specification and claims, of the plurality of surfaces of the nitride semiconductor crystal, the surface on which the gate electrode is disposed is defined as the upper surface, and the surface facing the upper surface is defined as the lower surface. A direction from the lower surface to the upper surface is expressed as upward, a direction from the upper surface to the lower surface is expressed as downward, and a direction parallel to the upper surface and the lower surface is expressed as side.

This semiconductor device has a structure in which a (11-22) crystal plane or a (1-101) crystal plane is formed on a side surface of a trench, and a gate electrode is opposed to the side surface of the trench. As a result, a channel on which carriers travel is formed on the (11-22) crystal plane or the (1-101) crystal plane. The (11-22) crystal plane and the (1-101) crystal plane are, for example, semipolar planes with a small change in polarity in the thickness direction compared to the (0001) crystal plane. Therefore, in the channel formed on the (0001) crystal plane, the generation of an electric field due to the piezo effect and spontaneous polarization is suppressed, and the density of the two-dimensional electron gas layer is significantly reduced. As a result, in a state where no voltage is applied to the gate electrode, electron travel is suppressed in the channel, and the semiconductor device is turned off.
A nitride semiconductor crystal whose main surface is a (0001) crystal plane has an advantage that it is relatively easy to manufacture and it is easy to obtain a homogeneous crystal. Since the semiconductor device according to the present invention uses a nitride semiconductor crystal whose surface is a (0001) crystal plane, it can be easily manufactured.

In the semiconductor device described above, the nitride semiconductor crystal is composed of the first layer composed of the first type nitride semiconductor and the second layer nitride semiconductor which is laminated above the first region. A second layer is preferably provided. In this case, it is preferable that at least a part of the boundary surface between the first layer and the second layer is parallel to the side surface of the trench.
In this semiconductor device, the heterojunction planes of the first layer and the second layer are formed on the (11-22) crystal plane or the (1-101) crystal plane, and a channel is formed along the heterojunction plane. The In a state where a voltage is applied to the gate electrode, a high-density two-dimensional electron gas layer is formed along the heterojunction surface, and a channel capable of traveling a large number of electrons is formed. Thereby, the on-resistance of the semiconductor device is significantly reduced.

In the case of adopting the above structure, it is preferable that the first type nitride semiconductor is gallium nitride and the second type nitride semiconductor is gallium nitride / aluminum.
With a combination of these materials, a heterojunction surface suitable for the channel is formed due to an appropriate band gap difference.

In the above semiconductor device, it is preferable that the trench extends in parallel with the <1-100> crystal axis, and a side surface of the trench is a (11-22) crystal plane.
Alternatively, it is preferable that the trench extends in parallel with the <11-20> crystal axis, and the side surface of the trench is a (1-101) crystal plane.
With these configurations, the (11-22) crystal plane or the (1-101) crystal plane can be formed wider on the side surface of the trench.

  The semiconductor device according to the present invention can be manufactured by a manufacturing method described below. This manufacturing method includes a step of preparing a nitride semiconductor crystal whose upper surface is a (0001) crystal plane, and a <1-100> crystal axis or a <11-20> crystal axis on the upper surface of the nitride semiconductor crystal. Forming a trench extending parallel to the trench, and heat-treating the nitride semiconductor crystal in which the trench is formed in an atmosphere of gas containing ammonia, and forming (11-22) crystal on at least a part of the side surface of the trench A heat treatment step for forming a plane or a (1-101) crystal plane, and an electrode formation step for forming a gate electrode facing the side surface of the trench through an insulating layer.

When a nitride semiconductor crystal is heat-treated in an atmosphere containing ammonia, group III element atoms and nitrogen atoms move to minimize the surface energy of the crystal, and the surface of the nitride semiconductor crystal is relatively The surface energy changes to a small crystal plane. Therefore, when a trench is formed in the (0001) crystal plane of the nitride semiconductor crystal and the nitride semiconductor after the trench formation is heat-treated in a reaction gas atmosphere containing ammonia, the (11-22) crystal plane or A (1-101) crystal plane can be formed. According to this method, a uniform (11-22) crystal plane or (1-101) crystal plane can be easily formed on the surface of the nitride semiconductor crystal.
According to this manufacturing method, the above-described semiconductor device can be easily manufactured from a nitride semiconductor crystal having a (0001) crystal plane on its surface without performing special crystal growth.

The manufacturing method includes a step of crystal-growing a second layer made of the second type nitride semiconductor on the (11-22) crystal plane or the (1-101) crystal plane formed on the side surface of the trench. It is preferable to further provide.
Thereby, a semiconductor device in which a heterojunction plane is formed on the (11-22) crystal plane or the (1-101) crystal plane and a channel is formed along the heterojunction plane can be manufactured.

When the second layer is stacked on the side surface of the trench, the crystal surface of gallium nitride is exposed on the side surface of the trench, and the second type nitride semiconductor to be stacked is preferably gallium nitride / aluminum.
By combining these materials, a heterojunction surface suitable for a channel can be formed with an appropriate difference in band gap.

  According to the present invention, a semiconductor device using a nitride semiconductor crystal, which realizes a normally-off operation and is relatively easy to manufacture, is realized.

First, the main features of the embodiments described below are listed.
(Feature 1) When the nitride semiconductor crystal after the trench formation is heat-treated, it is preferable to form a gallium nitride / aluminum layer on the upper surface of the nitride semiconductor crystal (excluding the trench formation range). Since the gallium nitride / aluminum layer has a high degree of bonding and atoms do not leave during heat treatment, it functions as a mask for maintaining the upper surface of the nitride semiconductor crystal.
(Feature 2) When a trench extending parallel to the <1-100> crystal axis is formed on the upper surface of the nitride semiconductor substrate, a (11-22) crystal plane can be formed on the side surface of the trench by subsequent heat treatment. . When a trench extending parallel to the <11-20> crystal axis is formed on the upper surface of the nitride semiconductor substrate, a (1-101) crystal plane can be formed on the side surface of the trench by subsequent heat treatment (feature 3). The semiconductor device includes a source electrode formed on the upper surface of the nitride semiconductor crystal and a drain electrode formed on the lower surface of the nitride semiconductor crystal.

Example 1
FIG. 1 schematically shows a cross-sectional view of a main part of a semiconductor device 10 according to the first embodiment. FIG. 1 schematically shows a unit structure of the semiconductor device 10. In the semiconductor device 10, the unit structure shown in FIG. 1 is repeatedly formed in the left-right direction of FIG.

The semiconductor device 10 includes a nitride semiconductor crystal 20. The nitride semiconductor crystal 20 is a crystal of a nitride semiconductor and has a hexagonal crystal structure. The upper surface 20a of the nitride semiconductor crystal 20 is a (0001) crystal plane, and the lower surface 20b is a (000-1) crystal plane.
The nitride semiconductor crystal 20 includes a GaN layer (first layer) 22, 24, 26 made of gallium nitride (GaN), an AlGaN layer (second layer) 27 made of gallium nitride / aluminum (AlGaN), 28. The AlGaN layers 27 and 28 are stacked above the GaN layers 22, 24 and 26. Since the GaN layers 22, 24 and 26 and the AlGaN layers 27 and 28 have different band gaps, the boundary surface 30 between the GaN layers 22, 24 and 26 and the AlGaN layers 27 and 28 is a heterojunction surface. Hereinafter, the interface 30 between the GaN layers 22, 24, 26 and the AlGaN layers 27, 28 may be simply referred to as a heterojunction surface 30.

  A trench 46 is formed in the upper surface 26 a of the GaN layer (first layer) 22, 24, 26. FIG. 2 shows an enlarged structure related to the trench 46. As shown in FIGS. 1 and 2, the trench 46 extends in parallel to the <1-100> crystal axis (in the depth direction of FIG. 1). The trench 46 has a substantially V-shaped cross section, and a pair of side surfaces 46a of the trench 46 is a <11-22> crystal plane. The side surface 46a and the bottom surface 46b of the trench 46 form an angle of about 120 degrees. Further, the side surface 46a of the trench 46 and the upper surface 26a of the GaN layers (first layer) 22, 24, 26 also form an angle of approximately 120 degrees.

As shown in FIGS. 1 and 2, a gate electrode 36 and a gate insulating film 37 are formed inside the trench 46. The gate insulating film 37 is formed on the surface (side surface 46 a and bottom surface 46 b) of the trench 46 and on the upper surface 26 a of the GaN layers (first layers) 22, 24, 26 located on both sides of the trench 46. . The gate electrode 36 is formed on the gate insulating film 37. The gate electrode 36 faces the side surface 46 a and the bottom surface 46 b of the trench 46 through the gate insulating film 37. The material forming the gate insulating film 37 and the gate electrode 36 is not particularly limited. In this embodiment, the gate insulating film 37 is formed of silicon oxide (SiO ₂ ), and the gate electrode 36 is formed of polycrystalline silicon (Poly Si).

  The GaN layers 22, 24, and 26 of the nitride semiconductor crystal 20 include the GaN substrate layer 22, the high-resistance GaN layer 24, the p-type GaN layer 26, and the source region according to the type and concentration of the introduced impurity. 42. The AlGaN layers 27 and 28 can be divided into a first AlGaN layer 27 and a second AlGaN layer 28 according to the content ratios of gallium and aluminum. The source region 42 extends to the first AlGaN layer 27 beyond the heterojunction surface 30.

The GaN substrate layer 22 is located in the lowermost layer portion of the nitride semiconductor crystal 20. The GaN substrate layer 22 is an n-type semiconductor region containing n-type impurities. The GaN substrate layer 22 may be an i-type semiconductor region into which no impurity is introduced.
The high resistance GaN layer 24 is stacked above the GaN substrate layer 22. The high resistance GaN layer 24 is an n ⁻ type semiconductor region containing an n type impurity at a relatively low concentration. In this embodiment, silicon (Si) is used as an n-type impurity, and its concentration is adjusted to about 1 × 10 ¹⁶ cm ⁻³ .

The p-type GaN layer 26 is stacked above the high resistance GaN layer 24. The p-type GaN layer 26 is a p-type semiconductor region containing p-type impurities. In this embodiment, magnesium (Mg) is used as a p-type impurity, and its concentration is adjusted to about 5 × 10 ¹⁹ cm ⁻³ . The p-type GaN layer 26 is formed above part of the high-resistance GaN layer 24. The p-type GaN layer 26 is located below the upper surface 20 a of the nitride semiconductor substrate 20 (excluding the formation range of the trench 46) and is located on the side of the trench 46. A part of the high-resistance GaN layer 24 is interposed between the p-type GaN layer 26 and the side surface 46 a of the trench 46.
The source region 42 is formed above part of the p-type GaN layer 26. A part of the source region 42 is located below the gate electrode 36. The source region 42 is an n-type semiconductor region containing an n-type impurity at a relatively high concentration. In this embodiment, silicon (Si) is used as an n-type impurity, and its concentration is adjusted to about 3 × 10 ¹⁸ cm ⁻³ .

The first AlGaN layer 27 is composed of gallium nitride aluminum (Al _y Ga _1-y N) having a gallium and aluminum content ratio of y: 1-y. In this embodiment, y is adjusted to 0.3. The first AlGaN layer 27 is stacked above the p-type GaN layer 26, and is formed along the upper surfaces 26a of the GaN layers (first layers) 22, 24, 26 (excluding the formation range of the trench 46). Yes.
The second AlGaN layer 28 is made of gallium aluminum nitride (Al _x Ga _1-x N) having a gallium and aluminum content ratio of x: 1-x. In the present embodiment, y is adjusted to 0.3 as with the first AlGaN layer 27. The second AlGaN layer 28 is laminated with a substantially constant layer thickness over substantially the entire upper surface 26a of the GaN layers (first layer) 22, 24, 26 and the surfaces 46a, 46b of the trench 46.

With the above configuration, in the nitride semiconductor crystal 20, the heterojunction surface 30 that is a boundary surface between the GaN layers 22, 24, 26 and the AlGaN layers 27, 28 is formed of the GaN layers (first layers) 22, 24, 26. The upper surface 26a and the surfaces 46a and 46b of the trench 46 extend substantially in parallel. As described above, the side surface 46a of the trench 46 is a (11-22) crystal plane. Therefore, the range parallel to the trench side surface 46a of the heterojunction surface 30 is located on the (11-22) crystal plane.
In a range parallel to the trench side surface 46a of the heterojunction plane 30, that is, a range located on the (11-22) crystal plane of the heterojunction plane 30, the gate electrode 36 is opposed from one side, and is p-type. The semiconductor region 26 is opposed from the other side through the high-resistance GaN layer 24.

The source electrode 32 is disposed on the upper surface 20a of the nitride semiconductor substrate 20 (excluding the formation range of the trench 46). On the upper surface 20a of the nitride semiconductor crystal 20, a plurality of source electrodes 32 and a plurality of gate electrodes 36 are alternately arranged in the left-right direction in FIG. A drain electrode 34 is formed on the lower surface 20 b of the nitride semiconductor crystal 20.
The material which comprises the source electrode 28 and the drain electrode 30 is not specifically limited, For example, it can comprise using a metal. In the present embodiment, the source electrode 28 and the drain electrode 30 are constituted by a laminate in which titanium (Ti) and aluminum (Al) are laminated.

  Next, the operation of the semiconductor device 10 will be described. In the semiconductor device 10, a part of the heterojunction surface 30 is formed in parallel to the trench side surface 46a. That is, a part of the heterojunction plane 30 is formed on the (11-22) crystal plane. Unlike the (0001) crystal plane, the (11-22) crystal plane is a semipolar plane with little change in polarity in the vertical direction. Therefore, in the heterojunction plane 30 formed on the (11-22) crystal plane, for example, the density of the two-dimensional electron gas layer is significantly reduced as compared with the case where the heterojunction plane 30 is formed on the (0001) crystal plane. To do. When no voltage is applied to the gate electrode 36, the depletion layer extends from the boundary surface between the high-resistance GaN layer 24 and the p-type GaN layer 26, and the depletion layer reaches the heterojunction surface 30. As a result, in the state where no voltage is applied to the gate electrode 36, the formation of the two-dimensional electron gas layer is prohibited in a range parallel to at least the side surface 46 a of the trench 46 of the heterojunction surface 30. In a state where no voltage is applied to the gate electrode 36, the electrons are reliably prohibited from traveling along the heterojunction surface 30, and the source electrode 32 and the drain electrode 34 are electrically disconnected.

  On the other hand, when a positive voltage is applied to the gate electrode 36, the depletion layer formed in the high-resistance GaN layer 24 is reduced, and a two-dimensional electron gas layer is formed on the heterojunction surface 30. By applying a positive voltage to the gate electrode 36, a channel through which a large number of electrons can travel is formed along the heterojunction surface 30, and the source electrode 32 and the drain electrode 34 can be energized. Thus, the semiconductor device 10 can realize a stable normally-off operation.

  The threshold voltage (gate voltage required to turn on) of the semiconductor device 10 is the impurity concentration of the high-resistance GaN layer 24, the impurity concentration of the p-type GaN layer 26, the position and size of the p-type GaN layer 26, the trench 46 It varies depending on the depth. Therefore, the semiconductor device 10 having a desired threshold voltage can be realized by appropriately changing these settings.

(Manufacturing method of the semiconductor device 10)
Next, a method for manufacturing the semiconductor device 10 will be described.
First, as shown in FIG. 3, a gallium nitride substrate 22 (which will later become a GaN substrate layer 22) is prepared, whose main material is gallium nitride and whose main surface is a (0001) crystal plane. Next, an n ⁻ -type gallium nitride layer 24 (which later becomes a high-resistance GaN layer 24) is grown on the gallium nitride substrate 22 by using a MOCVD (Metal Organic Chemical Vapor Deposition) method. Next, a p-type gallium nitride layer 26 (which will later become a p-type GaN layer 26) is grown on the n ⁻ -type gallium nitride layer 24 by MOCVD. Next, a gallium nitride / aluminum layer 27 (which will later become the first AlGaN layer 27) is grown on the p-type gallium nitride layer 26 by MOCVD.
Next, silicon is implanted into a part of the upper surface 20a of the nitride semiconductor crystal 20 obtained by the crystal growth by an ion implantation method to form the source region. Note that activation by heat treatment is performed after silicon is implanted by an ion implantation method. The semi-finished product 10a shown in FIG. 3 is obtained by the above process.

Next, as shown in FIG. 4, using the lithography technique and the RIE technique, a trench 46 that penetrates the source region 42 and the p-type gallium nitride layer 26 and reaches the n ⁻ -type gallium nitride layer 24 is formed. . The mask 60 used at this time can be formed of, for example, silicon oxide. The trench 46 is formed in parallel to the <1-100> crystal axis. The semi-finished product 10b shown in FIG. 4 is obtained by the above process. After the trench 46 is formed, the mask 60 is removed. Note that the side surface 46a and the bottom surface 46b of the trench 46 at this stage do not have a specific crystal plane.

Next, the nitride semiconductor substrate 20 after the formation of the trench 46 shown in FIG. 4 is subjected to heat treatment in an atmosphere of a reactive gas containing ammonia (NH ₃ ). The temperature of this heat treatment is about 1050 ° C., and the time is 10 minutes. By this heat treatment, movement of nitrogen atoms and gallium atoms occurs on the side surfaces 46a and bottom surfaces 46b of the trenches 46 where the gallium nitride layers 24 and 26 are exposed so that the surface energy is minimized. As a result, as shown in FIG. 5, the side surface 46a of the trench 46 becomes a (11-22) crystal plane with relatively low surface energy, and the bottom surface 46b of the trench 46 becomes a (0001) crystal plane. The semi-finished product 10c shown in FIG. 5 is obtained by the above process.
In this heat treatment, nitrogen atoms and gallium atoms mainly move from the bottom surface 46 b of the trench 46 to the side surface 46 b of the trench 46. That is, when viewed macroscopically, the n ⁻ -type gallium nitride layer 24 exposed on the bottom surface 46 b of the trench 46 is stacked on the p-type gallium nitride layer 26 exposed on the side surface 46 a of the trench 46. Move to. As a result, the side surface 46 a of the trench 46 is mainly constituted by the n-type gallium nitride layer 24.
Note that, since the gallium nitride / aluminum crystal has a stronger bonding force than the gallium nitride crystal, the movement of atoms from the gallium nitride / aluminum layer 27 does not substantially occur. Therefore, the shape of the upper surface 20a of the nitride semiconductor substrate 20 is maintained before and after the heat treatment.

Next, as shown in FIG. 6, the MOCVD method is used to form a gallium nitride / aluminum layer 28 (to be a second AlGaN layer 28 later) on the upper surface 20a of the nitride semiconductor substrate 20 and the inner surfaces 46a and 46b of the trench. ) Is grown. Thereby, the semi-finished product 10d shown in FIG. 6 is obtained.
Next, as shown in FIG. 7, a gate insulating film 37 and a gate electrode 36 are sequentially formed on the gallium nitride / aluminum layer 28. Thereby, the semi-finished product 10e shown in FIG. 7 is obtained.
Next, the source electrode 32 is formed on the upper surface 20 a of the nitride semiconductor crystal 20, and the drain electrode 34 is formed on the lower surface 20 b of the nitride semiconductor crystal 20. When forming the source electrode 32, a hole exposing the source region 42 is formed in the gallium nitride / aluminum layer 28, and the source electrode 32 is formed so as to be in contact with the source region 34. Through the above steps, the semiconductor device 10 shown in FIG. 1 can be manufactured.

  As described above, the semiconductor device 10 can be formed from the gallium nitride substrate 22 whose main surface is the (0001) crystal plane. The gallium nitride substrate 22 whose main surface is a (0001) crystal plane is relatively easy compared with, for example, a gallium nitride substrate whose main surface is a (11-22) crystal plane or a (1-101) crystal plane. Can be manufactured. According to the technique described in this embodiment, the (11-22) crystal plane or (1-1-) crystal plane can be used without using a gallium nitride substrate whose main surface is the (11-22) crystal plane or the (1-101) crystal plane. 101) The semiconductor device 10 having the heterojunction plane 30 on the crystal plane can be manufactured.

The semiconductor device 10 according to the first embodiment has been described in detail above. However, the configuration related to the trench 46 can be changed as shown in FIG. That is, as shown in FIG. 8, the trench 46 may be formed in parallel to the <11-20> crystal axis, and the pair of side surfaces 46a may be (1-101) crystal planes. The (1-101) crystal plane is a semipolar plane similar to the (11-22) crystal plane. Therefore, even when the side surface 46a of the trench 46 is a (1-101) crystal plane, the semiconductor device 10 can realize a stable normally-off operation.
The trench 46 shown in FIG. 8 can be formed as follows. That is, in the manufacturing method of the semiconductor device 10 described above, when the trench 46 is formed on the upper surface 20a of the nitride semiconductor crystal 20, the trench 46 that forms the trench 46 extending in parallel to the <11-20> crystal axis is formed <11-20> When formed parallel to the crystal axis, a subsequent heat treatment forms a (1-101) crystal plane on the side surface 46a of the trench 46, and the trench 46 shown in FIG. 8 is obtained.

(Example 2)
FIG. 9 schematically illustrates a cross-sectional view of a main part of the semiconductor device 100 according to the first embodiment. FIG. 9 schematically shows a unit structure of the semiconductor device 100. In the semiconductor device 100, the unit structure shown in FIG. 1 is repeatedly formed in the left-right direction of FIG.

The semiconductor device 100 includes a nitride semiconductor crystal 120. The upper surface 120a of the nitride semiconductor crystal 120 is a (0001) crystal plane, and the lower surface 120b is a (000-1) crystal plane.
The nitride semiconductor crystal 120 includes GaN layers (first layers) 122, 124, and 126 made of gallium nitride (GaN), and an AlGaN layer 127 mainly composed of gallium nitride and aluminum (AlGaN). The AlGaN layer 127 is stacked above the GaN layers 122, 124, and 216.

  A trench 146 is formed in the upper surface 126a of the GaN layer (first layer) 122, 124, 126. FIG. 10 shows an enlarged structure related to the trench 146. As shown in FIGS. 9 and 10, the trench 146 extends parallel to the <1-100> crystal axis (the depth direction in FIG. 1). The trench 146 has a substantially V-shaped cross section, and a pair of side surfaces 146a of the trench 146 is a <11-22> crystal plane. The side surface 146a and the bottom surface 146b of the trench 146 form an angle of approximately 120 degrees. Further, the side surface 146a of the trench 146 and the upper surface 126a of the GaN layers (first layers) 122, 124, 126 also form an angle of approximately 120 degrees.

  As shown in FIGS. 9 and 10, a gate electrode 136 and a gate insulating film 137 are formed inside the trench 146. The gate insulating film 137 is formed on the surface (side surface 146a and 1 bottom surface 46b) of the trench 146. The gate electrode 136 is formed on the gate insulating film 137. The gate electrode 136 faces the side surface 146a and the bottom surface 146b of the trench 146 with the gate insulating film 137 interposed therebetween.

  The GaN layers 122, 124, and 126 of the nitride semiconductor crystal 120 can be divided into a GaN substrate layer 122, a high-resistance GaN layer 124, a p-type GaN layer 126, and a source region 142. The configuration related to the GaN substrate layer 122, the high-resistance GaN layer 124, the p-type GaN layer 126, and the source region 142 includes the GaN substrate layer 22, the high-resistance GaN layer 24, the p-type GaN layer 26, and the source region described in the first embodiment. 42, respectively. The configuration related to the GaN layer 127 of the nitride semiconductor crystal 120 is equal to the configuration related to the first AlGaN layer 127 described in the first embodiment.

  A source electrode 132 is formed on the upper surface 120 a of the nitride semiconductor crystal 120. A drain electrode 134 is formed on the lower surface 120 b of the nitride semiconductor crystal 120. The configuration related to the source electrode 132 and the drain electrode 134 is the same as the configuration related to the source electrode 32 and the drain electrode 34 described in the first embodiment.

  With the above configuration, the semiconductor device 100 of the present embodiment has the following differences compared to the semiconductor device 10 described in the first embodiment. That is, in the semiconductor device 100 of this embodiment, the AlGaN layer 127 is formed only on the upper surface 126a of the GaN layers (first layers) 122, 124, 126 (excluding the formation range of the trench 146). The high resistance GaN layer 124 is exposed on the surfaces 146a and 146b. A gate insulating film 137 is directly formed on the surfaces 146 a and 146 b of the trench 146.

  Next, the operation of the semiconductor device 100 will be described. In the semiconductor device 100, the side surface 146a of the trench 146 is formed on the (11-22) crystal plane, and the gate insulating film 137 is formed on the side surface 146a of the trench 146. The (11-22) crystal plane is a semipolar plane with little change in polarity in the vertical direction. Therefore, on the side surface 146a of the trench 146, the generation of a piezo electric field due to the film stress of the gate insulating film 137 or the gate electrode 136 is relatively suppressed. Therefore, in a state where no voltage is applied to the gate electrode 136, a high-density two-dimensional electron gas layer is not formed in the vicinity of the side surface 146a of the trench 146. Furthermore, in the state where no voltage is applied to the gate electrode 136, the depletion layer extends from the p-type GaN layer 126, thereby preventing a two-dimensional electron gas layer from being formed on the side surface 146 a of the trench 146. In a state where no voltage is applied to the gate electrode 136, the electrons are reliably prohibited from traveling along the side surface 146 a of the trench 146, and the source electrode 132 and the drain electrode 134 are electrically disconnected from each other.

  On the other hand, when a positive voltage is applied to the gate electrode 136, the depletion layer formed in the high-resistance GaN layer 124 is reduced, and the formation of a two-dimensional electron gas layer is allowed along the side surface 146a of the trench 146. . By applying a positive voltage to the gate electrode 136, a channel through which a large number of electrons can travel is formed along the side surface 146a of the trench 146, and the source electrode 132 and the drain electrode 134 can be energized. As described above, the semiconductor device 100 can realize a stable normally-off operation.

  The manufacturing method of the semiconductor device 100 of the second embodiment is common in many parts to the manufacturing method of the semiconductor device 10 described in the first embodiment. Specifically, the semiconductor device 100 of Example 2 can be manufactured by removing the process of forming the second AlGaN layer 128 from the manufacturing process of the semiconductor device 10 described in Example 1. Therefore, similarly to the semiconductor device 10 of the first embodiment, the semiconductor device 100 of the second embodiment can be manufactured from a gallium nitride substrate whose main surface is a (0001) crystal plane.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. The technology illustrated in this specification or the drawings achieves a plurality of objects at the same time, and has technical usefulness by achieving one of them.

FIG. 3 is a schematic diagram illustrating a unit structure of the semiconductor device according to the first embodiment. FIG. 3 is an enlarged view showing the structure of a trench of Example 1. FIG. 3 is a diagram showing a first manufacturing process of the semiconductor device of Example 1; FIG. 6 is a diagram showing a second manufacturing process of the semiconductor device of Example 1; FIG. 6 is a diagram showing a third manufacturing process of the semiconductor device of Example 1; FIG. 6 is a diagram showing a fourth manufacturing process of the semiconductor device of Example 1; FIG. 6 is a diagram showing a fifth manufacturing process of the semiconductor device of Example 1; The figure which shows the example which changed the structure of the trench. FIG. 6 is a schematic diagram showing a unit structure of a semiconductor device of Example 2. The figure which expands and shows the structure of the trench of Example 2.

Explanation of symbols

10, 100: semiconductor device 20, 120: nitride semiconductor crystal 22, 122: GaN substrate layer (part of first layer)
24, 124: high-resistance GaN layer (part of the first layer)
26, 126: p-type GaN layer (part of the first layer)
27, 127: first AlGaN layer (part of the second layer)
28: Second AlGaN layer (part of the second layer)
30: heterojunction surface 32, 132: source electrode 34, 134: drain electrode 36, 136: gate electrode 37, 137: gate insulating film 42, 142: source region

Claims (3)

Preparing a nitride semiconductor crystal whose upper surface is a (0001) crystal plane;
Forming a trench extending in parallel with the <1-100> crystal axis or the <11-20> crystal axis on the upper surface of the nitride semiconductor crystal;
A heat treatment step of heating the nitride semiconductor crystal in which the trench is formed in an atmosphere of gas containing ammonia to form a (11-22) crystal plane or a (1-101) crystal plane on at least a part of the side surface of the trench. When,
Forming a gate electrode facing the side surface of the trench through an insulating layer;
A method for manufacturing a semiconductor device comprising: The method further includes the step of crystal-growing a second layer made of the second type nitride semiconductor on the (11-22) crystal plane or the (1-101) crystal plane formed on the side surface of the trench. The manufacturing method according to claim 1 . 3. The manufacturing method according to claim 2, wherein a crystal plane of gallium nitride is exposed on a side surface of the trench, and the second type nitride semiconductor is gallium nitride / aluminum.

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