DE102020202014A1 - Vertical field effect transistor and method of forming the same - Google Patents

Abstract

A vertical field effect transistor (10) is provided, comprising: a gallium nitride substrate (11) with an N-polar side (47); a gallium nitride drift region (12) on the N-polar side (47); a trench structure (50) on or above the gallium nitride drift region (12), the trench structure (50) having an undoped or substantially undoped gallium nitride layer (17) and a nitride-containing barrier layer (21) vertically between the Gallium nitride layer (17) and the drift region (12), wherein the gallium nitride layer (17) has a (FET) channel region.

Description

The invention relates to a vertical field effect transistor and a method of forming the same.

Transistors based on gallium nitride (GaN) offer the possibility of realizing components with lower switch-on (On) resistances and at the same time higher breakdown voltages than comparable components based on silicon or silicon carbide. One possible construction for such a transistor is the so-called VHEMT (vertical groove high electron mobility transistor; "transistor with vertical pit and high electron mobility"), in which the channel is formed by a two-dimensional electron gas (2DEG) at the interface of an AlGaN / GaN heterostructure is shown, which is grown in a V-shaped trench. A corresponding design is in 5A shown.

The transistor consists of a conductive GaN substrate 111 , on which a weakly n-doped GaN drift zone 112 is upset. Above the drift zone 112 there is a p-doped GaN region 115 and over it an insulating GaN or AlGaN region 116 . Both areas 115 , 116 are pierced by a V-shaped trench over which an undoped GaN region is located 117 as well as an AlGaN area 121 extends. At the interface of the two areas 117 , 121 the 2DEG is formed. A p-doped GaN region is located in the V-shaped trench 131 introduced to ensure a self-locking (normally-off) operation of the component. A gate electrode 132 contacts the p-GaN region 131 . The source contact 151 contacts both the 2DEG and the p-region 115 . An isolation 141 separates the source contact 151 and the gate contact 132 . There is a drain electrode on the back of the substrate 152 . In addition, highly doped p-regions can be used to shield the gate trench 118 be introduced in the drift zone.

5B illustrates a band diagram 500 a stack of layers with the barrier layer 121 , the undoped layer 117 and the drift area 112 , being a conduction band edge 502 , a valence band edge 506 and the location of a resulting two-dimensional electron gas 504 (2DEG) are illustrated.

Without applying a gate voltage, the transistor is normally off because the 2DEG is below the area 131 is impoverished. By applying a positive voltage to the gate electrode 132 the entire 2DEG is filled with electrons and the electrons flow from the source contact 151 over the side wall of the trench into the trench floor and from there into the drift zone 112 , about the substrate 111 into the drain electrode 152 . The surface of the substrate 111 conventionally has a (0001) orientation, which is also referred to as a Ga-polar surface.

The V-shaped trench is formed with a defined flank angle. The edge angle influences the threshold voltage of the transistor. Precise control of the flank angle is therefore necessary. Due to a missing barrier to the underlying insulating GaN region 116 or the drift zone 112 In the conventional transistor, the 2DEG is only insufficiently electrically restricted in the GaN (also known as electrical confinement). This allows the electrons to spread in forward mode in areas of lower electrical conductivity, which increases the resistance of the transistor. In addition, the limitation of vertical leakage currents is only possible to a limited extent. The activation of p-doped areas (areas 115 , 131 and 118 ) requires the structure to be heated at temperatures close to or above the decomposition temperature of the Ga-polar surface. A considerable technical effort is therefore necessary in order to activate the p-regions, for example covering (capping) the surface or high-rate heating.

It is an object of the invention to provide a vertical field effect transistor which has a more precisely formed trench structure, as well as a method for its production.

According to one aspect of the invention, the object is achieved by a vertical field effect transistor having: a gallium nitride substrate with an N-polar side, a gallium nitride drift region on the N-polar side, a trench structure on or above the gallium nitride drift region. The trench structure has an undoped or essentially undoped gallium nitride layer and a nitride-containing barrier layer vertically between the gallium nitride layer and the drift region. The gallium nitride layer has a field effect transistor (FET) channel region.

This enables setting and precise control of the flank angle of the trench structure. Alternatively or additionally, a more restricted two-dimensional charge carrier gas, for example two-dimensional electron gas (2DEG), is made possible. Alternatively or additionally, a substrate surface is provided, the decomposition temperature of which is significantly above the temperatures required to activate p-doped regions.

According to a further aspect of the invention, the object is achieved by a method for forming a vertical field effect transistor. That The method includes: providing a gallium nitride substrate with an N-polar side, forming a gallium nitride drift region on the N-polar side, forming a trench structure on or above the gallium nitride drift region. The trench structure is formed with an undoped or essentially undoped gallium nitride layer and a nitride-containing barrier layer vertically between the gallium nitride layer and the drift region. The gallium nitride layer has a field effect transistor (FET) channel region.

• 1A eine schematische Querschnittsansicht eines vertikalen Feldeffekttransistors gemäß verschiedenen Ausführungsformen;
• 1B ein Banddiagramm eines Schichtenstapels eines vertikalen Feldeffekttransistors gemäß verschiedenen Ausführungsformen;
• 2A eine schematische Querschnittsansicht eines vertikalen Feldeffekttransistors gemäß verschiedenen Ausführungsformen;
• 2B ein Banddiagramm eines Schichtenstapels eines vertikalen Feldeffekttransistors gemäß verschiedenen Ausführungsformen;
• 3 eine schematische Aufsicht einer Graben-Struktur eines vertikalen Feldeffekttransistors gemäß verschiedenen Ausführungsformen;
• 4 ein Ablaufdiagramm eines Verfahrens zum Ausbilden eines vertikalen Feldeffekttransistors gemäß verschiedenen Ausführungsformen;
• 5A eine schematische Querschnittsansicht eines vertikalen Feldeffekttransistors der bezogenen Technik; und
• 5B ein Banddiagramm des vertikalen Feldeffekttransistors der bezogenen Technik.

Further developments of the aspects are set out in the subclaims and the description. Embodiments of the invention are shown in the figures and are explained in more detail below. Show it:

• 1A a schematic cross-sectional view of a vertical field effect transistor according to various embodiments;
• 1B a band diagram of a layer stack of a vertical field effect transistor according to various embodiments;
• 2A a schematic cross-sectional view of a vertical field effect transistor according to various embodiments;
• 2 B a band diagram of a layer stack of a vertical field effect transistor according to various embodiments;
• 3 a schematic plan view of a trench structure of a vertical field effect transistor in accordance with various embodiments;
• 4th a flowchart of a method for forming a vertical field effect transistor according to various embodiments;
• 5A a schematic cross-sectional view of a related art vertical field effect transistor; and
• 5B a band diagram of the related art vertical field effect transistor.

In the following detailed description, reference is made to the accompanying drawings, which form a part of this specification and in which there is shown, for purposes of illustration, specific embodiments in which the invention may be practiced. It goes without saying that other embodiments can be used and structural or logical changes can be made without departing from the scope of protection of the present invention. It goes without saying that the features of the various embodiments described herein can be combined with one another, unless specifically stated otherwise. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. In the figures, identical or similar elements are provided with identical reference symbols, insofar as this is appropriate.

1A Figure 3 illustrates a schematic cross-sectional view of a vertical field effect transistor 10 according to various embodiments.

The vertical field effect transistor 10 has a conductive gallium nitride (GaN) substrate 11 with an N-polar side or surface 47 (i.e., with (000 1 ) Orientation) and one of the N-polar side 47 opposite Ga-polar side or surface 48 (ie, with (0001) orientation).

On or above the N-polar side 47 is a drift area 12th educated. The drift area 12th For example, a weakly n-conducting gallium nitride (GaN) drift region 12th be, for example a weakly n-doped GaN drift region 12th .

Above the drift area 12th is a p-doped GaN layer 15th formed and (optionally) above an insulating GaN or aluminum gallium nitride (AlGaN) layer 16 . Both layers 15th , 16 are of a V-shaped trench structure 50 pierce its side walls with the surface of the layers 15th , 16 form an angle between 0 ° and 80 °, preferably between 20 ° and 80 °. The vertical field effect transistor clearly shows 10 a trench structure 50 on or above the gallium nitride drift region 12th on.

The moat structure 50 has a bottom 45 and at least one side wall 46 on. At least on the side wall 46 the trench structure 50 the field effect transistor (FET) channel region can be formed.

The moat structure 50 has an undoped or substantially undoped gallium nitride (GaN) layer 17th and a nitride-containing barrier layer 21 (for example AlGaN or AlN) vertically between the gallium nitride layer 17th and the drift area 12th on. The barrier layer 21 is at least on the side wall 46 trained and can be in the ground 45 the trench structure 50 be trained.

The gallium nitride layer 17th has an FET channel region or at least a part thereof, or the FET channel region can be the gallium nitride layer 17th exhibit. In other words, the FET channel region has a III-V heterostructure made from the undoped GaN layer 17th and the barrier layer 21 on. The III-V heterostructure 17th , 21 is to form a two-dimensional charge carrier gas 56 , for example an electron gas (2DEG), at an interface of the III-V heterostructure 17th , 21 set up. The 2DEG is at the interface of the two layers 17th , 21 - but in the undoped GaN layer 17th - formed as in the band diagram in 1B and is described in more detail below.

The vertical field effect transistor 10 also has a first source / drain electrode (e.g. a source electrode) 51 on those with the III-V heterostructure 17th , 21 the trench structure 50 is electrically conductively connected. Furthermore, a second source / drain electrode (e.g. a drain electrode) 52 intended. The vertical field effect transistor can clearly be seen 10 a source electrode on or above the N-polar side 47 and a drain electrode on or above the Ga polar side 48 of the gallium nitride substrate 11 exhibit. Alternatively, the vertical field effect transistor 10 a drain electrode on or above the N-polar side 47 and a source electrode on or above the Ga polar side 48 of the gallium nitride substrate 11 exhibit. In the following, it is assumed by way of example that the first source / drain electrode 51 is a source electrode and that the second source / drain electrode 52 is a drain electrode.

The source electrode 51 can be applied directly to the barrier layer 21 adjoin. The drain electrode 52 can be on the Ga polar back 48 of the GaN substrate 11 can be formed.

On or above the III-V heterostructure 17th , 21 can be a gate electrode 32 be trained. An isolation 41 separates the source electrode 51 and the gate electrode 32 electrically from each other.

For shielding the trench structure 50 can additionally use highly doped p-regions 18th (also as a shielding structure 18th designated) in the drift area 12th be trained.

The vertical field effect transistor is without applying a gate voltage 10 self-locking (normally off), because the 2DEG is below the gate electrode 32 is impoverished. By applying a positive voltage to the gate electrode 32 the entire 2DEG is filled with electrons and the electrons flow from the source electrode 51 over the side wall 46 in the ground 45 the trench structure 50 and from there into the drift area 12th , about the substrate 11 into the drain electrode 52 .

The trench structure is achieved by using a substrate with an N-polar surface 50 compared to the substrate with Ga-polar surface of the related technology ( 5A) formed on a substrate surface having a higher decomposition temperature. This enables p-doped layers, for example the shielding structure 18th , which are formed for example by means of ion implantation, to activate at higher temperatures. This increases the shielding effect of the shielding structure, for example 18th and reduces leakage currents. It should be noted that the in 2A Surface orientation of the substrate shown 11 in the case of overlying GaN regions or layers (e.g. 12th , 15th , 16 , 18th ) can continue. That is, those in the same direction as the N-polar surface 47 of the substrate 11 The facing surfaces of these GaN regions can also be N-polar.

Alternatively or additionally, the barrier layer can be used 21 the spatial confinement of the 2DEG can be increased.
By suitable choice of the thickness of the barrier layer 21 it becomes the electrons of the 2DEG in the GaN layer 17th enabled in forward operation by the barrier layer 21 to tunnel to a vertical flow of electricity from the ground 45 the trench structure 50 to the drain electrode 52 to enable. Alternatively or additionally, at least some of the otherwise necessary for the activation of the p-doped regions ( 118 ) the necessary capping layers can be dispensed with.

Alternatively or additionally, etching processes are available for N-polar surfaces, for example wet etching with, for example, potassium hydroxide (KOH) or trimethylammonium hydroxide (TMAH), which utilize the extremely anisotropic etching rates of the crystal surfaces. As a result, a surface with a suitable flank angle can be formed on the N-polar side. This allows the V-shaped trench structure 50 on the N-polar surface 47 be generated with a homogeneous or more homogeneous flank angle. Alternatively or additionally, the anisotropic etching properties of the N-polar surface can be used to create a hexagonal trench structure 50 be trained in a simple way, which in the supervision in 3 is illustrated.

1 B. illustrates a band diagram 60 a stack of layers with the barrier layer 21 , the undoped GaN layer 17th and the drift area 12th , being a conduction band edge 58 , a valence band edge 54 and the location of a resulting two-dimensional electron gas 56 (2DEG) are illustrated.

In contrast to the Ga-polar surface of the related technology ( 5A , 5B) , are the areas 17th (AlGaN) and 21 (undoped GaN) of the III-V heterostructure 17th , 21 exchanged in their order relative to the Ga-polar surface. This results directly from the band structure, which is shown in 5B for the Ga-polar surface of the related engineering and in 1B for a vertical field effect transistor 10 on the N-polar surface 47 is illustrated according to various embodiments.

In the case of the Ga polar surface 148 ( 5B) the related technology forms the 2DEG 504 in one area 117 , to which directly the drift zone 112 or the areas 115 , 116 connect (see 5A) . In the case of the N-polar surface 47 ( 1A) is the 2DEG of these areas through the (AIGaN) barrier layer 21 separated.

The barrier layer 21 acts as a rear barrier, which limits the 2DEG more strongly. The barrier layer can increase this effect 21 Aluminum nitride (AlGaN) or be formed from it, which has a higher band gap than AlGaN.

Alternatively or additionally, the barrier layer prevents 21 also a diffusion of the in layer 15th Magnesium present as a dopant in the undoped GaN layer 17th the III-V heterostructure 17th , 21 . In other words: the undoped GaN layer 17th can be formed undoped, but dopant atoms (parasitic) can diffuse in from adjacent layers. This allows the undoped GaN layer 17th have a weak doping in the finished component, but this is not intended. By means of a parasitic doping in the GaN layer 17th the 2DEG can be degraded. In this respect, the GaN layer is 17th essentially undoped. The barrier layer 21 can help reduce the undoped state of the GaN layer 17th to maintain.

By means of the barrier layer 21 and using the N-polar surface of the substrate 11 can the layer 16 can be optionally omitted.

The barrier layer 21 can be made very thin, for example in the range from a few nm to sub-nm, for example in the range from 0.1 nm to 10 nm. Such a barrier layer 21 can act as a diffusion barrier for dopant atoms of neighboring, doped layers.

Should the vertical current flow through the barrier layer 21 If it is too low, it can also be local, for example in the area of the floor 45 the trench structure 50 as an additional barrier layer 23 modified to achieve better vertical current flow. In other words, as an alternative to the barrier layer 21 in the ground 45 can be an additional barrier layer 23 in the ground 45 the trench structure 50 be trained as in 2A and 2 B is illustrated. The barrier layer 21 has a first thickness. The additional barrier layer 23 has a second thickness that is different from the first thickness. The second thickness is, for example, greater or less than the first thickness. Alternatively, the second thickness can be the same as the first thickness. The barrier layer 21 comprises a first material or is formed therefrom. The additional barrier layer 23 comprises or is formed from a second material that is different from the first material. Alternatively, the second material and the first material can be the same material. The additional barrier layer 23 in the ground 45 the trench structure 50 can be formed, for example, by ion implantation.

In the related art, a p-type GaN effects area 131 the normally-off (normally-off) operation of the vertical field effect transistor. In various embodiments, the trench structure 50 alternative to the p-GaN region ( 131 ) a polarization compensating structure (polarization compensation structure 22nd , 42 ) on or above the gallium nitride layer 17th exhibit. The gate electrode 32 can be on or above the polarization compensation structure 22nd , 42 be trained.

The polarization compensation structure 22nd , 42 can for example at least a first layer 22nd and a second layer 42 exhibit. The first layer 22nd and the second layer 42 can be set up to compensate for polarization to one another.

In this context, polarization is to be understood as the net polarization charge that occurs at the interface of III-V nitrides due to the spontaneous polarization of the wurtzite crystal structure and the piezoelectric polarization due to the tensioning of epitaxially grown layers with a lattice mismatch. With the polarization compensation structure 22nd , 42 there are alternating positive and negative interfacial charges.

The first layer 22nd has a first conductivity type, for example 22nd on and the second layer 42 has a second conductivity type that is different from the first conductivity type. Alternatively, the second layer 42 be an insulator or electrically non-conductive. The first layer 22nd can for example comprise aluminum gallium nitride or be formed therefrom and the second layer 42 may comprise or be formed from silicon nitride.

How such a polarization compensation structure works 22nd , 42 is from the in 2 B illustrated band diagram showing the conduction band edge 58 for a vertical section through a layer stack with the gate electrode 32 , the second layer 42 , the first layer 22nd , the undoped GaN layer 17th , the barrier layer 21 and the drift area 12th shows (the layer thicknesses of the individual layers are not shown to scale for better visualization). The conduction band can be in the undoped GaN layer without an applied gate voltage 17th , in which the 2DEG is formed, must be above the Fermi energy (E = 0). Thus, the vertical field effect transistor 10 be self-locking. This can also be the case in areas in which the layer stack passes through at least one of the layers described above 15th or 16 instead of the drift area 12th is limited downwards, for example on the flanks of the trench structure 50 .

As an alternative to the material combination AlGaN / SiN for the polarization compensation structure 22nd , 42 other materials or material combinations can also be used. Furthermore, the polarization compensation structure 22nd , 42 can also be implemented by means of one, three or more layers, for example different doping.

In various embodiments, the trench structure 50 in plan view a hexagonal shape, as in the schematic plan view in 3 is illustrated. Due to the anisotropic etching rates, the facets of the hexagons can correspond to the crystal planes that can develop during the etching.

4th Figure 10 illustrates a flow diagram of a method 400 for forming a vertical field effect transistor according to various embodiments. The procedure 400 instructs a deploy 410 a gallium nitride substrate with an N-polar side, forming 420 a gallium nitride drift region on the N-polar side and forming 430 a trench structure on or above the gallium nitride drift region. The trench structure is formed with an undoped or essentially undoped gallium nitride layer and a nitride-containing barrier layer vertically between the gallium nitride layer and the drift region. The gallium nitride layer has an FET channel region.

The embodiments described and shown in the figures are selected only as examples. Different embodiments can be combined with one another completely or with regard to individual features. An embodiment can also be supplemented by features of a further embodiment. Furthermore, described method steps can be repeated and carried out in a sequence other than that described. In particular, the invention is not restricted to the specified method.

Claims (10)

Vertical field effect transistor (10), comprising: a gallium nitride substrate (11) having an N-polar side (47); a gallium nitride drift region (12) on the N-polar side (47); a trench structure (50) on or above the gallium nitride drift region (12), wherein the trench structure (50) has an undoped or substantially undoped gallium nitride layer (17) and a nitride-containing barrier layer (21) vertically between the gallium nitride layer (17) and the drift region (12), wherein the gallium nitride layer (17) has a field effect transistor (FET) channel region. Vertical field effect transistor (10) according to Claim 1 wherein the trench structure (50) has a bottom (45) and at least one side wall (46), the barrier layer (21) being formed on the side wall (46) and an additional barrier layer (23) being formed in the bottom (45) is. Vertical field effect transistor (10) according to Claim 2 wherein the barrier layer (21) has a first thickness and the additional barrier layer (23) has a second thickness that differs from the first thickness. Vertical field effect transistor (10) according to Claim 2 or 3 wherein the barrier layer (21) comprises or is formed from a first material and the additional barrier layer (23) comprises or is formed from a second material that differs from the first material. Vertical field effect transistor (10) according to one of the Claims 1 until 4th , wherein the trench structure (50) furthermore has a polarization compensation structure (22, 42) on or above the gallium nitride layer (17), the polarization compensation structure (22, 42) having at least a first layer (22) and a second layer (42 ) having. Vertical field effect transistor (10) according to Claim 5 wherein the first layer (22) has a first conductivity type (22) and the second layer (42) has a second conductivity type which is different from the first conductivity type. Vertical field effect transistor (10) according to Claim 5 or 6th wherein the first layer (22) comprises or is formed from aluminum gallium nitride and the second layer (42) comprises or is formed from silicon nitride. Vertical field effect transistor (10) according to one of the Claims 5 until 7th wherein the trench structure (50) further comprises a gate electrode (32) on or above the polarization compensation structure (22, 42). Vertical field effect transistor (10) according to one of the Claims 1 until 8th , wherein the trench structure (50) has a hexagonal shape in plan view. A method (400) for forming a vertical field effect transistor (10), the method (400) comprising: providing (410) a gallium nitride substrate (11) with an N-polar side (47); Forming (420) a gallium nitride drift region (12) on the N-polar side (47); Forming (430) a trench structure (50) on or above the gallium nitride drift region (12), the trench structure (50) having an undoped or essentially undoped gallium nitride layer (17) and a nitride-containing barrier layer ( 21) is formed vertically between the gallium nitride layer (17) and the drift region (12), the gallium nitride layer (17) having a field effect transistor (FET) channel region.

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