JP2003078136A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device by which the diffusion of impurity in an impurity area and a gate electrode is suppressed to prevent the variance of short channel effect and threshold voltage. SOLUTION: This method for manufacturing a semiconductor device includes a step for forming a gate electrode 7 on a p-type semiconductor substrate 1 with a silicon oxide film 5 as a gate insulation film, a step for introducing nitrogen to the gate electrode 7 and an n-well area 4, and a step for injecting a p-type impurity (boron) to the n-well area 4 of the p-type semiconductor substrate 1 while the gate electrode 7 is used as a mask and forming a p-type low-concentration diffusion layer 11 as a result.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more specifically, an impurity region (impurity diffusion layer) is formed by implanting impurities into the surface of a semiconductor substrate using a gate electrode as a mask. The present invention relates to a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, a dual gate CMOS is known as one of semiconductor devices. In this dual gate CMOS, the gate electrode of the p-type MOS transistor and the low concentration diffusion layer (SDE (Source Dra
In extension)), boron is used as a p-type impurity for forming.

[0003]

However, since boron has a large diffusion coefficient in silicon, boron in the low-concentration diffusion layer and the gate electrode easily diffuses. When boron is diffused in the low-concentration diffusion layer, the junction depth of the low-concentration diffusion layer becomes deeper, which disadvantageously increases the short channel effect. Further, when boron in the gate electrode diffuses, the boron penetrates into the silicon substrate, so that the p-type MO
There is an inconvenience that the threshold voltage of the S transistor changes.

Therefore, conventionally, various methods have been proposed in order to suppress the above diffusion of boron. As one of them, RT as a heat treatment process performed after boron implantation
A (Rapid Thermal Annealin
g) A method of optimizing the temperature and time in the step has been proposed.

However, in the RTA process, if it is attempted to simultaneously suppress the diffusion of impurities in addition to the activation of impurities, which is the original function, it becomes very difficult to set conditions such as temperature and time. Margin becomes smaller. As a result, there is a problem that the yield is reduced.

Further, in order to prevent boron from penetrating from the gate electrode to the silicon substrate, a method of using a silicon oxynitride film as a gate insulating film has been proposed.
However, when a silicon oxynitride film is used as the gate insulating film, nitrogen in the silicon oxynitride film forms an interface state, which causes a problem that mobility in the p-type transistor is lowered.

The present invention has been made to solve the above problems, and one object of the present invention is to:
It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of suppressing the short channel effect and the fluctuation of the threshold voltage due to the diffusion of impurities without lowering the yield.

Another object of the present invention is to prevent boron penetration from the gate electrode to the silicon substrate without lowering the mobility of the transistor.

[0009]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including a step of forming a gate electrode on a semiconductor substrate via a gate insulating film, and a step of forming a gate electrode and an element forming region of the semiconductor substrate. Then, a step of introducing nitrogen and a step of forming a first impurity region by introducing an impurity into the element formation region of the semiconductor substrate by using the gate electrode as a mask are then provided.

According to the first aspect of the present invention, as described above, the element formation region of the semiconductor substrate is made amorphous by introducing nitrogen into the element formation region of the semiconductor substrate. Therefore, when the first impurity region is formed thereafter. In addition, even if the heat treatment for recovering the crystal defects is performed, the introduced impurities can be suppressed from diffusing. This makes the shallow first
Impurity regions can be formed. As a result, the short channel effect can be suppressed. Further, by introducing nitrogen into the gate electrode, diffusion of impurities in the gate electrode to the semiconductor substrate can be suppressed even if heat treatment for defect recovery and activation of impurities is performed. As a result, it is possible to prevent the threshold voltage from changing. In addition, since the nitrogen introduction process can easily set the conditions, the yield does not decrease.

A method of manufacturing a semiconductor device according to claim 2 is
In the structure of claim 1, the step of introducing nitrogen is performed by injecting nitrogen into the element formation region of the semiconductor substrate,
The method includes the step of forming an amorphous layer in the element formation region of the semiconductor substrate. According to this structure, diffusion of impurities in the element formation region of the semiconductor substrate can be easily suppressed.

A method of manufacturing a semiconductor device according to claim 3 is
The structure of claim 1 or 2, wherein the step of forming the amorphous layer is larger than the region where the first impurity region is formed by implanting nitrogen into a region larger than the region where the first impurity region is formed. The process includes forming an amorphous layer up to the region. According to this structure, the amorphous layer can effectively suppress the diffusion of the impurities injected for forming the first impurity region.

A method of manufacturing a semiconductor device according to claim 4 is
In any one structure of Claims 1-3, the process of introduce ^| transducing nitrogen includes the process of introduce | transducing nitrogen by the injection amount of 5 * 10 ^{< 14} > cm ^<-2 > or more. According to this structure, the element formation region of the semiconductor substrate can be made amorphous to such an extent that diffusion of the impurities injected for forming the first impurity region can be suppressed.

A method of manufacturing a semiconductor device according to claim 5 is
In any one of the configurations of claims 1 to 4, the step of introducing nitrogen includes a step of implanting nitrogen from an oblique direction at an incident angle that is not perpendicular to the main surface of the semiconductor substrate. According to this structure, nitrogen can be introduced also into the region below the gate electrode, so that the diffusion of impurities below the gate electrode can be suppressed.

A method of manufacturing a semiconductor device according to claim 6 is
In the structure of claim 5, the step of introducing nitrogen is performed by rotating nitrogen injection four times or more. According to this structure, nitrogen can be uniformly introduced into the region below the gate electrode, so that the diffusion of impurities below the gate electrode can be further suppressed.

A method of manufacturing a semiconductor device according to claim 7 is
7. The structure according to claim 1, wherein the step of forming the first impurity region is performed by implanting a p-type impurity into the element formation region of the semiconductor substrate using the gate electrode as a mask, thereby forming a low impurity concentration p Forming a first impurity region of the mold. According to this structure, even if a p-type impurity such as boron having a large diffusion coefficient in the silicon substrate is used, it is possible to suppress the diffusion of the p-type impurity during the heat treatment for recovering the crystal defects. Therefore, the shallow p-type first impurity region can be formed.

A method of manufacturing a semiconductor device according to claim 8 is
In the structure of claim 7, the p-type impurity contains one of boron and BF ₂ . In claim 8,
By configuring in this way, boron or BF ₂
Can be suppressed from diffusing.

A method of manufacturing a semiconductor device according to claim 9 is
9. The structure according to claim 1, wherein the gate insulating film includes a silicon oxide film. That is, when a silicon oxynitride film is used as a gate insulating film as a measure against the penetration of impurities in the gate electrode, nitrogen in the silicon oxynitride film creates an interface state, which lowers the mobility in the p-type transistor. On the other hand, if a silicon oxide film is used as the gate insulating film and nitrogen is introduced into the gate electrode, it is possible to prevent impurities from penetrating through the gate electrode while obtaining high mobility.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIGS. 1 to 11 show a semiconductor device (dual gate CM) according to a first embodiment of the present invention.
FIG. 6 is a cross-sectional view for explaining the method for manufacturing the OS). Figure 1
The manufacturing process of the semiconductor device of the first embodiment will be described below with reference to FIGS.

First, as shown in FIG. 1, STI (Shallow Trench Iso) is formed on a p-type silicon substrate 1.
device isolation oxide film 2 and a p well 3 and an n well 4 are formed. After that, the silicon oxide film 5 is formed with a thickness of about 3 nm by using a thermal oxidation method by dry oxidation under a temperature condition of about 950 ° C. The p-type silicon substrate 1 is an example of the “semiconductor substrate” of the present invention, and the n well 4 is an example of the “element formation region” of the present invention.

After that, a polycrystalline silicon film (not shown) is formed on the entire surface, and then the polycrystalline silicon film and the silicon oxide film 5 thereunder are patterned by using a photolithography technique and a dry etching technique. The gate electrodes 6 and 7 as shown in FIG.
A silicon oxide film 5 as a gate insulating film is formed.
The polycrystalline silicon film may be an amorphous silicon film.

Next, as shown in FIG. 3, a resist film 8a is formed so as to cover the region on the n well 4. Then, using the resist film 8a and the gate electrode 6 as a mask, arsenic (As) is ion-implanted into the p-well 3 to form an n-type low-concentration diffusion layer (SDE) 9 and the gate electrode 6 is exposed to arsenic. Introduce. The implantation of this arsenic has an implantation energy of 10 keV and an implantation amount of 1.0 ×.
It is performed under the conditions of 10 ¹⁵ cm ^-2 and incident angle: 0 degree. After this,
The resist film 8a is removed.

Next, as shown in FIG. 4, a resist film 8b is formed so as to cover the region on the p well 3. Using the resist film 8b and the gate electrode 7 as a mask, nitrogen (N
₂ ) is ion-implanted into the n-well 4 to form the amorphous layer 10 near the surface of the silicon substrate and introduce nitrogen into the gate electrode 7. This nitrogen injection has an injection energy of 25 keV and an injection amount of 1.3 ×.
It is performed under the condition of four rotation injections of 10 ¹⁴ cm ^-2 and an incident angle of 7 degrees. Since it is a four-time rotation injection, the total injection amount is
It becomes 1.3 * 4 * 10 ^{< 14} > cm ^<-2 > = 5.2 * 10 ^{< 14} > cm ^<-2 >.

In order to completely amorphize the silicon substrate 1 by implanting nitrogen, 3 × 10 ¹⁵ c
An injection amount of m ^-2 or more is required. However, in the first embodiment, it is sufficient to make amorphous so that the diffusion of impurities (boron) can be suppressed, so an implantation amount of about 5.0 × 10 ¹⁴ cm ⁻² is sufficient. In fact, it was confirmed that a diffusion suppressing effect was obtained with an implantation amount of about 5.0 × 10 ¹⁴ cm ⁻² . Therefore, in the present invention, the implantation amount of nitrogen is 5.0 × 10 ¹⁴ c
It is preferably m ⁻² or more. In the first embodiment, in consideration of this point, the total nitrogen injection amount is set to 5.2 × 10 5.
^{It is 14} cm ^-2 .

The amorphous layer 10 formed by the nitrogen implantation is formed up to a region (deep) larger than a region where a p-type low concentration diffusion layer 11 described later is formed.

Next, as shown in FIG. 5, a resist film 8b is formed.
With the gate electrode 7 as a mask, boron (B) is n
By implanting ions into the surface of the well 4, a p-type low concentration diffusion layer (SDE) 11 is formed and boron is introduced into the gate electrode 7. In this case, the depth of the p-type low concentration diffusion layer 11 is shallower than the depth of the amorphous layer 10. This boron implant has an implant energy: 1
keV, implantation amount: 3.0 × 10 ¹⁴ cm ⁻² , and incident angle: 0 degree. After that, the resist film 8b is removed.
The p-type low concentration diffusion layer 11 is an example of the “first impurity region” in the present invention.

Next, as shown in FIG. 6, a heat treatment by an RTA method called spike anneal at about 1000.degree.
The impurities (arsenic, boron) in the n-type low-concentration diffusion layer 9 and the p-type low-concentration diffusion layer 11 are activated, and at the time of forming the n-type low-concentration diffusion layer 9 and the p-type low-concentration diffusion layer 11. The defects caused by the ion implantation are recovered, and the amorphous layer 10 is recrystallized. In this case, boron in the p-type low-concentration diffusion layer 11 has a large diffusion coefficient in silicon, and therefore tends to diffuse by the heat of the RTA process. But,
Since the amorphous layer 10 is formed, the diffusion of boron is suppressed. As a result, a shallow low concentration diffusion layer (SDE)
11 is formed.

Next, the entire surface of the HTO (High Temp) is
After forming an interlayer insulating film such as an erase oxide, the interlayer insulating film is anisotropically etched to form side wall spacers 12 as shown in FIG. 7 on the side surfaces of the gate electrodes 6 and 7.

Next, as shown in FIG. 8, a resist film 8c is formed so as to cover the region on the n well 4. Then, using the resist film 8c, the gate electrode 6 and the sidewall spacers 12 as a mask, arsenic (As) is ion-implanted into the p-well 3 to form the n-type high-concentration diffusion layer 13 and the gate electrode 6 at the same time. Introduce arsenic. The implantation energy of this arsenic is 60 ke.
V, implantation amount: 5.0 × 10 ¹⁵ cm ⁻² , incident angle: 7 degrees. After that, the resist film 8c is removed.

Next, as shown in FIG. 9, a resist film 8d is formed so as to cover the region on the p well 3. Then, boron (B) is ion-implanted into the n-well 4 using the resist film 8d, the gate electrode 7 and the sidewall spacers 12 as a mask to form the p-type high concentration diffusion layer 14 and the gate electrode 7 with boron. To introduce. The implantation energy of this boron is implantation energy: 10 k.
eV, implantation amount: 3.0 × 10 ¹⁵ cm ⁻² , and incident angle: 7 degrees. After that, the resist film 8d is removed.

Next, as shown in FIG. 10, about 1050 ° C.
The n-type high-concentration diffusion layer 13 and the p-type high-concentration diffusion layer 1 are subjected to heat treatment by the RTA method under the temperature conditions of
The defect generated at the time of forming 4 is recovered, and the impurities (arsenic, boron) in the n-type high-concentration diffusion layer 13 and the p-type high-concentration diffusion layer 14 are activated. In this case, RTA
When the amount of heat (temperature and time) in the process is increased, the activation rate of impurities can be increased, but boron easily penetrates. On the other hand, when the amount of heat in the RTA process is reduced, the penetration of boron can be suppressed, but the activation rate of impurities decreases.

In the first embodiment, since nitrogen is implanted into the gate electrode 7 in advance in the step shown in FIG. 4, the implanted nitrogen bonds with boron to increase the molecular radius. As a result, even if the amount of heat in the RTA process is increased, the boron in the gate electrode remains in the p-type silicon substrate 1.
It is possible to suppress the penetration. Therefore, it is possible to improve the activation rate of impurities and suppress the penetration of boron.

Since arsenic has a small diffusion coefficient in silicon, it does not relatively diffuse even if a heat treatment for defect recovery is performed. Therefore, the shallow n-type low concentration diffusion layer 9 can be formed without implanting nitrogen.

Finally, as shown in FIG. 11, an interlayer insulating film 15 made of a silicon oxide film is formed on the entire surface of the device. As a result, the semiconductor device of the first embodiment is formed.

In the first embodiment, in order to recover the crystal defects by forming the amorphous layer 10 by previously implanting nitrogen into the region where the p-type low concentration diffusion layer 11 is formed, as described above. Even if the heat treatment by the RTA method is performed, the diffusion of boron in the p-type low concentration diffusion layer 11 can be suppressed. This allows for shallow p
The mold low concentration diffusion layer 11 can be formed. As a result, the short channel effect can be suppressed.

Also, when nitrogen is previously introduced into the p-type gate electrode 7 and then boron is injected into the gate electrode 7 to perform heat treatment by the RTA method for defect recovery and activation of impurities, It is possible to prevent boron in the gate electrode 7 from diffusing and penetrating to the p-type semiconductor substrate 1. This can prevent the threshold voltage of the p-type MOS transistor from changing.

Since the conditions can be easily set in the nitrogen introduction process, the yield does not decrease.

In addition, in the step shown in FIG.
Since nitrogen can be uniformly introduced into the region below the gate electrode 7 by rotating the well 4 at least four times from an oblique direction when implanting into the well 4, boron below the gate electrode 7 can be introduced. Can be further suppressed.

Further, in the first embodiment, the silicon oxide film 5 is used as the gate insulating film, so that the silicon oxynitride film is used as the gate insulating film.
Since the interface state can be suppressed, the mobility does not decrease. As a result, boron can be prevented from penetrating from the gate electrode 7 to the p-type silicon substrate 1 while obtaining high mobility.

(Second Embodiment) FIGS. 12 to 24 show a semiconductor device (dual gate C according to a second embodiment of the present invention).
FIG. 6 is a cross-sectional view for explaining the method of manufacturing the (MOS). The manufacturing process of the semiconductor device of the second embodiment will be described below with reference to FIGS.

Of the manufacturing process of the semiconductor device of the second embodiment, the manufacturing process shown in FIGS. 12 to 16 is the same as the manufacturing process shown in FIGS. 1 to 5 of the first embodiment. is there.

That is, first, as shown in FIG.
An element isolation oxide film 22 of STI is formed on a silicon substrate 21, and a p well 23 and an n well 24 are formed. After that, the silicon oxide film 25 is formed by a thermal oxidation method by dry oxidation using a temperature of about 950 ° C.
Is formed with a thickness of about 3 nm.

After that, a polycrystalline silicon film (not shown) is formed on the entire surface, and then the polycrystalline silicon film and the silicon oxide film 25 are patterned by using the photolithography technique and the dry etching technique. , Gate electrodes 26 and 27, and a silicon oxide film 25 as a gate insulating film are formed. The polycrystalline silicon film may be an amorphous silicon film.

Next, as shown in FIG.
A resist film 28a is formed so as to cover the upper region.
By using the resist film 28a as a mask, arsenic (As) is ion-implanted into the gate electrode 26 and the p-well 23 to form an n-type low concentration diffusion layer (SDE) 29 and introduce arsenic into the gate electrode 26. This arsenic implantation is performed with an implantation energy of 10 keV and an implantation amount of 1.0 ×.
It is performed under the conditions of 10 ¹⁵ cm ^-2 and incident angle: 0 degree. After this,
The resist film 28a is removed.

Next, as shown in FIG.
A resist film 28b is formed so as to cover the upper region.
Nitrogen (N ₂ ) is ion-implanted into the n-well 24 and the gate electrode 27 using the resist film 28b as a mask to amorphize the silicon on the surface of the n-well 24 to form the amorphous layer 30 and the gate electrode. Nitrogen is introduced at 27. This nitrogen injection is
Injection energy: 25 keV, injection amount: 1.3 × 10 ¹⁴
cm ⁻² , incident angle: 7 degrees, 4 times rotation injection. The amorphous layer 30 is formed up to a region (deep region) larger than a region where a p-type low concentration diffusion layer 31 described later is formed.

Next, as shown in FIG. 16, the resist film 2
8b and the gate electrode 27 as a mask, the n-well 2
By implanting boron (B) into the surface of 4
To form the p-type low-concentration diffusion layer 31 and
Boron is introduced into the electrode 27. This boron injection is
Input energy: 1 keV, injection amount: 3.0 × 10¹⁴cm
^-2, Injection angle: performed under the condition of 0 degree. After this, the resist
The film 28b is removed.

Next, as shown in FIG. 17, about 1000.degree.
The n-type low-concentration diffusion layer 29 and the p-type low-concentration diffusion layer 3 are subjected to the heat treatment by the RTA method under the temperature condition of
The impurities (arsenic, boron) in 1 are activated, the defects caused by the ion implantation are recovered, and the amorphous layer 30 is recrystallized. In addition, this RTA
The process uses an anneal called spike anneal, which takes almost no time at the highest temperature.

After that, for example, an interlayer insulating film such as an HTO film is formed on the entire surface, and then the interlayer insulating film is anisotropically etched to form side surfaces of the gate electrodes 26 and 27 as shown in FIG. The side wall spacer 32 is formed.

Next, as shown in FIG.
A resist film 28c is formed so as to cover the upper region.
By using the resist film 28c and the sidewall spacers 32 as a mask, arsenic (As) is ion-implanted into the n-well 23 to form the n-type high-concentration diffusion layer 33 and introduce arsenic into the gate electrode 26. This arsenic implantation is performed with an implantation energy of 60 keV and an implantation amount of 5.
It is performed under the conditions of 0 × 10 ¹⁵ cm ^-2 and incident angle: 7 degrees. In this case, arsenic is also implanted into the gate electrode 26. After this,
The resist film 28c is removed.

Next, as shown in FIG. 20, the p well 23
A resist film 28d is formed so as to cover the upper region.
The resist film 28d and the sidewall spacer 32 are
Ion-implant boron (B) into the n-well 24 as a mask
To form the p-type high-concentration diffusion layer 34.
At the same time, boron is introduced into the gate electrode 27. This Bo
The implantation of Ron has an implantation energy of 10 keV and an implantation dose of:
3.0 x 10¹⁵cm^-2 , Incident angle: performed under the condition of 7 degrees.
After that, the resist film 28d is removed.

Next, as shown in FIG. 21, the RTA method is used to activate the impurities (arsenic, boron) and to recover the defects caused by the ion implantation. The conditions of the RTA process at this time are: heat source: halogen lamp, temperature: about 900 ° C. to about 1000 ° C., atmosphere: N ₂ , time:
It is about 0.1 second to about 1 second. The main purpose of this RTA process is TED (Transie) in the subsequent heat treatment.
nt Enhanced Diffusion: transient enhanced diffusion). Here, the transient enhanced diffusion is
This is a phenomenon in which impurities are diffused together with defects when the defects are about to appear on the surface when heat is applied.

In order to prevent such TED, this RT
The process A uses an anneal called spike anneal, which takes almost no time at the highest temperature. Furthermore, in order to prevent TED further, the temperature raising rate (temperature raising rate) and the temperature lowering rate (temperature lowering rate) are increased as much as possible. Also,
By adding 1 to 10% of oxygen (O ₂ ) to the atmosphere, it is possible to further suppress the diffusion of boron in the p-type high concentration diffusion layer 34.

Next, as shown in FIG. 22, furnace annealing is performed.
It has not been recovered by the RTA process shown in FIG.
Defect recovery by ion implantation and RTA shown in FIG.
Crystal defects newly generated due to a steep temperature gradient in the process
And recover. The condition of furnace annealing at this time is
Source: electric furnace, temperature: about 700 ° C to 850 ° C, atmosphere: N
₂, Time: about 30 minutes to about 120 minutes. Furnace anneal
Is a sufficient amount of heat due to the amount of heat applied at low temperature for a long time.
Crystal defects can be recovered. Furthermore, n-type high concentration
The diffusion layer 33 and the p-type high-concentration diffusion layer 34 are slightly diffused.
Therefore, the n-type high concentration diffusion layer 33 and the p-type
Defects existing under the bottom surface of the concentration diffusion layer 34 are removed by n-type high concentration
Inside the diffusion layer 33 and the p-type high-concentration diffusion layer 34.
Can be crowded. This removes the defect almost completely.
Can be excluded.

Next, as shown in FIG. 23, impurities (arsenic, boron) in the gate electrodes 26 and 27 and the n-type high-concentration diffusion layer 33 and the p-type high-concentration diffusion layer 34 are formed by the RTA method. Activates the impurities (arsenic, boron).
The RTA process conditions at this time are: heat source: halogen lamp, temperature: about 1000 ° C. to about 1100 ° C., atmosphere:
N ₂ , time: about 5 seconds to about 10 seconds. In the RTA process shown in FIG. 23, the temperature is set higher than that in the RTA process shown in FIG.

In the furnace annealing, defects newly generated by ion implantation and the RTA process shown in FIG. 21 can be almost completely recovered, but the temperature is about 700 ° C. to about 850 ° C.
In particular, the activation rate of the impurities in the gate electrodes 26 and 27 made of polycrystalline silicon is lowered by applying the heat. Therefore, in the second embodiment, R in FIG.
The TA step activates the impurities whose activation rate has decreased. At this time, in the RTA process shown in FIG. 23, the temperature is higher than that in the RTA process shown in FIG. 21, whereby the activation rate is further improved, the temperature rising rate and the temperature lowering rate are lowered, and the maximum is reached. By prolonging the annealing time at the temperature, it is possible to obtain a condition in which defects are less likely to occur and process variations are small.

Furthermore, since most of the defects have been recovered by the furnace annealing process shown in FIG. 22, defects due to the RTA process shown in FIG. 23 are unlikely to occur. That is, in the RTA process shown in FIG.
Since defects are still generated by ion implantation, R
Defects increase due to the stress caused by the TA process. However, in the RTA process shown in FIG. 23, the furnace anneal shown in FIG. 22 sufficiently recovers the defects and almost no defects are found in the semiconductor substrate.
Even if there is stress due to the process A, no increase in defects is observed.

Incidentally, the impurities in the gate electrodes 26 and 27 made of polycrystalline silicon are the n-type high-concentration diffusion layer 33 and the p-type high-concentration diffusion layer 34 made of single-crystal silicon.
The inactivation of impurities by furnace annealing is more remarkable than the impurities in (drain region, source region). Therefore, the main purpose of the RTA process shown in FIG. 23 is to increase the activation rate of impurities in gate electrodes 26 and 27.

Finally, as shown in FIG. 24, an interlayer insulating film 35 made of a silicon oxide film is formed on the entire surface of the device. As a result, the semiconductor device of the second embodiment is formed.

In the second embodiment, as shown in FIG.
By the furnace anneal shown in FIG. 21, the defects caused by the RTA step shown in FIG. 21 are recovered, and by the RTA step shown in FIG. 23, the activation rate of the impurities lowered by the furnace anneal shown in FIG. 22 is improved. More specifically, FIG.
By the RTA process shown in (1), the defects generated by the ion implantation as well as the activation of the impurities are recovered, and TED in the subsequent heat treatment is prevented. Then, the furnace anneal shown in FIG. 22 recovers the defects caused by the ion implantation not sufficiently recovered in the RTA process shown in FIG. 21 and the defects newly generated in the RTA process shown in FIG. Further, the RTA process shown in FIG. 23 activates the impurities whose activation rate has been lowered by the furnace annealing shown in FIG.

Since the main purpose of the RTA process shown in FIG. 21 is to prevent TED in the subsequent heat treatment, the impurities in the n-type high-concentration diffusion layer 33 and the p-type high-concentration diffusion layer 34 are not necessarily removed. No need to activate.
Therefore, in the RTA process shown in FIG. 21, it is sufficient to add the minimum necessary temperature that can remove the defects that cause TED. On the other hand, since the RTA process shown in FIG. 23 is for activating the impurities in the gate electrode, the drain region and the source region, the treatment at the highest temperature is performed as far as boron penetration does not occur. The higher the activation rate of impurities, the better. The penetration of boron can be suppressed by injecting nitrogen.

Further, generally, when the annealing time in the RTA process is short, an increase in defects due to the RTA process and an increase in process variation become problems. However, since the RTA process shown in FIG. 21 is followed by the two annealing processes of the furnace annealing process shown in FIG. 22 and the RTA process shown in FIG. 23, the annealing time of the RTA process shown in FIG. 21 is short. The problem does not occur. On the other hand, the RTA process shown in FIG. 23 requires an annealing time capable of controlling process variations.

Since the main purpose of the RTA process shown in FIG. 21 is to prevent TED in the subsequent heat treatment, it is not always necessary to activate the high concentration diffusion layer. Therefore, in the RTA process shown in FIG. 21, it is only necessary to add the minimum necessary amount of heat that can remove the defects that cause TED. Therefore, TED can be further prevented by increasing the temperature raising rate and the temperature lowering rate. . Generally, when the temperature rising rate and the temperature lowering rate of the RTA process are high, an increase in defects due to the RTA process and an increase in process variation become problems. However, after the RTA step shown in FIG. 21, the furnace annealing step shown in FIG.
Since there are two heat treatment steps of the RTA step shown in FIG. 21, there is no problem due to the short annealing time of the RTA step shown in FIG.

Also in the second embodiment, since nitrogen is injected in the step shown in FIG. 15, the same effect as that of the first embodiment can be obtained. That is, in the second embodiment, as described above, the amorphous layer 30 is formed by previously implanting nitrogen into the region where the p-type low-concentration diffusion layer 31 is formed.
It is possible to suppress the diffusion of boron in the p-type low-concentration diffusion layer 31 even if the RTA method heat treatment for recovering the crystal defects is performed. Thereby, the shallow p-type low concentration diffusion layer 31 can be formed. As a result, the short channel effect can be suppressed.

Further, in the second embodiment, after the nitrogen is introduced into the p-type gate electrode 27 in advance, boron is injected into the gate electrode 27 to perform heat treatment by the RTA method for defect recovery and impurity activation. Also in the case of performing the above, it is possible to prevent the boron in the gate electrode 27 from diffusing and penetrating to the p-type semiconductor substrate 21. This can prevent the threshold voltage of the p-type MOS transistor from changing.

Since the conditions can be easily set in the nitrogen introduction process, the yield does not decrease.

Further, in the second embodiment, when nitrogen is injected into the n-well 24 in the step shown in FIG. 15, the nitrogen is injected below the gate electrode 27 by rotating the obliquely four times or more. Nitrogen can be uniformly introduced into the region, so that the diffusion of boron below the gate electrode 27 can be further suppressed.

Further, in the second embodiment, by using the silicon oxide film 25 as the gate insulating film, the interface state can be suppressed more than in the case where the silicon oxynitride film is used as the gate insulating film. Is never reduced. As a result, boron can be prevented from penetrating from the gate electrode 27 to the p-type silicon substrate 21 while obtaining high mobility.

It should be understood that the embodiments disclosed this time are exemplifications in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of the claims, and further includes meanings equivalent to the scope of the claims and all modifications within the scope.

For example, in the above embodiment, boron and BF ₂ are used as the p-type impurities, but the present invention is not limited to this, and the same effect can be obtained by using other p-type impurities. it can.

Further, in the above-mentioned embodiment, the application example to the dual gate CMOS is shown, but the present invention is not limited to this, and the p-channel type field effect transistor (p-type MOS).
The same effect can be obtained if it is a semiconductor device including a transistor.

[0072]

As described above, according to the present invention, the short channel effect and the fluctuation of the threshold voltage are suppressed by suppressing the diffusion of the impurities in the impurity region and the gate electrode without lowering the yield. be able to.

[Brief description of drawings]

FIG. 1 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a sectional view illustrating the manufacturing process for the semiconductor device according to the first embodiment of the present invention;

FIG. 8 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 10 is a sectional view illustrating the manufacturing process for the semiconductor device according to the first embodiment of the present invention;

FIG. 11 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

FIG. 12 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 13 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 14 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 15 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 16 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 17 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 18 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 19 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 20 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 21 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 22 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 23 is a cross-sectional view illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

FIG. 24 is a sectional view for illustrating the manufacturing process for the semiconductor device according to the second embodiment of the present invention.

[Explanation of symbols]

1,21 p-type silicon substrate (semiconductor substrate) 3,23 p well 4, 24 n-well (element formation region) 5, 25 Silicon oxide film (gate insulating film) 6, 7, 26, 27 Gate electrode 9, 29 n-type low concentration diffusion layer 10, 30 Amorphous layer 11, 31 p-type low concentration diffusion layer (first impurity region) 13, 33 n-type high-concentration diffusion layer 14, 34 p-type high concentration diffusion layer

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/265 W (72) Inventor Atsuhiro Nishida 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Inside the Electric Co., Ltd. (72) Inventor Kazunori Fujita 2-5-5 Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. (72) Hideki Mizuhara 2-5-5 Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. (72) Inventor Tetsuhiro Inoue 2-5-5 Keihan Hondori, Moriguchi City, Osaka Prefecture Sanyo Electric Co., Ltd. (72) Inori Inori Takanori Kobayashi 2-5 Keihan Hondori, Moriguchi City, Osaka Prefecture No. 5 Sanyo Electric Co., Ltd. F term (reference) 5F048 AB03 AC03 BA01 BB04 BB06 BB07 BC06 BE03 DA23 DA25 5F140 AA06 AA13 AA21 AA28 AB03 AC01 BA01 BE07 BF01 BF04 BF34 BF38 BG08 BG12 BG38 BG43 BG44 BG52 BG53 BG56 BH15 BH22 BK02 BK10 BK13 BK21 CB04 CB08 CC03 CF00 CF07

Claims (9)

[Claims] 1. A step of forming a gate electrode on a semiconductor substrate via a gate insulating film, a step of introducing nitrogen into the gate electrode and an element formation region of the semiconductor substrate, and then the gate electrode. Forming a first impurity region by introducing an impurity into the element forming region of the semiconductor substrate using the mask as a mask. 2. The step of introducing the nitrogen includes the step of forming an amorphous layer in the element formation region of the semiconductor substrate by injecting the nitrogen into the element formation region of the semiconductor substrate. A method for manufacturing a semiconductor device as described above. 3. The step of forming the amorphous layer is performed by implanting the nitrogen into a region larger than a region in which the first impurity region is formed, so that the amorphous layer is larger than a region in which the first impurity region is formed. The method of manufacturing a semiconductor device according to claim 2, further comprising the step of forming the amorphous layer up to a region. 4. The semiconductor device according to claim 1, wherein the step of introducing the nitrogen includes the step of introducing the nitrogen with an implantation amount of 5 × 10 ¹⁴ cm ⁻² or more. Production method. 5. The step of introducing the nitrogen includes the step of injecting the nitrogen from an oblique direction at an incident angle that is not perpendicular to the main surface of the semiconductor substrate.
5. The method for manufacturing a semiconductor device according to any one of 4 above. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the step of introducing the nitrogen is performed by rotating the implantation of the nitrogen four times or more. 7. The step of forming the first impurity region comprises implanting a p-type impurity into an element formation region of the semiconductor substrate using the gate electrode as a mask, thereby forming the p-type first impurity region with a low impurity concentration. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of forming one impurity region. 8. The p-type impurities are boron and BF.
8. The method for manufacturing a semiconductor device according to claim 7, comprising either one of the _two . 9. The method of manufacturing a semiconductor device according to claim 1, wherein the gate insulating film includes a silicon oxide film.