JPH10233457A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To inhibit speedy diffusion of impurities implanted at a low energy, by a method wherein the impurities are implanted in the source and drain regions of a semiconductor substrate by an ion-implantation using a gate electrode which is formed on the substrate as a mask, and an activation annealing of the introduced impurities is performed in a short time at a high temperature. SOLUTION: A field oxide film 2 is selectively formed in the surface of a silicon substrate 1, a gate oxide film 3 and a polysilicon film are deposited on a region defend by the film 2, and these of the film 3 and the polysilicon film are patterned to form a poysilicon gate 4, which is used as a gate electrode. Then, an ion-implantation for forming a shallow junction is performed in the substrate, an ion-implanted region 5 in low acceleration is formed and after that, a lamp annealing is performed and shallow diffused layers 6 are formed. An impurity ion-implantation is performed in source-drain ion-implanted regions 8 formed in the layers 6, a lamp annealing for activating the implanted impurities is performed and source-drain diffused layers 9 are formed in the substrate 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a highly integrated CMOS LSI having a MOS structure device having a fine gate electrode and a shallow junction, particularly a threshold voltage in a logic or memory device. The present invention relates to a method for manufacturing a semiconductor device which suppresses fluctuations in the performance and has a high performance and a simplified number of steps.

[0002]

2. Description of the Related Art In order to suppress the short channel effect and improve the driving force with the miniaturization of MOSFETs, it is necessary to make the source / drain (S / D) diffusion layer region shallow (shallow junction). is there.

In recent years, solid-phase diffusion, vapor-phase diffusion, plasma doping, laser doping, and the like have been studied as methods for forming shallow junctions. This is because, when an impurity is introduced by ion implantation, it is particularly difficult to form a shallow boron profile generally used as a dopant for a p-type semiconductor.

The cause of this is that during annealing for activating the implanted impurities, the diffusion of the impurities is promoted by the action of defects introduced into the substrate at the same time as the implantation of the impurities (accelerated diffusion), and the shallow junction is formed. This is because it becomes difficult.

However, the ion implantation technique as a method of doping the S / D diffusion layer is superior in uniformity, reproducibility, controllability, throughput, etc. as compared with the other techniques described above, and therefore, the introduction of impurities. Is performed by ion implantation, and it is suitable as a method for forming a shallow junction in which it is preferable to suppress accelerated diffusion during activation annealing.

On the other hand, as described above, the problem of the ion implantation technique is the accelerated diffusion of impurities during activation annealing. Optimization of this annealing method is the most important issue. Since a shallow diffusion layer is required to have a low resistance at the same time, the activation rate of the implanted impurity must be improved. The activation ratio increases as the annealing temperature increases and the annealing time increases, but at the same time, the diffusion of impurities is accelerated. For this reason, the diffusion layer becomes deeper and redistribution of impurities in the channel region occurs. In these cases, a short channel effect occurs and the gate electrode cannot be reduced in size.
Problems such as difficulty in controlling the threshold value occur.

[0007] Therefore, as an alternative to the usual annealing method in an electric furnace in which high-temperature heat is applied to the substrate for a long time at a high temperature and the diffusion of impurities cannot be suppressed, for example, JP-A-1-205522 and JP-A-63-1988. As disclosed in JP-A-56915 and JP-A-2-353,
An annealing method at 900 ° C. to 1100 ° C. for a few seconds to several tens of seconds at a high temperature and a short time by lamp heating is considered, and attempts have been made to minimize the diffusion distance of impurities by shortening the annealing time.

[0008]

The lamp annealing shown in the prior art suppresses the diffusion of impurities as compared with the electric furnace annealing, and to some extent the junction depth (X
A j) shallow diffusion layer can be formed.

However, in order to achieve Xj of 0.1 μm or 0.05 μm or less required for the next-generation microdevice, at present, there is a limit to lowering the energy of ion implantation. Has been an essential issue.

In the conventional lamp annealing method, the diffusion length of the impurity is simply shortened by shortening the annealing time, but the enhanced diffusion is not suppressed. In an experiment actually performed by the conventional technique, for example, even if Xj is 0.03 μm immediately after B is implanted at 1 KeV, even if
When the lamp annealing is performed for 10 ° C. for 10 seconds, Xj becomes 0.08.
It becomes deep to about μm. That is, accelerated diffusion occurs even in the conventional annealing method. In order to actually form a shallow junction having a thickness of 0.05 μm or less, the prior art is insufficiently studied. Requires some measures to be taken.

In order to realize high speed and low power consumption of LSI, it is necessary to improve the performance of semiconductor elements.
A MOSFET having a shallow diffusion layer must be formed in order to suppress the short channel effect accompanying the miniaturization of the OS transistor.

An object of the present invention is to provide a channel region or S / S
Diffusion of the impurity introduced into the D diffusion layer region is suppressed, and not only the operation stability is improved, but also the fine MOS in which the short channel effect is suppressed by realizing a shallow S / D junction.
It is an object of the present invention to provide a method of manufacturing a type transistor.

[0013]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is a method of manufacturing a semiconductor device having an impurity introducing step and an annealing step. Using a gate electrode formed on a semiconductor substrate via a gate oxide film as a mask to introduce impurities into the source / drain regions of the substrate by ion implantation, and performing the annealing process in the source / drain regions. This is a process in which activation annealing of impurities is performed at a high temperature for a short time.

In the high-temperature short-time annealing,
By increasing the temperature at a rate of 400 ° C. or more per second, a process for suppressing the diffusion of impurities and not lowering the activation rate of impurities is performed.

In the high-temperature short-time annealing,
The annealing temperature is set to 1000 ° C. or more and the annealing time is set to 1 second or less.

Further, by performing the high-temperature short-time annealing immediately after the impurity is implanted, redistribution of the impurity due to heat in the subsequent steps is suppressed, and a process for preventing deterioration of characteristics such as threshold value fluctuation is performed. Things.

Further, a method of manufacturing a semiconductor device according to the present invention includes an impurity introducing step and an annealing step,
A method of manufacturing a semiconductor device for forming a pn junction of μm or less, wherein the impurity introducing step is a step of introducing impurity boron into an N-type semiconductor substrate, and the annealing step is introducing the boron into the N-type semiconductor substrate. In the annealing process in the annealing process, the temperature is increased from 1000 ° C. to 1150 ° C. at a rate of 150 ° C./sec or more by lamp heating. This is a process for immediately lowering the temperature by setting the holding time at 1 second or less.

The annealing in the annealing step is performed by heating the lamp at a rate of 150 ° C./sec or more.
This is a process of raising the temperature to 1000 ° C. or higher, immediately lowering the holding time at the maximum attained temperature in 1 second, and then performing annealing for 10 minutes in a temperature range of 800 ° C. to 850 ° C.

In the annealing in the annealing step, annealing is performed for 10 seconds or less while the semiconductor substrate is heated to 950 ° C., and subsequently, the temperature is rapidly increased to 1100 ° C. without lowering the temperature. This is a process in which the temperature is raised to a holding time of 1 second or less and the temperature is immediately lowered to room temperature.

Generally, the diffusion rate of boron is very high,
It is known that the diffusion coefficient increases exponentially with increasing temperature. Furthermore, it is known that the interstitial silicon type point defects simultaneously introduced into the silicon crystal at the time of impurity implantation have an effect of accelerating the diffusion of boron, and the diffusion coefficient of boron introduced by the ion implantation method is We must discuss it on the premise of accelerated diffusion.

It is known that the point defect which causes the enhanced diffusion is originally faster than the diffusion rate of the impurity. For example, the diffusion coefficient of the point defect at 1000 ° C. is smaller than that of boron in the interstitial silicon type. It is known that the value is 7 orders of magnitude larger, and that of a hole type point defect is 5 orders of magnitude larger. Therefore, in practice, it is impossible to prevent diffusion of point defects that cause accelerated diffusion at a heating rate on the order of seconds.

Normally, the impurity activation annealing is performed as follows.
Since the temperature is generally in the temperature range of 800 ° C. to 1150 ° C., the change in the diffusion coefficient of boron in this temperature range is shown. Although not much different from the diffusion coefficient, the difference tends to widen as the temperature becomes lower. For example, 800 ° C
Is a value that is about two digits larger than the intrinsic diffusion coefficient.

For this reason, for example, when annealing is performed at 1100 ° C., it is possible to allow the substrate wafer to be exposed to a temperature range of 800 ° C. to 1000 ° C. where the enhanced diffusion of boron appears most remarkably in the temperature rising process. It is considered that shortening as much as possible is effective in suppressing the diffusion of impurities.

Therefore, if the ramp rate is set to 100 ° C.
When the speed is increased from 400 ° C./sec to 400 ° C./sec, it is simply calculated that the time from 800 ° C. to 1100 ° C. is 1 /
After 4, the effect of suppressing the accelerated diffusion appears sufficiently.

In the present invention, the activation anneal after the impurity implantation is performed by lamp anneal with a very high temperature rising rate (a ramping rate), whereby the diffusion of the impurities is suppressed, so that activation at a higher temperature is possible. Thus, a low-resistance shallow junction with an improved activation rate can be formed.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. The semiconductor device shown in FIG.
It is intended for OS transistors.

First, as shown in FIG. 1A, a field oxide film 2 is selectively formed on the surface of a silicon substrate 1, and a gate oxide film 3 and polysilicon are formed in a region defined by the field oxide film 2. A polysilicon gate 4 as a gate electrode is formed by stacking and depositing these and patterning them.

Next, as shown in FIG.
Ion implantation for forming a shallow junction of j <50 nm is performed to form a low-acceleration ion implantation region 5. Its slow ion implantation is performed, for example if an impurity is boron implantation energy of about 1 KeV, also the implantation energy if BF ₂ in the following 3 KeV. Then, FIG.
As shown in (b), lamp annealing is performed to activate the ion-implanted impurities, and a shallow diffusion layer 6 is formed.

Next, as shown in FIG. 1C, a gate side wall 7 is formed on the side surface of the polysilicon gate 4, and thereafter, a low resistance and good contact are formed in the shallow diffusion layer 6 by silicidation or the like. For this purpose, ion implantation for forming the source / drain diffusion layer 8 having a certain depth is performed. It is necessary to optimize the ion implantation conditions for forming the gate sidewall 7 or the source / drain regions so as not to affect the characteristics of the shallow diffusion layer 6 formed in advance. That is, the width of the gate side wall 7 is set to, for example, 100 so that the S / D diffusion layer 9 formed by the source / drain implantation does not approach the channel region 10 more than the shallow diffusion layer 6.
BF ₂ at 20 KeV and 3 ×
Implant at 10 ¹⁵ / cm ² .

Next, as shown in FIG. 1D, in order to activate the impurities implanted in the source / drain regions, lamp annealing is performed to form an S / D diffusion layer 9. Thereby, the base of the PMOS having the double drain structure is completed.

Next, in Embodiment 1 of the present invention, a method of forming a shallow diffusion layer by minimizing diffusion of impurities introduced by ion implantation during activation annealing of impurities, specifically, FIG. A method for forming the junction depth Xj in the shallow diffusion layer 6 to be shallow by suppressing impurity diffusion will be described in detail with reference to FIGS.

FIG. 2 is a characteristic diagram showing a temperature sequence during annealing after low-acceleration ion implantation. In the first embodiment, the ramping rate is set to 550 ° C./sec and 1100 ° C.
The temperature of the substrate is raised to 1100 ° C., and the power of the lamp is turned off when the temperature reaches 1100 ° C. That is, the time for holding at the highest temperature is set to 0 second.

Here, compared with the conventional lamp annealing method in which the ramping rate is about 100 ° C./sec,
The time during which the substrate is heated to 800 ° C. or higher, at which accelerated diffusion easily occurs, is very short. Therefore, as shown in FIG. 3, in the first embodiment of the present invention, when the substrate is annealed at different heating rates with the hold time during the annealing being 0 seconds, the distribution of boron in the depth direction is increased. The diffusion of impurities is suppressed as the temperature rate is increased.

FIG. 4 shows that boron is 1 KeV / 1E15 / c.
m ² implanted silicon substrate at 1100 ° C. for 0.05
The layer resistance after the lamp annealing performed for 2 seconds is plotted against the rate of temperature rise. When the rate of temperature rise is 250 ° C. or higher, the junction depth becomes substantially equilibrium. This supports the fact that the effect of suppressing the diffusion of impurities due to the high-speed temperature rise appears as described above, because the time for which the substrate is exposed to the high-temperature atmosphere is shortened.

FIG. 5 shows the relationship between the junction depth and the holding time by lamp annealing. Heating rate 40
When the holding time after the temperature of the boron-implanted substrate is raised to 1100 ° C. is set to 1 second or less at 0 ° C./second, diffusion of impurities is suppressed and the junction can be made shallower. Therefore, the holding time when performing the lamp annealing at 1100 ° C. needs to be 1 second or less. Further, since this holding time naturally depends on the annealing temperature, 1100 ° C.
Lower temperatures may be somewhat longer, and temperatures higher than 1100 ° C. require less than 1 second.

FIG. 6 is a diagram showing the relationship between the junction depth and the annealing temperature. When the annealing temperature is increased, the diffusion rate of the impurity is increased, and the junction is formed deeply.

FIG. 7 is a diagram showing the relationship between the layer resistance and the annealing temperature. If the impurity activation annealing is performed at a low temperature, diffusion of the impurity is suppressed and a shallow junction is obtained. However, as shown in FIG. 7, a problem arises in that the activation rate is reduced and the layer resistance is increased.

As described above, in the lamp annealing at the time of activating the impurities, the substrate wafer is heated to 1100 ° C. at a heating rate of 250 ° C./sec or more, and the temperature is immediately lowered by setting the holding time within 1 second. Thus, a diffusion layer having a low resistance and a shallow junction can be formed.

(Embodiment 2) Next, Embodiment 2 of the present invention will be described with reference to the drawings. In the second embodiment, in the step shown in FIG. 1B, annealing is performed immediately after low-acceleration ion implantation to prevent redistribution of impurities in the shallow diffusion layer due to heat applied to the substrate in a subsequent step. It has the advantage that it can be done.

FIG. 8 shows that the temperature was raised to 1000 ° C. by a rapid temperature rise (400 ° C./second), lamp annealing was performed for 0.05 seconds, and then heat was applied at 800 ° C. for 10 minutes by electric furnace annealing. 4 shows the distribution of boron in the depth direction at the time. After lamp annealing, boron redistribution does not occur even if electric furnace annealing at 800 ° C. is performed. On the other hand, when lamp annealing is not performed, boron diffuses deeply. Even when the same high-speed ramp annealing is performed under a condition of less than 1000 ° C., redistribution of boron occurs due to electric furnace annealing.

These facts indicate that, even in the case of annealing for a very short time due to a rapid temperature rise, by raising the temperature to 1000 ° C. or higher, it is possible to recover the crystal defects while suppressing the diffusion of impurities. 100 ° C as in the conventional example
Since lamp diffusion at a rate of temperature rise of about 1 / sec cannot suppress diffusion of impurities, redistribution due to heat in a later step can be suppressed by using the present invention. This leads to an increase in process margin, excellent controllability of impurity diffusion, and simplification of device design.

(Embodiment 3) FIG. 9 is a view for explaining a method of manufacturing a semiconductor device according to Embodiment 3 of the present invention.

In the method for manufacturing a semiconductor device according to the third embodiment of the present invention shown in FIG. 9, after the impurities for forming the source and drain are ion-implanted, the substrate wafer is heated to 950 ° C. by a lamp annealing apparatus and held for 10 seconds. After that, the temperature is continuously raised to 1100 ° C. at a heating rate of 400 ° C./sec without lowering the temperature, and the temperature is immediately lowered to room temperature within a holding time of 1 second. By performing annealing at 950 ° C. for 10 seconds, crystal defects generated during ion implantation are recovered, pn junction leakage current can be suppressed, and diffusion of impurities hardly occurs, so that the junction depth increases. Never.

Furthermore, by raising the temperature of the substrate wafer to 1100 ° C. by the next high-speed heating with a heating lamp, the activation rate of impurities can be improved and the layer resistance can be reduced.

As described in the first embodiment, in the above-described high-speed temperature raising, high-temperature, and short-time annealing, the impurity activation rate can be improved while suppressing the diffusion of impurities as much as possible.

Further, according to the third embodiment of the present invention, since the wafer is heated at a high speed from a state where the wafer is heated to 950 ° C. at a high temperature, the output of the lamp can be easily increased, and the heating rate can be increased. Not only can it be performed faster, but also controllability can be improved, and there is an advantage that heat treatment can be performed in which temperature unevenness in the wafer surface is suppressed.

[0048]

As described above, according to the present invention, it is possible to control the depth of the impurity diffusion layer near the gate end, to suppress the accelerated diffusion of the impurity implanted with low energy, and Short channel effects can be suppressed in the device, and high-performance device characteristics can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a method for manufacturing a double-drain structure PMOS transistor according to Embodiment 1 of the present invention in the order of steps.

FIG. 2 is a characteristic diagram showing a temperature sequence of a high-speed ramp-up lamp annealing according to the present invention.

FIG. 3 is a characteristic diagram showing a boron depth direction distribution when lamp annealing is performed in the embodiment of the present invention.

FIG. 4 is a characteristic diagram of a diffusion layer that demonstrates the present invention.

FIG. 5 is a characteristic diagram of a diffusion layer that demonstrates the present invention.

FIG. 6 is a characteristic diagram of a diffusion layer that demonstrates the present invention.

FIG. 7 is a characteristic diagram of a diffusion layer that demonstrates the present invention.

FIG. 8 is a characteristic diagram showing a distribution of boron in a depth direction showing an effect according to the second embodiment of the present invention.

FIG. 9 is a characteristic diagram illustrating a temperature sequence according to the third embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Si substrate 2 Field oxide film 3 Gate oxide film 4 Polysilicon gate 5 Low acceleration ion implantation area 6 Shallow diffusion layer 7 Gate side wall 8 S / D ion implantation area 9 S / D diffusion layer 10 Channel area

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/336

Claims (7)

[Claims] 1. A method of manufacturing a semiconductor device comprising an impurity introducing step and an annealing step, wherein the impurity introducing step is performed by using a gate electrode formed on a semiconductor substrate via a gate oxide film as a mask. A process of introducing impurities into the source / drain regions by ion implantation; and the annealing step is a process of performing activation annealing of the impurities implanted into the source / drain regions at a high temperature for a short time. Production method. 2. The method according to claim 1, wherein in the high-temperature short-time annealing, the temperature is increased at a rate of 400 ° C. or more per second to suppress the diffusion of impurities and not to lower the activation rate of the impurities. The manufacturing method of the semiconductor device described in the above. 3. The method of manufacturing a semiconductor device according to claim 2, wherein in the high-temperature short-time annealing, the annealing temperature is 1000 ° C. or more and the annealing time is 1 second or less. 4. The method according to claim 1, wherein the high-temperature short-time annealing is performed immediately after the impurity is implanted, so that redistribution of the impurity due to heat in a subsequent step is suppressed, and deterioration of characteristics such as threshold fluctuation is prevented. The method of manufacturing a semiconductor device according to claim 1. 5. A method of manufacturing a semiconductor device having an impurity introducing step and an annealing step and forming a pn junction of 0.1 μm or less, wherein the impurity introducing step introduces impurity boron into an N-type semiconductor substrate. The annealing step is an activation annealing step for activating the impurities introduced into the N-type semiconductor substrate. The annealing step in the annealing step is performed at a rate of 150 ° C./sec or more by lamp heating. 1000 ° C. to 115
A method of manufacturing a semiconductor device, wherein the temperature is raised to 0 ° C., and the holding time at this temperature is set to 1 second or less, and the temperature is immediately lowered. 6. An annealing process in the annealing process,
At a heating rate of 150 ° C / sec or more by lamp heating, 10
6. A process of raising the temperature to 00 ° C. or higher, immediately lowering the holding time at the maximum attained temperature in one second, and thereafter performing annealing for 10 minutes in a temperature range of 800 ° C. to 850 ° C. 13. The method for manufacturing a semiconductor device according to item 5. 7. An annealing process in the annealing process,
While the semiconductor substrate is heated to 950 ° C., annealing is performed for 10 seconds or less, and subsequently, without lowering the temperature, the temperature is rapidly increased to 1100 ° C., and the holding time is set to 1 second or less, and the temperature is immediately lowered to room temperature. The method for manufacturing a semiconductor device according to claim 5, wherein: