JP2007324361A - Semiconductor device and its method for manufacturing - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a small size semiconductor device and its method for manufacturing which operates as a lateral power MOS and an LIGBT with low switching loss. <P>SOLUTION: The semiconductor device includes a p-type silicon (Si) substrate 100, an n-type drift region 101, a p-type collector region 110a, an n-type source region 103, a p-type emitter region 106, an emitter electrode 107, a gate electrode 105, a collector electrode 111, an n-type drain region 109 formed in the front surface of the p-type silicon (Si) substrate 100 so as to be positioned between the p-type collector region 110a and the collector electrode 111, and a p-type collector connection region 110b which is formed in the n-type drain region 109 and electrically connects the p-type collector region 110a and the collector electrode 111. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a power transistor intended for use at a high withstand voltage, and more particularly to an insulated gate bipolar transistor (hereinafter abbreviated as IGBT) and a method for manufacturing the same.

  As power transistors that handle high voltage and high power, power MOSFETs and IGBTs are well known. When these elements are formed on the same semiconductor substrate as other semiconductor integrated circuits, since the compatibility with other integrated circuit formation processes is good, a horizontal power MOSFET (hereinafter abbreviated as a horizontal power MOS) or a horizontal type is used as the element. An IGBT (hereinafter abbreviated as LIGBT) is used. However, the LIGBT has a conductivity modulation in the drift region of a bipolar transistor in addition to the MOSFET gate insulation structure, and is a device that can realize a high breakdown resistance and a low on-resistance, but operates as a bipolar transistor. Therefore, the switching speed is slower than that of MOSFET.

  At this time, as a conventional technique for improving the switching characteristics of the LIGBT, for example, there is a semiconductor device described in Patent Document 1. FIG. 17 is a cross-sectional view showing the structure of the semiconductor device.

In this semiconductor device, p ^- -type semiconductor substrate 21 surface n ^- type epitaxial layer 22 is formed, the n ^- -type epitaxial layer 22, n by the trench well 23 ^- -type epitaxial layer 22a and the n ^- 2 -type epitaxial layer 22b It is separated into two areas. An electrically insulating layer 24 is formed on the trench well walls 25 and 26 that constitute the trench well 23 and are opposed to each other. A trench well filling material 27 such as polysilicon is formed inside the trench well 23.

In the n ⁻ type epitaxial layer 22 b on the right side of the trench well 23, an n ⁺ type region 28 serving as a drain is formed, and a drain electrode 43 is formed on the n ⁺ type region 28 serving as a drain. A p-type well 29 is formed at a certain distance from the n ⁺ -type region 28 serving as the drain. On the surface of the p-type well 29, an n ⁺ -type region 30 and a p ⁺ -type region 31 forming a source region are formed. A source electrode 32 is formed above the n ⁺ type region 30 and the p ⁺ type region 31 that form the source region. An oxide layer 33 is formed on the n ⁻ -type epitaxial layer 22b, and a gate electrode 41 is formed on the oxide layer 33.

In the n ⁻ type epitaxial layer 22a on the left side of the trench well 23, a p ⁺ type region 34 serving as an anode of the LIGBT is formed, and an anode electrode 42 is formed on the p ⁺ type region 34 serving as an anode. A p-type well 35 is formed at a certain distance from the p ⁺ -type region 34 serving as the anode. An n ⁺ type region 36 and a p ⁺ type region 37 forming a cathode region are formed on the surface of the p type well 35. A cathode electrode 38 is formed on the n ⁺ type region 36 and the p ⁺ type region 37 that form the cathode region. An oxide layer 39 is formed on the n ⁻ -type epitaxial layer 22a, and a gate electrode 40 is formed on the oxide layer 39. The drain electrode 43 and the anode electrode 42 are electrically connected.

In the semiconductor device having the above structure, the n ⁻ type epitaxial layer 22a on the left side of the trench well 23 becomes a LIGBT, the n ⁻ type epitaxial layer 22b on the right side of the trench well 23 becomes a lateral power MOS, and the LIGBT and the lateral power MOS are on the same substrate. It is formed. Since the gate electrode 40 of the LIGBT and the gate electrode 41 of the lateral power MOS have independent structures, the LIGBT and the lateral power MOS can be switched independently. Therefore, only the lateral power MOS having a high switching speed is operated when the semiconductor device is switched on and off, and the switching speed can be increased by operating the LIGBT when the semiconductor device is in the on state.
Japanese Patent Application Laid-Open No. 8-213617

  However, the semiconductor device described in Patent Document 1 in which the lateral power MOS and the LIGBT are formed on the same substrate has the same breakdown voltage and on-state as compared with the semiconductor device on which only one of the lateral power MOS and the LIGBT is mounted. The area of the semiconductor device necessary for obtaining the resistance increases.

  In view of the above problems, an object of the present invention is to provide a small-sized semiconductor device that operates as a LIGBT and has a small switching loss, and a manufacturing method thereof.

  In order to achieve the above object, a semiconductor device according to the present invention includes a first conductivity type semiconductor substrate, a second conductivity type first drift region formed on a surface of the semiconductor substrate, and the first drift region. A first conductivity type collector region formed on the surface; a second conductivity type source region formed on the surface of the semiconductor substrate at a distance from the first drift region; and the source region adjacent to the source region. A first conductivity type emitter region formed on the surface of the semiconductor substrate, an emitter electrode formed on the semiconductor substrate in contact with the source region and the emitter region, and between the first drift region and the source region A gate electrode formed on the semiconductor substrate via a gate oxide film, a collector electrode formed on the semiconductor substrate so as to be positioned above the collector region, and the collector region A drain region of a second conductivity type formed on the surface of the semiconductor substrate and located in the drain region so as to be positioned between the collector electrode and the collector region and the collector electrode; And a collector connection region of the first conductivity type.

  With this configuration, the semiconductor device operates as a LIGBT. The semiconductor device also operates as a lateral power MOS when a predetermined voltage is applied to the gate electrode and a voltage is further applied to the collector electrode. By starting the lateral power MOS before the rising voltage of the LIGBT, the time required for the LIGBT to turn on is shortened, and the switching loss is reduced. Therefore, a small semiconductor device that operates as a LIGBT and has little switching loss can be realized.

  In addition, since the collector region of the LIGBT is formed immediately below the drain region, the area of the collector region effective against the on-current can be reduced as compared with the case where the drain region and the collector region are formed planarly under the collector electrode. The on-current can be increased. Therefore, since the on-current can be increased without increasing the area of the LIGBT, a small semiconductor device capable of increasing the on-current can be realized.

  Here, the emitter region is located below the source region, and the semiconductor device is further formed in the source region and electrically connected to the emitter region and the emitter electrode. An emitter connection region may be provided.

  With this configuration, the area of the emitter region having a high impurity concentration can be increased, so that the on-current when the LIGBT is turned on increases. As a result, a semiconductor device capable of further increasing the on-current can be realized.

  The semiconductor device may further include a first conductivity type second drift region formed on a surface of the first drift region.

  With this configuration, the depletion layer formed at the junction between the semiconductor substrate and the first drift region when the LIGBT is turned off, and the depletion layer formed at the junction between the first drift region and the second drift region, The entire drift region can be efficiently depleted. For this reason, since the breakdown voltage can be secured even when the impurity concentration of the first drift region is increased, a semiconductor device capable of reducing the on-resistance can be realized.

  The semiconductor device may further include a first conductivity type third drift region embedded in the first drift region.

  With this configuration, the depletion layer formed at the junction between the semiconductor substrate and the first drift region when the LIGBT is turned off, and the depletion layer formed at the junction between the first drift region and the third drift region, The entire one drift region can be more efficiently depleted. For this reason, since the breakdown voltage can be secured even when the impurity concentration of the first drift region is further increased, a semiconductor device capable of further reducing the on-resistance can be realized.

  The semiconductor device may further include a plurality of first conductivity type fourth drift regions formed at different depths in the first drift region.

  With this configuration, the first drift region is more efficiently depleted, so that a semiconductor device that can further reduce the on-resistance can be realized.

  The present invention also provides a first step of forming a first conductivity type first drift region on a surface of a first conductivity type semiconductor substrate, and a first step of forming a gate electrode on the semiconductor substrate via a gate oxide film. And after ion implantation of a first conductivity type impurity into each of the semiconductor substrate and the first drift region, heat treatment of the semiconductor substrate is performed to form a first conductivity type emitter region and a collector region. A third step of performing ion implantation of impurities of a second conductivity type into each of the semiconductor substrate and the collector region, and then heat-treating the semiconductor substrate to perform second conductivity at a higher impurity concentration than the collector region. The semiconductor device manufacturing method may include a fourth step of simultaneously forming the source and drain regions of the mold and the collector connection region of the first conductivity type.

  With this manufacturing method, a small semiconductor device with a small switching loss that operates as a LIGBT can be easily manufactured with a small number of steps. In addition, a small semiconductor device capable of increasing the on-current can be easily manufactured with a small number of steps.

  Here, in the fourth step, ion implantation of a second conductivity type impurity is performed in each of the emitter region and the collector region, and a source region and a drain region of the second conductivity type with a higher impurity concentration than the emitter region. In addition, the collector connection region and the emitter connection region of the first conductivity type may be formed at the same time.

  With this manufacturing method, a small semiconductor device capable of increasing the on-current can be easily manufactured with a small number of steps.

  The method for manufacturing a semiconductor device may further include a fifth step of forming a first conductivity type second drift region by ion implantation of a first conductivity type impurity in the first drift region.

  With this manufacturing method, a semiconductor device capable of reducing the on-resistance can be easily manufactured.

  According to the present invention, a drain region serving as a drain of the lateral power MOS is formed between the collector region of the LIGBT and the collector electrode, and further for electrically connecting the collector region and the collector electrode in the drain region. Since the collector connection region is formed, the LIGBT operates as a lateral power MOS when a predetermined voltage is applied to the gate electrode of the LIGBT and a voltage is further applied to the collector electrode. By starting the lateral power MOS before the rising voltage of the LIGBT, the time required for the LIGBT to turn on is shortened, and the switching loss is reduced. Therefore, a small LIGBT with little switching loss can be realized.

  In addition, since the LIGBT collector region is formed immediately below the drain region, the area of the collector region effective against the on-current can be reduced compared to the case where the drain region and the collector region are planarly formed below the collector electrode. The on-current can be increased. Therefore, it is possible to realize a LIGBT that can increase the on-current without increasing the area of the LIGBT.

  Further, in the step of forming the collector region of the LIGBT, after ion implantation is performed in the drift region and the first conductivity type collector region is formed by diffusion of impurities by heat treatment, the collector region has a higher impurity concentration than the collector region. The second conductivity type drain region and the collector connection region in the drain region are formed at the same time by implanting ions into portions other than the region where the collector connection region is formed and diffusing impurities by heat treatment. Therefore, a small LIGBT with little switching loss can be easily manufactured with a small number of steps.

  A drift region of the first conductivity type is formed on the surface of the drift region of the second conductivity type. Therefore, a depletion layer formed at the junction between the first conductivity type semiconductor substrate and the second conductivity type drift region when the LIGBT is turned off, and the second conductivity type drift region and the first conductivity type drift region The entire drift region can be efficiently depleted by the depletion layer formed at the junction. As a result, a breakdown voltage can be ensured even when the impurity concentration of the drift region of the second conductivity type is increased, so that a LIGBT that can reduce on-resistance can be realized.

  Also, a first conductivity type drift region is formed on the surface of the second conductivity type drift region by ion implantation. Therefore, a LIGBT that can reduce on-resistance can be easily manufactured.

  Hereinafter, semiconductor devices according to embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a schematic cross-sectional view showing the structure of the LIGBT according to the first embodiment of the present invention. This LIGBT is an example of the semiconductor device of the present invention.

This LIGBT is formed on a p-type silicon (Si) substrate 100 having an impurity concentration of about 1E14 cm ⁻³ to 1E17 cm ⁻³ . Some of the p-type silicon (Si) surface of the substrate 100, n-type drift region 101 of about 8μm impurity concentration from 4μm thickness in 5E16cm about ^-3 to 1E14 cm ^-3 is formed, n-type drift region 101 A p-type low-concentration emitter region 102 having an impurity concentration of about 1E16 cm ⁻³ to 1E17 cm ⁻³ is formed adjacent to. A high impurity concentration n-type source region 103 is formed on a part of the surface of the p-type low-concentration emitter region 102. A gate oxide film 104 made of silicon oxide (SiO ₂ ) is formed above a part of the surface of the p-type low-concentration emitter region 102 and the n-type drift region 101 sandwiched between the n-type drift region 101 and the n-type source region 103. A gate electrode 105 made of polysilicon (poly-Si) is formed therethrough. A high impurity concentration p-type emitter region 106 having an impurity concentration higher than that of the p-type low-concentration emitter region 102 is formed on the surface of the p-type low-concentration emitter region 102. On the upper side, an emitter electrode 107 made of an aluminum alloy such as AlSiCu is formed. Further, an n-type buffer region 108 having an impurity concentration higher than that of the n-type drift region 101 is formed on the surface of the n-type drift region 101, and an n-type drain region 109 having a high impurity concentration is formed on the surface of the n-type buffer region 108. A collector electrode 111 made of an aluminum alloy such as AlSiCu is formed above the n-type drain region 109. A high impurity concentration p-type collector region 110 a is formed immediately below the n-type drain region 109. The collector electrode 111 is electrically connected to the p-type collector region 110 a by a high impurity concentration p-type collector connection region 110 b formed in a part of the n-type drain region 109. Further, an isolation layer 112 made of silicon oxide (SiO ₂ ) for isolating the transistors is formed on the p-type silicon (Si) substrate 100 so as to be located above the n-type drift region 101. Between the gate electrode 105 and the emitter electrode 107 and the collector electrode 111, an interlayer insulation composed of a laminated structure of silicon oxide (SiO ₂ ) and boron-phosphorus-doped silicate glass (BPSG) for separating the electrodes. A film 113 is formed, and a protective film 114 made of silicon nitride (SiN) is formed thereon.

  The LIGBT of FIG. 1 operates as a lateral power MOS when a predetermined voltage is applied to the gate electrode 105 of the LIGBT and a predetermined voltage is further applied to the collector electrode 111. Therefore, the lateral power MOS is raised before the rising voltage of the LIGBT, the time required for the LIGT to be turned on is shortened, and the switching loss can be reduced. In addition, since the p-type collector region 110a of the LIGBT is formed immediately below the n-type drain region 109, the n-type drain region 109 and the p-type collector region 110a are formed planarly below the collector electrode 111. The area of the p-type collector region 110a effective for the on-current can be increased, and the on-current can be increased. Therefore, it is possible to realize a LIGBT that can increase the on-current without increasing the area of the LIGBT and that can operate as a lateral power MOS. That is, a small LIGBT with a small switching loss that can increase the on-current can be realized.

  As shown in FIG. 2, a p-type emitter region 115a is formed immediately below the n-type source region 103, and the p-type emitter region 115a and the emitter electrode 107 are electrically connected by the p-type emitter connection region 115b. It is good also as such a structure. By doing so, since the area of the p-type emitter region having a high impurity concentration can be increased, an on-current when the LIGBT is turned on increases, and a LIGBT with further reduced switching loss can be realized.

  Next, the manufacturing method of LIGBT of FIG. 1 is demonstrated using FIGS. 3 is a cross-sectional view showing a process of forming the n-type drift region 101 of the LIGBT, and FIG. 4 is a cross-sectional view showing a process of forming the p-type low-concentration emitter region 102 and the isolation layer 112 of the LIGBT. 5 is a cross-sectional view showing a process of forming the gate oxide film 104 and the gate electrode 105 of the LIGBT, and FIG. 6 is a cross-sectional view showing a process of forming the n-type buffer region 108 of the LIGBT. 7 is a cross-sectional view showing a process of forming the p-type collector region 110a and the p-type emitter region 106 of the LIGBT. FIG. 8 shows an n-type drain region 109, a p-type collector connection region 110b of the LIGBT, FIG. 9 is a cross-sectional view showing a process of forming an n-type source region 103. FIG. 9 shows an interlayer insulating film 113, an emitter electrode 107, and a collector electrode 111 of the same LIGBT. It is a cross-sectional view showing a step of forming a fine protective film 114.

First, as shown in FIG. 3, phosphorus ions are implanted into a desired position using a resist pattern on a p-type silicon (Si) substrate 100 having an impurity concentration of about 1E14 cm ⁻³ to 1E17 cm ⁻³ . Thereafter, the impurity concentration by thermal diffusion heat treatment is performed to the p-type silicon (Si) substrate 100 as n-type drift region 101 of about 8μm from 4μm thickness in 5E16cm about ^-3 to 1E16 cm ^-3 is formed.

Next, as shown in FIG. 4, boron ions are implanted into a desired position using a resist pattern in a p-type silicon (Si) substrate 100. Thereafter, a separation layer 112 made of silicon oxide (SiO ₂ ) is formed by a thermal oxidation method using a SiN mask. This thermal oxidation process causes thermal diffusion of the implanted boron, and a p-type low-concentration emitter region 102 having an impurity concentration of about 1E16 cm ⁻³ to 1E17 cm ⁻³ is formed.

Next, as shown in FIG. 5, after a silicon oxide (SiO ₂ ) film and a polysilicon (poly-Si) film are formed on the entire wafer, a silicon oxide (SiO ₂ ) film and polysilicon ( The poly-Si) film is etched to form a gate oxide film 104 made of silicon oxide (SiO ₂ ) and a gate electrode 105 made of polysilicon (poly-Si).

Next, as shown in FIG. 6, phosphorus ions are implanted into a desired position using a resist pattern in the n-type drift region 101. Thereafter, a heat treatment is performed to the p-type silicon (Si) substrate 100 as n-type buffer region 108 of about 5E16 cm ^-3 impurity concentration from 1E16 cm ^-3 is formed by thermal diffusion.

Next, as shown in FIG. 7, boron ions are implanted into desired positions using resist patterns in the n-type buffer region 108 and the p-type low-concentration emitter region 102. Thereafter, the p-type silicon (p-type silicon region 110a and p-type emitter region 106 having an impurity concentration of about 1E18 cm ⁻³ to 1E19 cm ⁻³ and a depth of about 0.5 μm to 1 μm are simultaneously formed by thermal diffusion. Si) The substrate 100 is subjected to heat treatment.

Next, as shown in FIG. 8, arsenic ions are implanted into desired positions using a resist pattern in the n-type buffer region 108 (p-type collector region 110a) and the p-type low-concentration emitter region 102. Thereafter, an interlayer insulating film 113 having a laminated structure of silicon oxide (SiO ₂ ) and boron / phosphorus-added silicate glass (BPSG) is formed, and then BPSG is reflowed by heat treatment to flatten the surface. By this heat treatment, higher than the impurity concentration of the p-type collector region 110a impurity concentration in 1E20cm about ^-3 to 1E19 cm ^-3, the depth of about 0.4μm from 0.2 [mu] m n-type drain region 109 and the n-type source region 103 and the p-type collector connection region 110b are formed simultaneously. At this time, ion implantation into the p-type collector region 110a is performed so that arsenic is not implanted into the region where the p-type collector connection region 110b is formed.

  Next, as shown in FIG. 9, after etching a desired region of the interlayer insulating film 113 using a resist pattern, an aluminum alloy film such as AlSiCu is formed by sputtering. Thereafter, a desired region of the aluminum alloy film is etched using the resist pattern to form the emitter electrode 107 and the collector electrode 111. Then, after a protective film 114 made of silicon nitride (SiN) is formed on the entire surface by plasma CVD, the pad portion is opened by dry etching using a resist pattern. Thereby, the LIGBT of FIG. 1 is formed.

  By using such a manufacturing method, a double structure of the n-type drain region 109 and the p-type collector region 110a electrically connected to the collector electrode through the p-type collector connection region 110b can be formed. A LIGBT that can also operate as a power MOS can be easily manufactured.

  Next, the manufacturing method of LIGBT of FIG. 2 is demonstrated using FIGS. FIG. 10 is a cross-sectional view showing a process of forming the p-type collector region 110a and the p-type emitter region 115a of the LIGBT. FIG. 11 shows the n-type drain region 109, p-type collector connection region 110b, p of the LIGBT. FIG. 12 is a cross-sectional view showing a process of forming the n-type emitter connection region 115b and the n-type source region 103. FIG. 12 shows a process of forming the interlayer insulating film 113, the emitter electrode 107, the collector electrode 111, and the protective film 114 of the LIGBT. It is sectional drawing shown.

  First, the steps shown in FIGS. 3 to 6 are performed.

  Next, as shown in FIG. 10, boron ions are implanted into desired positions using a resist pattern in the n-type buffer region 108 and the p-type low-concentration emitter region 102. Thereafter, heat treatment is performed on the p-type silicon (Si) substrate 100 so that the p-type collector region 110a and the p-type emitter region 115a are formed by thermal diffusion.

Next, as shown in FIG. 11, arsenic ions are implanted into desired positions using a resist pattern in the n-type buffer region 108 (p-type collector region 110a) and the p-type emitter region 115a. Thereafter, an interlayer insulating film 113 having a laminated structure of silicon oxide (SiO ₂ ) and boron / phosphorus-added silicate glass (BPSG) is formed, and then BPSG is reflowed by heat treatment to flatten the surface. By this heat treatment, an n-type drain region 109 and an n-type source region 103 that are higher in impurity concentration than the p-type emitter region 115a, and a p-type collector connection region 110b and a p-type emitter connection region 115b are simultaneously formed. At this time, ion implantation into the p-type emitter region 115a is performed so that arsenic is not implanted into the region where the p-type emitter connection region 115b is formed.

  Next, as shown in FIG. 12, after etching a desired region of the interlayer insulating film 113 using a resist pattern, an aluminum alloy film such as AlSiCu is formed by sputtering. Thereafter, a desired region of the aluminum alloy film is etched using the resist pattern to form the emitter electrode 107 and the collector electrode 111. Then, after a protective film 114 made of silicon nitride (SiN) is formed on the entire surface by plasma CVD, the pad portion is opened by dry etching using a resist pattern. Thereby, the LIGBT of FIG. 2 is formed.

  By using such a manufacturing method process, the p-type emitter region 115a is formed immediately below the n-type source region 103, and the p-type emitter region 115a and the emitter electrode 107 are electrically connected by the p-type emitter connection region 115b. Thus, the area of the high impurity concentration emitter region can be increased. As a result, the ON current when the LIGBT is turned on increases, and the LIGBT with further reduced switching loss can be easily manufactured.

(Second Embodiment)
FIG. 13 is a schematic cross-sectional view showing the structure of the LIGBT according to the second embodiment of the present invention. This LIGBT is an example of the semiconductor device of the present invention. In FIG. 13, the same components as those in FIG. 1 are denoted by the same reference numerals.

The LIGBT is formed on a p-type silicon (Si) substrate 100. An n-type drift region 101 is formed on a part of the surface of the p-type silicon (Si) substrate 100. The n-type drift region 101 has a thickness of about 1 μm and an impurity concentration of 1E16 cm ⁻³ to 3E16 cm ^−3. About a p-type drift region 116 is formed. The p-type drift region 116 is electrically connected to the p-type silicon (Si) substrate 100.

  With this configuration, a depletion layer is formed between the n-type drift region 101 and the p-type drift region 116 when the LIGBT is turned off, so that a higher breakdown voltage can be ensured. Therefore, by increasing the impurity concentration of the n-type drift region 101, it is possible to reduce the on-resistance as compared with the LIGBT of the first embodiment. Therefore, in the LIGBT of this embodiment, the on-resistance can be reduced at the same time as the switching loss is reduced.

Incidentally, as shown in FIG. 14, a depth of about 1.2μm from the surface to the n-type drift region 101, a p-type drift region 117 is an impurity concentration of 1E16 cm ^-3 of about 3E16cm ^-3 with a thickness of 1μm about An embedded structure may be used. In this way, when the LIGBT is turned off, the junction between the n-type drift region 101 and the p-type drift region 117 spreads, and a depletion layer is formed at the junction, so that a higher breakdown voltage can be ensured. Further, by increasing the impurity concentration of the n-type drift region 101, it is possible to reduce the on-resistance as compared with the LIGBT of the first embodiment. Therefore, in the LIGBT of this embodiment, the on-resistance can be reduced at the same time as the switching loss is reduced.

  Further, as shown in FIG. 15, a plurality of p-type drift regions 118 a and 118 b may be formed in the n-type drift region 101 at different depths. In this case, the switching loss and the on-resistance can be further reduced as compared with the case where one n-type drift region is embedded in the n-type drift region 101.

  Next, a method for manufacturing the LIGBT of FIG. 13 will be described with reference to FIGS. The manufacturing method of the LIGBT is almost the same as the manufacturing method of the LIGBT according to the first embodiment, and only the step of forming the p-type drift region 116 shown in the cross-sectional view of FIG. 16 is added. Is different. For this reason, it demonstrates below centering on the process different from the process in the manufacturing method of LIGBT which concerns on 1st Embodiment.

  First, the steps shown in FIGS. 3 to 6 are performed. As a result, the n-type drift region 101, the separation layer 112, the p-type low-concentration emitter region 102, the gate oxide film 104, the gate electrode 105, and the n-type buffer region 108 are formed on the p-type silicon (Si) substrate 100.

Next, as shown in FIG. 16, boron ions are implanted into a desired position using a resist pattern in the n-type drift region 101 at a dose of about 4E12 cm ^{−2 and} an acceleration voltage of about 600 keV. Thereafter, heat treatment is performed on the p-type silicon (Si) substrate 100 so that the p-type drift region 116 having an impurity concentration of about 1E16 cm ⁻³ to 3E16 cm ⁻³ is formed by thermal diffusion.

Next, as shown in FIG. 7 to FIG. 9, an interlayer composed of a p-type collector region 110a, a p-type emitter region 106, and a laminated structure of silicon oxide (SiO ₂ ) and boron-phosphorus-doped silicate glass (BPSG). An insulating film 113, an n-type drain region 109, a p-type collector connection region 110b, an n-type source region 103, a p-type emitter region 106, an emitter electrode 107, and a collector electrode 111 are formed, and silicon nitride is further formed. A protective film 114 made of (SiN) is formed. Thereby, the LIGBT of FIG. 13 is formed.

  By using such a manufacturing method, a LIGBT that can secure a breakdown voltage even when the impurity concentration of the n-type drift region 101 is increased and can further reduce the on-resistance as compared with the LIGBT of the first embodiment. It can be manufactured easily.

  The present invention is useful for switching elements and the like, and particularly useful for power LIGBTs and the like formed on the same substrate as the control circuit and protection circuit.

It is a typical sectional view of LIGBT of a 1st embodiment of the present invention. It is typical sectional drawing of the modification of LIGBT which concerns on the embodiment. It is sectional drawing of LIG for demonstrating the manufacturing method of LIGBT of the embodiment. It is sectional drawing of LIG for demonstrating the manufacturing method of LIGBT of the embodiment. It is sectional drawing of LIG for demonstrating the manufacturing method of LIGBT of the embodiment. It is sectional drawing of LIG for demonstrating the manufacturing method of LIGBT of the embodiment. It is sectional drawing of LIG for demonstrating the manufacturing method of LIGBT of the embodiment. It is sectional drawing of LIG for demonstrating the manufacturing method of LIGBT of the embodiment. It is sectional drawing of LIG for demonstrating the manufacturing method of LIGBT of the embodiment. It is sectional drawing of LIGBT for demonstrating the manufacturing method of the modification of LIGBT of the embodiment. It is sectional drawing of LIGBT for demonstrating the manufacturing method of the modification of LIGBT of the embodiment. It is sectional drawing of LIGBT for demonstrating the manufacturing method of the modification of LIGBT of the embodiment. It is typical sectional drawing of LIGBT of the 2nd Embodiment of this invention. It is typical sectional drawing of the modification of LIGBT of the embodiment. It is typical sectional drawing of the modification of LIGBT of the embodiment. It is sectional drawing of LIG for demonstrating the manufacturing method of LIGBT of the embodiment. It is typical sectional drawing of the conventional semiconductor device.

Explanation of symbols

21 p ⁻ type semiconductor substrate 22, 22a, 22b n ⁻ type epitaxial layer 23 trench well 24 electrically insulating layer 25, 26 trench well wall 27 trench well filling material 28, 30, 36 n ⁺ type region 29, 35 p type well 31, 34, 37 p ⁺ type region 32 Source electrode 33, 39 Oxide layer 38 Cathode electrode 40, 41 Gate electrode 42 Anode electrode 43 Drain electrode 100 p-type silicon (Si) substrate 101 n-type drift region 102 p-type low concentration emitter Region 103 n-type source region 104 gate oxide film 105 gate electrode 106 p-type emitter region 107 emitter electrode 108 n-type buffer region 109 n-type drain region 110a p-type collector region 110b p-type collector connection region 111 collector electrode 112 separation layer 113 interlayer Absolute Edge film 114 Protective film 115a p-type emitter region 115b p-type emitter connection region 116 p-type drift region 117, 118a, 118b p-type drift region

Claims (8)

A first conductivity type semiconductor substrate;
A first conductivity type first drift region formed on the surface of the semiconductor substrate;
A first conductivity type collector region formed on the surface of the first drift region;
A source region of a second conductivity type formed on the surface of the semiconductor substrate spaced from the first drift region;
A first conductivity type emitter region formed on a surface of the semiconductor substrate adjacent to the source region;
An emitter electrode formed on the semiconductor substrate in contact with the source region and the emitter region;
A gate electrode formed on a semiconductor substrate between the first drift region and the source region via a gate oxide film;
A collector electrode formed on the semiconductor substrate so as to be located above the collector region;
A drain region of a second conductivity type formed on the surface of the semiconductor substrate so as to be located between the collector region and the collector electrode;
A semiconductor device comprising: a first conductivity type collector connection region formed in the drain region and electrically connecting the collector region and the collector electrode. The emitter region is located below the source region;
The semiconductor device according to claim 1, further comprising a first conductivity type emitter connection region formed in the source region and electrically connecting the emitter region and the emitter electrode. apparatus. The semiconductor device according to claim 1, further comprising a second conductivity region of a first conductivity type formed on a surface of the first drift region. The semiconductor device according to claim 1, further comprising a third drift region of a first conductivity type embedded in the first drift region. The semiconductor device according to claim 1, further comprising a plurality of first conductivity type fourth drift regions formed at different depths in the first drift region. Forming a first conductivity type first drift region on a surface of a first conductivity type semiconductor substrate;
A second step of forming a gate electrode on the semiconductor substrate through a gate oxide film;
A third step of forming a first conductivity type emitter region and a collector region by ion-implanting a first conductivity type impurity into each of the semiconductor substrate and the first drift region, and then heat-treating the semiconductor substrate. When,
After ion implantation of a second conductivity type impurity into each of the semiconductor substrate and the collector region, heat treatment of the semiconductor substrate is performed, so that the second conductivity type source region and drain are higher in impurity concentration than the collector region. A method for manufacturing a semiconductor device, comprising: a fourth step of simultaneously forming a region and a collector connection region of a first conductivity type. In the fourth step, ion implantation of a second conductivity type impurity is performed in each of the emitter region and the collector region, and a second conductivity type source region and drain region having a higher impurity concentration than the emitter region, The method for manufacturing a semiconductor device according to claim 6, wherein a collector connection region and an emitter connection region of one conductivity type are formed simultaneously. The method for manufacturing a semiconductor device further includes a fifth step of forming a first conductivity type second drift region by performing ion implantation of a first conductivity type impurity in the first drift region. A method for manufacturing a semiconductor device according to claim 6.

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