JPS60241266A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To remove the kink phenomenon in the current-voltage characteristic or the threshold voltage characteristic by a method wherein the titled device formed on an insulator is newly provided with two pieces of electrode which are penetrable to the majority carrier of an active layer. CONSTITUTION:After the active layer 22 of required form isolated by an insulator layer 20 is formed on the upper surface of a semiconductor substrate 50, a gate insulation film 24 is formed on this active layer 22. Next, a gate electrode 26 is formed thereon; then, the first source region 28 and the first drain region 30 are formed by ion implantation, using a mask. The second drain region 32 and the second source region 34 are formed by ion implantation, using another mask. Afterwards, an insulation layer 36 is deposited over the substrate 50, and electrodes 38 and 40 are formed by boring contact holes above the source and drain regions, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device formed on an insulator and a method for manufacturing the same, and in particular to a method for reducing parasitic bipolar effects such as kink phenomenon in current-voltage characteristics. The present invention relates to a semiconductor device (not shown) and a method for manufacturing the same.

[Prior art]

FIG. 1 shows a conventional general structure of a semiconductor device formed on an insulator. Note that FIG. 1(a) is a plan layout diagram, and FIG. 1(b) is a sectional view.

In the figure, 2 is an insulating substrate, 4 is an active layer made of a p-type semiconductor, 6 is a gate insulating film, 8 is a gate electrode, 10 is a source region made of an n-type semiconductor, 12 is a drain region made of an n-type semiconductor, and 14 is a source. The electrode 16 is a drain electrode.

This semiconductor device is used by grounding the source electrode 14, applying a positive drain voltage to the drain electrode 16, and applying a positive gate voltage to the gate electrode 8.

At this time, when the drain voltage is increased, a weak avalanche phenomenon occurs in the depletion layer generated near the junction with the n-type drain region 12 in the region of the active layer 4 due to the high electric field strength. That is, pairs of holes and electrons are generated one after another within the depletion layer, and the electrons flow into the n-type drain region 12, but some of the holes are injected into the n-type source region 10, and the other part is injected into the n-type source region 10. - Temporarily remains in active layer 4.

This means that the potential of the active layer 4 becomes higher, resulting in a lower threshold voltage of the device and an increase in the drain current. That is, a first kink appears as shown by arrow A in the current-voltage characteristic diagram of FIG. 1 and FIG. 2(a).

As the drain voltage is further increased, the rate at which electrons are back-injected from the n-type source region 10 to the active N4 increases.
This causes an increase in drain current and promotes avalanche. As a result, the well-known parasitic high hole operation region where the drain current increases more and more is entered, and the drain current increases significantly. This is the second kink shown by arrow B in FIG. 2(a).

Further, in the threshold voltage characteristic diagram of FIG. 2(b), a kink appears as indicated by arrow C. Note that the broken line in the figure shows the characteristics when no kink appears.

These kink phenomena significantly increase distortion when signals are amplified by this semiconductor device.

Therefore, in order to eliminate the genuine tag generated in the active layer that causes the kink, it has been conventionally considered to add a region of the same conductivity type as the active layer to the source region.

That is, as shown in the plan layout and cross-sectional view of FIG.
By configuring these, holes generated in the active layer 4 are absorbed by the p-type source region 18, and an increase in the potential of the active layer 4 is prevented. However, in this semiconductor device, it was not possible to completely suppress the rise in potential of the active layer 4, and the kink phenomenon could not be completely eliminated.

[Summary of the invention]

The present invention has been made in view of the above problems, and its purpose is to completely eliminate the kink phenomenon in current-voltage characteristics or threshold voltage characteristics. An object of the present invention is to provide a semiconductor device that exhibits good signal amplification characteristics.

In order to achieve this object, the present invention provides two new electrodes (vA region) through which the majority carriers of the active layer can pass.

Hereinafter, the present invention will be described in detail along with examples.

[Embodiment] FIG. 4(a) is a plan layout diagram showing an embodiment of the present invention, and FIG. 4(b) and (c) are V-w and x-y sectional views, respectively. Note that in FIG. 4(a), for the sake of simplicity, a first source electrode, a first drain electrode, an insulator layer, etc., which will be described later, are omitted.

22 is a p-type active layer formed on the insulator layer 20. 24 is a gate insulating film 24 formed on the active layer 22
Further, a gate electrode 26 is formed thereon. Note that the active layer 22 below the gate electrode 26 is divided into a depleted region 22a and a non-depleted region 22b during operation.

A first source region 28 is formed of an n-type high impurity concentration semiconductor at one end of the active layer 22, and a first source electrode 38 is formed thereon. A first drain region 30 is also made of an n-type semiconductor with a high impurity concentration, and is formed at one end of the active layer 22 on the side opposite to the first source region 28, on which a first drain electrode is formed. 40 is formed.

A second drain region 32 is formed at another end of the active layer 22 using a p-type high impurity concentration semiconductor, and a second drain electrode 42 is formed thereon. 34 is the same (the second one formed of a p-type high impurity concentration semiconductor)
A source region and a second drain N+43 of the active layer 22
2, and a second source electrode 44 is formed thereon. Each electrode 38.40,
42 and 44 are electrically insulated from each other by an insulator layer 36.

Note that the direction from the first drain region 30 to the first source region 28 and the direction from the second drain region 32 to the second source region 34 refer to the active layer 2 below the gate electrode 26.
They intersect each other at 2.

Next, the operation of the semiconductor device configured as described above will be explained.

First, the first source electrode 38 and the second drain electrode 42 are connected, the second source electrode 44 is grounded, and a positive voltage is applied to the first drain electrode 40 . In this state, the gate electrode 2
When a positive voltage is applied to 6, a depleted region 22a is generated in the active layer 22, and an inversion layer is formed at the interface between the active layer 22 and the gate insulating film 24.

As a result, the first
A current flows from the drain region 30 to the first source region 28, and this current further flows from the first source region 28 to the second drain region 32 via the connection line 46, and then flows through the non-depleted region 22b to the second drain region 32. from there to the second source region 34 .

When a current flows in this way, the potential of the portion of the non-depleted region 22b closer to the second source region 34 is different from the potential of the second drain region 32 and the second drain region 32.
It becomes lower by the potential difference between the source region 34 and the source region 34 . Also,
The potential of the portion of the non-depleted region 22b closer to the second source region 34 is close to the potential of the second drain region 32, but is slightly lower.

Therefore, the depletion region 22 near the first drain region 30
Holes generated by weak avalanche inside the region a enter the non-depleted region 22b, but are not injected into the first source region 28 and flow toward the lower potential (A second source region 34). Therefore, no kink phenomenon appears.

Note that in this embodiment, the direction from the first drain region 30 to the first source region 28 and the direction from the second drain region 32 to the second source region 34 are perpendicular to each other; It is sufficient that the active layer 22 intersects, and the intersecting angle does not need to be exactly 90 degrees.

Furthermore, the insulating layer 20 may be a so-called semi-insulating layer.

Next, an embodiment of the method for manufacturing a semiconductor device of the present invention will be described with reference to FIG. Figures 5(a) and (b).

(c) and (e) are cross-sectional views of the semiconductor device in the manufacturing process, and (d) of the same figure is a plan view corresponding to (C) of the same figure.

First, approximately 10111 oxygen ions/d are implanted into the inside of the semiconductor substrate 50 at a predetermined energy using an ion implantation method, and then heat-treated at a predetermined temperature for a predetermined time to form a fixed amount of oxygen ions at a predetermined depth. Thickness of insulation layer 2
0 (FIG. 5(a)). As a result, the active layer 22 separated by the insulating layer 20 is formed on the upper surface of the semiconductor substrate 50.

Next, the active layer 22 formed on the upper surface of the semiconductor substrate 50
is shaped into a predetermined dimension by etching, and then a gate insulating film 24 is formed on the active layer 22 by a method such as oxidation (FIG. 5(b)).

Next, a gate electrode material is deposited on the gate insulating film 24, and the gate electrode material is shaped into a predetermined size by etching to form a gate electrode 26.

- After that, a mask is made leaving the parts of the peripheral part of the active layer 22 that are to become the first source region 28 and the first drain region 30, and an n-type dopant is implanted into these parts by ion implantation or the like to form an n-type The first layer is made of a highly impurity-concentrated semiconductor.
A source region 28 and a first drain region 30 are formed, and the mask is removed.

Similarly, the second drain region 32 and the second source region 34
A second drain region 32 and a second source region 34 made of a p-type high impurity concentration semiconductor are formed by making a mask and implanting a p-type impurity into the regions that should become .
is formed, and then the mask is removed (Fig. 5(c), (
d)).

Next, an insulating layer 36 is deposited over the entire surface of the semiconductor substrate 50 and the first source region 28 . First drain region 30. Second
Contact holes are formed above the drain region 32 and the second source region 34 by etching. Note that 52 and 54 indicate contact holes formed above the first source region 28 and first drain region 3o, respectively.

Next, a lead-out electrode is formed on each contact ball by a vapor deposition method or the like. Reference numerals 38 and 40 are lead-out electrodes formed in the contact holes 52 and 54, which become the first drain electrode and the first source electrode, respectively (see FIG.
e)).

Note that mask processing is used when forming the first source region, first drain region, second source region, and second drain region, and predetermined impurities are partially and selectively added to each region. It doesn't matter if you type it in.

Further, the step of forming the active layer 22 on the insulator layer 20 (
In FIG. 5(a), it is not necessarily necessary to use the ion implantation method as in the above embodiment, and other well-known methods for forming a semiconductor layer on an insulating layer may be used.

〔Effect of the invention〕

As explained above, according to the semiconductor device of the present invention, the electrode (region) through which the majority carriers of the active layer can pass
Since two new elements are provided, the kink phenomenon in current-voltage characteristics or threshold voltage characteristics can be completely eliminated.

Therefore, (1) this type of device is known to perform a high-speed switching operation, and in addition, it is possible to amplify a signal with low distortion. (2) Noise accompanying the kink phenomenon can be removed, which is effective in reducing noise. (3) Since the holes (majority carriers) generated near the first drain region are extracted without being injected into the first source region, the breakdown voltage between the first drain region and the first source region due to the parasitic bipolar effect is improved; There are various advantages such as an increase in the maximum usable power supply voltage value.

Further, according to the manufacturing method of the present invention, an excellent semiconductor device can be easily realized without using any special manufacturing process.

[Brief explanation of the drawing]

Figure 1(a) is a plan layout showing a conventional general configuration of a semiconductor device formed on an insulator, Figure 1(b) is a cross-sectional view, and Figure 2(a) is a current-voltage characteristic. Figure, same figure (b)
3(a) is a planar layout diagram showing the structure of another conventional semiconductor device, FIG. 3(b) is a cross-sectional view, and FIG. 4(a) is a diagram of one of the present invention. A plan layout diagram showing an embodiment, FIGS. 5(b) and 5(c) are v-w and x-y sectional views, respectively, and FIG. 5 shows an embodiment of the semiconductor device manufacturing method of the present invention. (a), (b), (c), and (e) are sectional views of the semiconductor device in the manufacturing process, respectively, and (d) is a plan view corresponding to (C). 20... Insulator layer, 22... Active layer, 24... Gate insulating film, 26... Gate electrode, 28... First source region, 30... First drain region, 32... ...Second drain region, 34...Second source region, 36...
- Insulator layer, 38... first source electrode, 40... first drain electrode, 42... second drain electrode, 44...
...Second source electrode, 50...Semiconductor substrate 50゜Patent applicant: Nippon Telegraph and Telephone Public Corporation Agent: Nariyo Yamakawa (and one other person) Fig. 1 □ Ro 32 Fig. 3 Fig. 4 Fig. 6

Claims (1)

[Scope of claims] a first drain region made of a second conductivity type high impurity concentration semiconductor formed at one end of the layer and on the opposite side of the first source region;
a second source region made of a first conductivity type high impurity concentration semiconductor formed at one end of the active layer and different from the first source region and the first drain region; and one end of the active layer. a second drain region made of a first conductivity type high impurity concentration semiconductor formed on the opposite side of the second source region; and a gate electrode formed on the top of the active layer with an insulating film interposed therebetween; a first source electrode formed on the first source region; a first drain electrode formed on the first drain region; a second source electrode formed on the second source N region; A semiconductor device comprising: a second drain electrode formed on a second drain region. (2) forming an active layer of a first conductivity type to a predetermined size on an insulating layer or a semi-insulating layer; forming an insulating film on the active layer; and forming an insulating film on the insulating film. forming a gate electrode; forming a first source region made of a second conductivity type high impurity concentration semiconductor at one end of the active layer; forming a first drain region made of a highly impurity-concentrated semiconductor of a second conductivity type on the opposite side of the active layer; forming a second source region made of a high impurity concentration semiconductor of a first conductivity type; and forming a second source region made of a high impurity concentration semiconductor of a first conductivity type at one end of the active layer and on the opposite side of the second source region. a step of forming two drain regions; and a step of forming the first source region, the first drain region, the second
A first layer is formed on top of the source region and a second drain region, respectively.
A method of manufacturing a semiconductor device, the method comprising at least the step of forming a source-semi electrode, a first drain electrode, a second source electrode, and a second drain electrode.