GB2066571A - Junction field effect transistor - Google Patents

Junction field effect transistor Download PDF

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Publication number
GB2066571A
GB2066571A GB8040887A GB8040887A GB2066571A GB 2066571 A GB2066571 A GB 2066571A GB 8040887 A GB8040887 A GB 8040887A GB 8040887 A GB8040887 A GB 8040887A GB 2066571 A GB2066571 A GB 2066571A
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United Kingdom
Prior art keywords
gate region
region
field effect
effect transistor
junction field
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GB8040887A
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Koninklijke Philips NV
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Philips Gloeilampenfabrieken NV
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Publication of GB2066571A publication Critical patent/GB2066571A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/80Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
    • H01L29/808Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066Gate region of field-effect devices with PN junction gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831Field effect transistors with field effect produced by an insulated gate with multiple gate structure
    • H01L29/7832Field effect transistors with field effect produced by an insulated gate with multiple gate structure the structure comprising a MOS gate and at least one non-MOS gate, e.g. JFET or MESFET gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

A junction field effect transistor formed in a semiconductor body has source and drain regions (12, 13) of one conductivity type with a channel region (15) of the same conductivity type extending therebetween. The upper gate region (14) is electrically connected to the lower gate region (10) by zones of the opposite conductivity type in the semiconductor body and also by a conductive layer (141) on the semiconductor body above the region (15). The conductive layer (141), which may be insulated from or in electrical contact with the region (14), allows better control of the channel region and improves the frequency response of the transistor. <IMAGE>

Description

SPECIFICATIONZ Junction field effect transistors and their manufacture The present invention relates to a junction field effect transistor comprising a semiconductor body which has a surface layer of a first conductivity type, in which surface layer are present surface-adjoining source and drain regions of a second conductivity type opposite to the first, which regions are connected together by a low-doped channel region of the second conductivity type, wherein the semiconductor body comprises between the source and drain regions a first gate region of the first conductivity type adjoining the surface of the semiconductor body, which first gate region, at least at the area of the channel region, form a p-n junction therewith, the first gate region being connected electrically to a part of the surface layer which forms a second gate region of the field effect transistor.
The invention further relates to a method of manufacturing such a transistor.
The expression "low-doped" applies in the case of a concentration lower than 5 x 1 017 atoms per cm3. Usually higher dopant concentrations are used for the source and drain regions.
The invention relates particularly, but not exclusively, to very sensitive field-effect transistors which have low threshold voltages and which operate at low supply voltages and, for example, are used as input elements of amplifiers having a low noise level, for example, input amplifiers of radio receivers.
Experience teaches that such very sensitive transistors, at least as far as the channel and gate regions are concerned, can be manufactured only by means of ion implantation. In order to obtain a good sensitivity it is in fact necessary for the said gate and channel regions to have a very small thickness. In practice it is impossible to achieve such thicknesses in a reproducible manner other than by ion implantation.
A junction field effect transistor having the features mentioned in the opening paragraph is disclosed in U.K. Patent GB 1,281,363. In this case the first gate region is connected to a part of the surface layer which forms a second gate region of the field effect transistor. In order to realize the connection between the two gate regions, the first gate region extends beyond the channel region where it is connected to the second gate region by a highly doped connection zone.
In such a transistor the input resistance of the first gate region is a problem. This region is very thin (thickness in the order of 0.2 micrometre). Consequently the ohmic resistance between a point of the first gate region and the connection zone is high and it increases with the distance relative to the said connection zone. Hence the voltage between the first gate region and the channel region is not uniform across the gate region at a given gate voltage. In addition, a high input resistance causes a high charge and discharge time constant for the gate which restricts the use of the transistor at high frequencies, while the nature of the conductivity, due to majority charge carriers, should make high operating frequencies possible.
In the above-mentioned U.K. Patent GB,1,281,363 these disadvantages are mitigated by providing a number of regularly divided "deep contact zones" between the first gate region and the underlying part of the semiconductor layer which forms the second gate region and which is provided with a metal gate contact.
However, such a device has a smaller active cross-section of the channel region without the first gate region having an equal influence througout its surface at all points of the channel region.
The invention provides an improved structure of a junction field effect transistor having the features mentioned in the opening paragraph, in which these disadvantages are mitigated.
According to a first aspect of the present invention a junction field effect transistor comprising a semiconductor body which has a surface layer of a first conductivity type, in which surface layer are present surface-adjoining source and drain regions of a second conductivity type opposite to the first, which regions are connected together by a low-doped channel region of the second conductivity type, wherein the semiconductor body comprises between the source and drain regions a first gate region of the first conductivity type adjoining the surface of the semiconductor body, which first gate region, at least at the area of the channel region, forms a p-n junction therewith, the first gate region being connected electrically to a part of the surface layer which forms a second gate region of the field effect transistor, is characterized in that the first gate region extends at least up to the source and drain regions and covers the channel region entirely, and in that a conductive layer is present on the semiconductor body, which conductive layer extends at least above the channel region and contacts the surface layer.
The conductive layer on the semiconductor body provides a second control possibility for the first gate region and hence for the junction between said region and the channel region. This allows a better distribution of the electric control of the channel region so that, in particular, the frequency response of the transistor can be improved.
In once particular device in accordance with the invention a large capacitor is formed between the conductive layer and the first gate region as they are mutually separated by a thin insulating layer. The reactance of this capacitor decreases as the frequency of the signal which is applied to the gate region increases. Above a given frequency substantially only the voltage which, via the extra control possibility formed by the conductive layer and the capacitor connected thereto, is applied to the junction between the first gate region and the channel region becomes active to an increasing extent.
At high frequencies the voltage transmitted to said junction via the ohmic input path, that is to say only via the first gate region itself, tends to zero. The parts of the gate region which are farthest remote from the contact zone of the gate region are the first to become inoperative.
The conductive layer which extends above the overall surface of the first gate region transmits a provided gate voltage uniformly to this region and to the gate-channel junction and thus compensates for the loss of sensitivity as a result of the resistance of said region. Due to the extent of the conductive layer and the associated capacitor it is possible to increase the value of the cut-off frequency of the transistor with respect to the cut-off frequency of a junction field effect transistor in the absence of such a conductive layer.
It is to be noted, however, that the capacitor between the conductive layer and the first gate region is connected in series with the capacitor of the junction between the first gate region and the channel region so that the ratio between the voltage which is present across said junction and the input voltage which is applied to the first gate region is attenuated.
In another embodiment of the invention, the conductive layer is provided in direct contact, at least locally, with the first gate region.
In order that the electrical connection between the conductive layer and the first gate region has a sufficient ohmic quality, the first gate region is highly doped, e.g. to a level of 1018 atoms/cm3 or more, at least at its surface. It has been found that a doping concentration of 5 x 1018 atoms/cm3 in n-type silicon, when the connection is obtained, in accordance with a second aspect of the invention, by deposition of an alloy of 99% aluminium and 1% silicon and curing at a temperature of at least approximately 4200C or higher for 10 to 1 5 minutes, gives good results. Such a doping concentration can be achieved by implantation of phosphorus ions. At the temperature of 4200C the first gate region experiences substantially no damage, even when this region is very shallow.
The connection obtained in these conditions is not strictly ohmic (to achieve this, as is known, the doping concentration would have to be 3 to 4 x 1019 atoms/cm3). Instead it has a weak impedance compared with the lateral resistance of the first gate region. The contact thus formed between the conductive layer and the first gate region can be described as a degenerate "Schottky contact". In use this type of contact is found to be particularly suitable, especially in the case of a double implanted junction field effect transistor.
Because the conductive layer is in direct contact with the first gate region the above-mentioned attenuation is substantially avoided.
The conductive layer, preferably contacts the first gate region substantially over its whole surface.
As a result of this, the operation of all parts of the first gate region becomes substantially uniform and this region obtains a maximum efficacy.
Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which Figure 1 is a plan view of a part of a junction field effect transistor in accordance with the invention.
Figure 2 is a cross-sectional view taken on the line Il-Il of Figure 1, Figure 3 is a cross-sectional view taken on the line Ill-Ill of Figure 1, Figure 4 is a cross-sectional view of another junction field effect transistor in accordance with the invention, and Figure 5 is an equivalent circuit diagram of the transistor shown in Figure 4.
The Figures are diagrammatic and, for the sake of clarity, they are not drawn to scale.
Semiconductor components of the same conductivity type are generally shaded in the same direction.
Figure 1 is a plan view and Figures 2 and 3 are cross sectional views taken on the lines Il-Il and Ill-Ill respectively of Figure 1 of a junction field effect transistor in accordance with the invention. The geometry thereof is of a known interdigital type. For clarity, the same reference numeral is used for each of the sub-regions which form a given region of said transistor.
The transistor is formed in a surface layer 10 of a first conductivity type provided on a substrate 1 1 of the second opposite conductivity type. The substrate 1 1 and the layer 10 constitute a part of a semiconductor body in which other cirucit elements may also be formed, for example, other transistors such as those in accordance with the invention and/or bipolar transistors. The assembly of these circuit elements constitutes an integrated circuit.
In the relevant transistor the following features can be distinguished: - A surface-adjoining source region 12 of the second conductivity type which is highly doped. A contact metallisation 121 is connected electrically to the region 12 through an insulating layer 20.
- A surface-adjoining drain region 13 is separated from the source region 12 but is also of the second conductivity type and highly doped. The drain region is connected electrically to a second contact metallization 131.
- A surface-adjoinig first gate region 14 of the first conductivity type is situated between the source and drain regions and extends up to these regions. In the embodiment shown (see Figures 1 and 3) rectangular areas defining the region 14 extend, in the longitudinal direction, into two semiconductor zones 1 6A and 1 6B which are of the first conductivity type and which are highly doped. The zones 1 6A, 1 6B are provided symmetrically, one on each side of the regions 12 and 13 to form an electric connection between the first gate region 14 and the said layer 10 of which parts 1 OA constitute a second gate region. A conductive layer 141 which contacts the layer 10 via the zones 16A and 16B extends above the region 14.
- A channel region 15 of the second conductivity type which is low-doped and is provided below the third surface region 14 and which also extends up to the source and drain regions 12 and 13.
In accordance with the invention, the conductive layer 141 extends at least above the channel region 15.
The semiconductor layer 141 preferably is in direct contact with the first gate region 14, at least locally. In the embodiment of Figures 1, 2 and 3 this contact is provided over the whole surface of the region 14.
In a transistor in accordance with the invention, as shown in the Figures, there atre two signal paths to the first gate region 14. A first path comprises the region 14 itself and conducts the signals from the zones 1 6A, 1 6B into the active part of the said surface region 14 situated between the regions 12 and 13. This path has an electrical resistance as the region 14 has a very small thickness.
Furthermore, the resistance differs from place to place in the region 14 as a result of differences in distance between these places relative to the zones 16A and 16B. The central part of the region 14 is least favourable in this respect in ths case of the transistor described.
A second signal path to the active part of the region 14 is provided by the conductive layer 141 which in this example directly contacts the active region. This second path has considerably less resistance than the first. Since this covers the overall surface of the active region, the embodiment shown has the advantage of enabling a more uniform control of the whole region 14 and the channel region 15.
The manufacture of a transistor in accordance with the invention can be included without special difficulties in the manufacture of an integrated circuit which also comprises other semiconductor elements. This manufacture is preferably carried out as follows.
In a first step the source and drain regions (12 and 13, respectively) are simultaneously formed by diffusion, either during a special process step or during the formation of a semiconductor region for another circuit element of the integrated circuit. The zones 1 6A and 1 68 are then formed, also by diffusion, for example, simultaneously with the bipolar transistor emitter regions of other circuit elements of the integrated circuit. The regions 1 5 and 14 are then formed by ion implantation (as is known, during processing an integrated circuit, implantation steps generally succeed the diffusion steps), preferably in this sequence. The apertures of the implantation masks are provided so that the implanted ions overlap the regions 12 and 13 and also the zone 16. This is to avoid discontinuities.The regions 12 and 13 and the zone 16 are highly doped and there is no risk of influencing their conductivity by this implantation. The annealing conditions after the implantation are dependent on the implantation.
The annealing treatment often takes place in a nitrogen and/or oxygen atmosphere at a temperature of approximately 850#9000C. After the annealing treatment the manufacture of the transistor, as well as that of the integrated circuit, is completed by the deposition of a metallization layer for contact surfaces and connections strips.
By way of practical example, a few physical characteristics and dimensions are given hereinafter which relate to a transistor in accordance with the invention for an integrated circuit as well as the conditions relevant to the manufacture thereof.
The substrate 11 is of the p-type and low doped. The resistance thereof is in the order of 10 Ohm.cm, The layer 10 of the n-type is obtained by epitaxy. The impurity concentration thereof is in the order of 1015 atoms/cm3 and the thickness thereof is 1 5 to 20 micrometess.
The source and drain regions 12 and 13 of the p-type which are obtained by diffusion of boron show a high impurity concentration of approximately 1018 atoms/cm3 at the surface. The thickness of these regions is 2 to 3 micrometers.
The zones 1 6A and 1 6B of the n-type which are obtained by phosphorus diffusion have an impurity concentration of 3 to 4 x 1019 atoms /cm3 at the surface; the thickness thereof is between 0.5 and 1 micrometre.
The channel region 1 5 of the p-type is formed by implantation of boron ions with an energy of 1 50 keV and in a dose which on an average lies at 1.6 x 1012 atoms/cm2. After the final thermal treatment the average impurity concentration is between 5 x 1014 and 1015 atoms/cm3. This region has a thickness of 0.2 micrometre. The peak concentration lies at a depth of 0.2 micrometre from the surface.
The first gate region 14 of the n-type is formed by implantation of phosphorus ions with an energy of approximately 90 keV in a dose which on an average is at 1014 atoms/cm2. The impurity concentration at the surface is 5 x 1018 atoms/cm3 (1019 before the thermal treatment). This region has a thickness of 0.2 micrometre.
The networks of contact surfaces and connection conductors are made from aluminium (99%) and silicon (1%) cured at 420O in a nitrogen atmosphere, the curing treatment lasting from 10 to 15 minutes.
At this temperature a satisfactory ohmic connection to the p-type silicon of the source and drain regions 12 and 13 and to the n-type silicon of the connection zone 16 is obtained. The contact to the ntype silicon of the first gate region 14, without being strictly ohmic, has a small impedance and enables a uniform control of the whole useful surface of the region 14 in particular due to the large area of contact.
The layer 141 projects approximately 0.2 micrometre onto the insulating layer 20, the lines J, and J2 (Figure 2) denoting the junctions between the first gate region 14 and the source and drain regions 12 and 13, respectively.
Figure 4 shows a modified embodiment of a junction field effect transistor in accordance with the invention in which at the area of the first gate region 14 a thin layer of gate oxide 120, for example 50 nm thick, is provided between the first gate region 14 and the conductive layer 141. The conductive layer 141 in this case is not in direct contact with the active part of the region 14 but is capacitively separated therefrom.
Figure 5 shows diagrammatically an equivalent circuit diagram for the Figure 4 field effect transistor in which the capacitive separation forming part of the above-mentioned second signal path (in Figure 5 referenced 122) is denoted by the capacitor COx. The resistance of the conductive layer 141 which, as a matter of fact, is very small, also forms part of the signal path 122 and is indicated by the equivalent resistor Rc.
The above-mentioned first signal path 121 to the first gate region 14 comprises parts of the region 14 itself and said signal path extends from the zones 1 6A, 168 into the active part of the region 14. This path has a high resistance, in Figure 5 shown diagrammatically by the eqiuvalent resistor Rn.
The capacitor between the gate region 14 and the channel region 15 is indicated in Figure 5 by the capacity Cg.
For comparatively low frequencies the second signal path 122 may substantially be neglected so that for the ratio between the channel voltage Vch and the input voltage Vin it holds that
where w is the frequency and j = At higher frequencies, on the contrary, the first signal path 121 is substantially negligible, so that
and as Rc RnRn it holds that
From this it appears that this embodiment of the invention also provides improved control at high frequencies.

Claims (8)

1. A junction field effect transistor comprising a semiconductor body which has a surface layer of a first conductivity type, in which surface layer are present surface-adjoining source and drain regions of a second conductivity type opposite to the first, which regions are connected together by a low-doped channel region of the second conductivity type, wherein the semiconductor body comprises between the source and drain regions a first gate region of the first conductivity type adjoining the surface of the semiconductor body, which first gate region, at least at the area of the channel region, forms a p-n junction therewith, the first gate region being connected electrically to a part of the surface layer which forms a second gate region of the field effect transistor, characterized in that the first gate region extends at least up to the source and drain regions and covers the channel region entirely, and in that a conduc#tive layer is present on the semiconductor body, which conductive layer extends at least above the channel region and contacts the surface layer.
2. A junction field effect transistor as claimed in Claim 1, characterized in that the conductive layer directly contacts the first gate region at least locally.
3. A junction field effect transistor as claimed in Claim 2, characterized in that the conductive layer contacts the first gate region substantially over its whole surface.
4. A junction field effect transistor as claimed in any of Claim 1 to 3, characterized in that the first gate region is highly doped at least at the surface of the semiconductor body.
5. A junction field effect transistor as claimed in Claim 4, characterized in that the first gate region and the channel region are ion implanted regions, and in that the first gate region comprises n-type silicon and has a doping concentration at the surface of 5 x 1018 atoms/cm3.
6. A method of manufacturing a junction field effect transistor claimed in Claim 5, wherein the conductive layer is an alloy of 99% aluminium and 1% silicon, characterized in that the electrical connection between said conductive layer and the first gate region is obtained by curing at a temperature of at least approximately 4200C in a nitrogen atmosphere for 10 to 15 minutres.
7. A junction field effect transistor substantially as herein described with reference to Figures 1 to 3 and Figures 4 and 5 of the accompanying drawings.
8. A method of manufacturing a junction field effect transistor substantially as herein described.
GB8040887A 1979-12-26 1980-12-19 Junction field effect transistor Withdrawn GB2066571A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7931682A FR2472838A1 (en) 1979-12-26 1979-12-26 FIELD EFFECT TRANSISTOR OF JUNCTION TYPE AND METHOD FOR MAKING SAME

Publications (1)

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GB2066571A true GB2066571A (en) 1981-07-08

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JP (1) JPS5698878A (en)
DE (1) DE3046855A1 (en)
FR (1) FR2472838A1 (en)
GB (1) GB2066571A (en)
NL (1) NL8006949A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986002203A1 (en) * 1984-10-05 1986-04-10 Analog Devices, Incorporated Low-leakage jfet
WO2006042669A1 (en) * 2004-10-19 2006-04-27 Austriamicrosystems Ag Jfet and production method
WO2008021919A1 (en) * 2006-08-10 2008-02-21 Dsm Solutions, Inc. Jfet with built in back gate in either soi or bulk silicon
US7642617B2 (en) * 2005-09-28 2010-01-05 Agere Systems Inc. Integrated circuit with depletion mode JFET
EP2309534A1 (en) * 2009-10-08 2011-04-13 Intersil Americas Inc. Depleted top gate junction field effect transistor (DTGJFET)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62243369A (en) * 1986-04-15 1987-10-23 Matsushita Electric Ind Co Ltd Manufacture of gaas semiconductor device

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL161621C (en) * 1968-10-16 1980-02-15 Philips Nv SEMICONDUCTOR DEVICE WITH FIELD EFFECT TRANSISTOR.
DE2630079A1 (en) * 1976-07-03 1978-01-05 Licentia Gmbh BARRIER LAYER EFFECT TRANSISTOR
JPS5365078A (en) * 1976-11-24 1978-06-10 Toshiba Corp Production of junction type field effect transistor
DE2702282A1 (en) * 1977-01-20 1978-07-27 Siemens Ag Contacts and/or conductor paths made on semiconductors - where substrate is alternately exposed to vapour from two evaporators

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1986002203A1 (en) * 1984-10-05 1986-04-10 Analog Devices, Incorporated Low-leakage jfet
WO2006042669A1 (en) * 2004-10-19 2006-04-27 Austriamicrosystems Ag Jfet and production method
US7642617B2 (en) * 2005-09-28 2010-01-05 Agere Systems Inc. Integrated circuit with depletion mode JFET
WO2008021919A1 (en) * 2006-08-10 2008-02-21 Dsm Solutions, Inc. Jfet with built in back gate in either soi or bulk silicon
US7557393B2 (en) 2006-08-10 2009-07-07 Dsm Solutions, Inc. JFET with built in back gate in either SOI or bulk silicon
US7645654B2 (en) 2006-08-10 2010-01-12 Dsm Solutions, Inc. JFET with built in back gate in either SOI or bulk silicon
EP2309534A1 (en) * 2009-10-08 2011-04-13 Intersil Americas Inc. Depleted top gate junction field effect transistor (DTGJFET)
CN102254951A (en) * 2009-10-08 2011-11-23 英特赛尔美国股份有限公司 Depleted top gate junction field effect transistor (DTGJFET)

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Publication number Publication date
JPS5698878A (en) 1981-08-08
DE3046855A1 (en) 1981-08-27
NL8006949A (en) 1981-07-16
FR2472838A1 (en) 1981-07-03

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