JPH1174504A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacture by which the operating speed and the gain can be improved and the power consumption can be reduced. SOLUTION: A gate electrode 16 is formed on the surface of a semiconductor substrate 11 through a gate oxide film 15. Before or after forming a source and drain area 19, an insulating layer 20 is formed by implanting oxygen, nitrogen, fluorine and the like from the PN junction between the source and drain area 19 and the substrate 11 downward to reduce the junction capacity parasitic to this part and to increase the operating speed. The current loss from the source and drain area 19 toward the substrate 11 is also prevented. In this way, high efficiency and reduction of power consumption is achieved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a device including a MIS transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 6 shows a sectional structure of a semiconductor device in which a conventional MIS transistor is formed. In the surface portion of the semiconductor substrate, a P well 91 is formed in an N channel type MOS transistor formation region, and a P channel type MO transistor is formed.
An N well is formed in the S transistor formation region. A field oxide film 94 is formed in the element isolation region by the LOCOS method, and a gate electrode 96 made of polysilicon or the like is formed on the gate oxide film 95 in the element region.
Are formed.

An impurity diffusion layer 97 having a high resistivity is formed on both surface regions of the surface of the semiconductor substrate 91 immediately below the gate electrode 96 in order to prevent generation of hot carriers and reduce a short channel effect. A side wall 98 is formed around the gate electrode 96. Using the side wall 98 and the gate electrode 96 as a mask, source and drain regions 100 are formed by implanting impurity ions by self-alignment. The source and drain regions 100 are formed to have a high impurity concentration in order to reduce parasitic resistance and prevent junction leakage to the substrate.

Further, silicide films 101 and 99 are formed on the surface of the gate electrode 96 and on the surfaces of the source and drain regions 100, respectively, in order to reduce the parasitic resistance. Further, an interlayer insulating film and a wiring layer (not shown) are formed on the upper surface to form a MOS transistor.

[0005]

However, the conventional semiconductor device having the above structure has the following problems.
In other words, a PN junction exists between the source / drain region and the P well or N well, and a small high-frequency signal flows to the P well or N well via this junction capacitance, and the input / output of the transistor Because the efficiency decreases,
This has led to a decrease in operating speed and gain and an increase in power consumption.

Further, even if the design rule of the MOS transistor is advanced and the junction capacitance is reduced, it is difficult to reduce the current flowing to the semiconductor substrate or the well because the resistivity of the well is low. If the impurity concentration of the well is reduced in order to increase the resistance of the well, latch-up is likely to occur between adjacent wells of different conductivity types.

Further, conventionally, an SOI (Silicon) is used to prevent a current from flowing from the source and drain regions to the semiconductor substrate.
On insulator) substrates have also been proposed. However, this substrate is very expensive, and the upper part is electrically insulated from the bottom surface of the substrate, so that there are problems such as an increase in operating current and easy oscillation.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a semiconductor device capable of improving operating speed and gain and reducing consumption electrodes, and a method of manufacturing the same.

[0009]

According to the present invention, there is provided a semiconductor device comprising:
A gate electrode formed on a surface of a semiconductor substrate of one conductivity type via a gate insulating film, and a source region and a drain formed on both sides of the gate electrode in a surface portion of the semiconductor substrate A MIS transistor including a region and an insulating layer formed at a position deeper than a junction between the source region and the drain region and the semiconductor substrate is provided.

Since the insulating layer is provided at a position deeper than the junction between the source region and the drain region and the semiconductor substrate, the capacity of this portion is reduced and the operating speed is increased.
A current can be suppressed from flowing from the source and drain regions to the semiconductor substrate, and higher efficiency and lower power consumption can be achieved.

Here, it is preferable that the insulating layer is formed in an arc shape surrounding the source region and the drain region by injecting impurities while rotating the semiconductor substrate.

According to a method of manufacturing a semiconductor device of the present invention, a step of forming a gate electrode on a surface of a semiconductor substrate of one conductivity type via a gate insulating film, and a step of forming the gate electrode on a surface portion of the semiconductor substrate. Forming a source region and a drain region in a self-aligned manner to form a source region and a drain region; and injecting impurities into a surface portion of the semiconductor substrate while rotating the semiconductor substrate in a self-aligned manner with the gate electrode. Forming an insulating layer below the source region and the drain region.

Further, a method of manufacturing a semiconductor device according to the present invention
Depositing a gate electrode material on a surface of a semiconductor substrate of one conductivity type via a gate insulating film, further depositing a protective film material on the surface of the deposited gate electrode material; and depositing the gate electrode material. Patterning a protective film material and forming a gate electrode and a protective film, and injecting impurities of a reverse conductivity type into the surface portion of the semiconductor substrate in a self-aligned manner with the gate electrode and the protective film, Forming a region and a drain region, and on a surface portion of the semiconductor substrate,
Implanting impurities while rotating the semiconductor substrate in a self-aligned manner with the gate electrode and the protective film to form an insulating layer below the source region and the drain region.

Alternatively, in the method of manufacturing a semiconductor device according to the present invention, a step of forming a gate electrode on a surface of a semiconductor substrate of one conductivity type via a gate insulating film, and a step of applying a resist over the entire surface to perform patterning Performing a step of forming a resist film covering at least the gate electrode, and a step of injecting impurities of the opposite conductivity type into a surface portion of the semiconductor substrate using the resist film as a mask to form a source region and a drain region; Implanting impurities into the surface portion of the semiconductor substrate while rotating the semiconductor substrate using the resist film as a mask to form an insulating layer below the source region and the drain region.

Here, the impurity implanted to form the insulating layer may be any of oxygen, nitrogen or fluorine.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings.

The semiconductor device according to the first embodiment of the present invention is manufactured through the steps shown in FIG. First, as shown in FIG. 1A, for example, impurity ions are implanted into a surface portion of a P-type semiconductor substrate 11, and a P well 1 is formed in an element region where an N-channel MOS transistor is formed.
2 and an N-well 13 is formed in an element region where a P-channel MOS transistor is to be formed. And LO
The field oxide film 14 is formed between the wells by using the COS method to perform element isolation.

Next, as shown in FIG. 1B, a silicon oxide film 1 is formed on the surface of the semiconductor substrate 11 by a thermal oxidation method.
5 is formed, and a polycrystalline silicon film is formed on the surface by CVD. Thereafter, patterning is performed on the polycrystalline silicon film and the silicon oxide film 15 to form a gate electrode 16.

Next, as shown in FIG. 1C, an impurity region 17 is formed on both surface regions of the surface of the semiconductor substrate 11 immediately below the gate electrode 16. This impurity region 1
Numeral 7 is formed to prevent the generation of hot carriers and to reduce the short channel effect. Since it is necessary to prevent punch-through, it is formed so that the impurity concentration is low and the depth is shallow. For example, when an N-channel MOS transistor is formed in the P well 12, arsenic (As) is implanted as N-type impurity ions at an acceleration voltage of 15 keV and a dose of 2.0 × 10 ¹⁴ 1 / cm ² . When a P-channel MOS transistor is formed in the N-well 13, boron fluoride (BF ₂ ) is used as P-type impurity ions at an acceleration voltage of 15 keV and a dose of 5.0 × 10 ¹³ 1 / cm ^2.
Ion implantation.

Further, for example, a silicon nitride film (Si ₃ N ₄ ) is deposited as an insulating film on the entire surface, and, for example, reactive ion etching is performed as anisotropic etching, and a gate electrode 16 having a width of about 1000 Å is formed around the gate electrode 16. The side wall 18 is formed. Further, a resist film 21 is formed on the field oxide film 14.

Subsequently, using the gate electrode 16, the side wall 18, and the resist film 21 as a mask, impurities are ion-implanted to form source and drain regions 19. N-channel type MO
When an S transistor is formed, arsenic is ion-implanted at an acceleration voltage of 50 keV and a dose of 5 × 10 ¹⁵ 1 / cm ² , for example, when a P-channel MOS transistor is formed, boron fluoride is accelerated at an acceleration voltage of 30 keV. Ion implantation is performed at a dose of 3 × 10 ¹⁵ 1 / cm ² .

After or before the formation of the source / drain regions 19, the P
The insulating layer 20 is formed below the N junction. When the insulating layer 20 is formed, the acceleration voltage is applied to the source / drain region 1 at an angle larger than the angle of the field edge and not so as to contact the impurity diffusion layer 17.
Oxygen is ion-implanted while the semiconductor substrate 11 is set to be deeper than the PN junction between the semiconductor substrate 9 and the semiconductor substrate 11, preferably while the semiconductor substrate 11 is rotated in the direction of arrow A. For example,
The ion implantation angle may be 30 degrees as indicated by arrow B, and the rotation speed may be 60 rotations per minute. Note that, similarly to the normal ion implantation, the ion implantation may be performed at an implantation angle of about 0 degree without rotating. After the ion implantation, the impurities are activated by, for example, performing a rapid thermal annealing process at 1000 degrees Celsius for 20 seconds.

The acceleration voltage at the time of injecting oxygen is
For example, the dose may be 250 keV and the dose may be 1 × 10 ¹⁵ 1 / cm ² . Here, the ion implantation conditions may be changed according to the impurities in the source / drain regions 19. For example, when the source and drain regions 19 are formed of arsenic, the acceleration voltage is not less than 4.7 times the acceleration voltage when arsenic is implanted.
In the case of using boron fluoride, the insulating layer 20 can be formed below the source / drain region 19 by setting the acceleration voltage to 3.4 times or more when boron fluoride is implanted. .

Next, as shown in FIG.
The insulating layer on the surface of the gate electrode and the silicon oxide film as the insulating layer on the surface of the source / drain region 19, which are generated by ion implantation for forming 0, are removed by dilute hydrofluoric acid treatment.

Further, as shown in FIG. 1E, a salicide treatment is performed on the surface portions of the gate electrode 16 and the source / drain regions 19 to form a metal such as cobalt (Co), nickel (Ni), and titanium (Ti). And silicon are formed to form silicide films 23 and 22.

Thereafter, although not shown, a silicon oxide film is deposited by a CVD method to form an interlayer insulating film, and a contact hole is opened. On the surface, for example, aluminum-silicon-copper (AlSiCu) or aluminum-copper (AlCu) is deposited by sputtering and patterned to form a wiring layer. Further, when a multilayer wiring structure is adopted, an interlayer insulating film and second and third wiring layers are formed as necessary.

According to the present embodiment, the insulating layer 20 in which silicon and oxygen are bonded is formed at a position deeper than the PN junction between the source / drain region 19 and the semiconductor substrate 11, so that the following Such effects can be obtained.

Semiconductor substrate 11 and source / drain region 1
9, there is a junction capacitance due to the presence of the PN junction, which causes a reduction in operating speed. But,
In the first embodiment, since the insulating layer 20 is further formed below the joint portion, the joint capacitance of the entire portion is reduced, and the operation speed is improved and the high-frequency characteristics are improved.

Further, the presence of the insulating layer 20 between the source / drain region 19 and the semiconductor substrate 11 increases the resistance between the element and the substrate, thereby preventing a high frequency signal from flowing to the substrate. Yes, the gain is improved.

Next, a second embodiment of the present invention will be described with reference to FIG. This embodiment is characterized in that a protective film is formed over a gate electrode to suppress a decrease in conductivity when ion implantation is performed to form an insulating layer below a source and drain region.

First, as shown in FIG. 2A, for example, impurity ions are implanted into the surface of a P-type semiconductor substrate 31 to form a P-well 32 and an N-well 33. A field oxide film 34 is formed in the element isolation region to perform element isolation.

Next, as shown in FIG. 2B, a silicon oxide film 35 and a polycrystalline silicon film are formed in the same manner as in the first embodiment. Further, a silicon oxide film (Si) is formed on the surface of the polycrystalline silicon film as a protective film.
O ₂ ), tungsten silicide film (WSi ₂ ), molybdenum silicide film (MoSi), silicon nitride film (S
iN), a metal film, a titanium silicide film (TiSi ₂ ) film, and the like. Then, the silicon oxide film 35, the polycrystalline silicon film, and the protective film are patterned into the shape of the gate electrode, and the gate electrode 36 made of polycrystalline silicon is formed.
Then, a protective film 44 for protecting the gate electrode 36 is formed.

Next, as shown in FIG. 2C, the impurity region 3 having a low impurity concentration and a shallow depth is provided at both end regions immediately below the gate electrode 36 on the surface of the semiconductor substrate 31.
7 is formed.

Further, for example, a silicon nitride film (Si ₃ N ₄ ) is deposited as an insulating film on the entire surface, and reactive ion etching is performed as anisotropic etching to form a side wall 38 around the gate electrode 36. A resist film 41 is formed outside the element region.

Subsequently, impurities are ion-implanted using the gate electrode 36, the side wall 38 and the resist film 41 as a mask.
Source and drain regions 39 are formed. N-channel type M
When forming an OS transistor, for example, arsenic is ion-implanted at an acceleration voltage of 50 keV and a dose of 5 × 10 ¹⁵ 1 / cm ² , and when a P-channel MOS transistor is formed, for example, boron fluoride is accelerated at an acceleration voltage of 30 keV. Ion implantation is performed at a dose of 3 × 10 ¹⁵ 1 / cm ² .

After or before the formation of the source / drain regions 39, the P
The insulating layer 40 is formed below the N junction. When the insulating layer 40 is formed, the acceleration voltage is applied to the source / drain regions 3 in a state where the angle is larger than the angle of the field edge and is set so as not to contact the impurity diffusion layer 37.
As described in the first embodiment, the depth is set to be deeper than the PN junction between the semiconductor substrate 31 and the semiconductor substrate 31, and ion implantation of oxygen is performed with or without rotating the semiconductor substrate 31. I do. The acceleration voltage and the dose in this ion implantation may be set in the same manner as in the first embodiment. After the ion implantation, the impurities are activated by, for example, performing a rapid thermal annealing process at 1000 degrees Celsius for 20 seconds.

Next, as shown in FIG. 2D, the silicon oxide film as an insulating layer on the surface of the source / drain region 39 generated by ion implantation for forming the insulating layer 40 is subjected to a dilute hydrofluoric acid treatment. Remove.

The protective film 37 is also removed by wet processing, for example, in the case of a silicon oxide film, by dilute hydrofluoric acid processing.

Further, as shown in FIG. 2E, a salicide treatment is performed on the surface portions of the gate electrode 36 and the source / drain regions 39, and cobalt (Co), nickel (N
i), a metal such as titanium (Ti) and silicon are combined to form silicide films 43 and 42.

Thereafter, although not shown, a silicon oxide film is deposited by a CVD method to form an interlayer insulating film, and a contact hole is opened. On the surface, for example, aluminum-silicon-copper (AlSiCu) or aluminum-copper (AlCu) is deposited by sputtering and patterned to form a wiring layer. Further, when a multilayer wiring structure is adopted, an interlayer insulating film and second and third wiring layers are formed as necessary.

The manufacturing method according to the third embodiment of the present invention includes steps as shown in FIG. The second
In this embodiment, a protective film is formed on the gate electrode when performing ion implantation to form an insulating layer below the source and drain regions. However, in this embodiment, a resist film is formed instead of the protective film. In that the conductivity of the gate electrode is prevented from lowering.

First, as shown in FIG. 3A, impurity ions are implanted into the surface of the P-type
A well 52 and an N well 53 are formed. A field oxide film 54 is formed in an element isolation region to perform element isolation.

Next, as shown in FIG. 3B, a silicon oxide film 55 and a polycrystalline silicon film are formed on the surface of the semiconductor substrate 51. The silicon oxide film 55 and the polycrystalline silicon film are patterned into the shape of a gate electrode to form a gate electrode 56 made of polycrystalline silicon.

Subsequently, as shown in FIG. 3C, an impurity region 57 having a low impurity concentration and a small depth is formed in both end regions immediately below the gate electrode 56 on the surface of the semiconductor substrate 51. Next, for example, a silicon nitride film (Si ₃ N ₄ ) is deposited as an insulating film on the entire surface, and reactive ion etching is performed as anisotropic etching to form the gate electrode 5
A sidewall 58 having a width of, for example, about 1000 angstroms is formed around the periphery of 6. Further, a resist is applied to the entire surface and patterned to form a resist film 61 covering the gate electrode 56 and the side wall 58 and a resist film 62 covering the outside of the element region.

The resist films 61 and 62 and the side walls 58
Is used as a mask to ion-implant impurities to form source / drain regions 59. The acceleration voltage and the dose in the case of forming an N-channel type MOS transistor or the case of forming a P-channel type MOS transistor may be the same as those in the first and second embodiments.

After or before the formation of the source / drain regions 59, the P
The insulating layer 60 is formed below the N junction. The conditions for forming the insulating layer 60 may be set in the same manner as in the first and second embodiments. Thereafter, as shown in FIG. 3D, after the resist films 61 and 62 are peeled off, a thermal annealing process is performed to activate the implanted impurities.

Further, as shown in FIG. 3E, a salicide treatment is performed on the surface portions of the gate electrode 56 and the source / drain regions 59, and cobalt (Co), nickel (N)
i), a metal such as titanium (Ti) and silicon are combined to form silicide films 63 and 64. Thereafter, an interlayer insulating film and a wiring layer (not shown) are formed.

In the first to third embodiments,
In any case, the insulating layers 20, 40, and 60 are used as the P and P regions between the source and drain regions 19, 39, and 59 and the substrates 11, 31, and 51.
It is formed at a position deeper than the N junction. In contrast,
Even if the insulating layer 80 is formed at substantially the same depth as the junction between the source / drain region 79 and the semiconductor substrate 71 as in the cross-sectional structure shown in FIG. An increase in resistance between the substrate and the substrate can be expected. However, compared to such a structure, the structures according to the first to third embodiments have a larger junction portion between the source / drain region and the substrate, so that the junction capacitance is further reduced. Therefore, when the insulating layer is formed deeper than the junction between the source / drain region and the substrate as in the present invention, the operation speed and the efficiency can be effectively improved.

FIG. 5 shows a configuration of a general equivalent circuit of a small signal in a MOS transistor. When a gate voltage is input to the gate electrode via the resistance Rg of the gate electrode and the capacitance Cgs between the gate and the source, the resistance value Rch + Rs +
In addition to the original signal path having Rd, the capacitance Cj at the junction between the source / drain region and the substrate, and the resistance Rds present between the source / drain region and the substrate
A signal current also flows between. According to the first to third embodiments, the junction capacitance Cj is reduced and the substrate resistance Rds is increased by the presence of the insulating layer.
Higher gain and lower power consumption can both be realized.

Further, when forming the insulating layer, oxygen is injected while rotating the semiconductor substrate, so that the insulating layer 20 is formed.
40 and 60 are formed in an arc shape as shown in FIGS. Therefore, not only the capacitance in the central region of the source and drain regions but also the capacitance in the peripheral portion of the gate electrode and the peripheral portion of the field oxide film can be reduced.

When the acceleration voltage is relatively low, the first
Even if a protective film or the like is not formed as in the above embodiment, the insulating film formed by the implantation of oxygen can be replaced with ammonium fluoride (N
It can be removed by etching using H ₄ F). However, when the acceleration voltage is set high, oxygen may enter the inside of the gate electrode and increase the resistance of the gate electrode. In such a case, an increase in resistance can be prevented by injecting oxygen with the upper part of the gate electrode covered with a protective film or a resist film as in the second and third embodiments.

Further, the above-described embodiments are merely examples, and do not limit the present invention. For example, in the above embodiment, the insulating layer located below the PN junction between the source and drain regions and the semiconductor substrate is formed by injecting oxygen. However, not only oxygen but also other elements such as fluorine (F ₂ ) and nitrogen (N ₂ ) may be implanted as long as they can form a layer having an insulating property by being combined with silicon. Further, the insulating layer does not need to be formed deeply over the entire periphery than the PN junction between the source / drain region and the substrate, and may be formed so as to have a part of which is in contact.

[0053]

As described above, according to the present invention,
By forming the insulating layer at a position deeper than the PN junction between the source / drain region and the substrate, the parasitic capacitance between the source / drain region and the substrate is reduced, and the substrate is connected via the junction capacitance. Since the loss of current flowing to the power supply can be reduced, it is possible to contribute to speeding up of operation, improvement of gain, and reduction of power consumption.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a cross-sectional structure of a semiconductor device according to a first embodiment of the present invention and steps of a method of manufacturing the same.

FIG. 2 is a longitudinal sectional view showing a cross-sectional structure of a semiconductor device according to a second embodiment of the present invention and steps of a method of manufacturing the same.

FIG. 3 is a longitudinal sectional view showing a cross-sectional structure of a semiconductor device according to a third embodiment of the present invention and a process of a method of manufacturing the same.

FIG. 4 is a longitudinal sectional view showing a sectional structure of a semiconductor device in which an insulating layer is formed by a method different from that of the semiconductor device according to the first to third embodiments.

FIG. 5 is a circuit diagram showing a configuration of an equivalent circuit when a small signal is input to a MOS transistor to which the present invention can be applied.

FIG. 6 is a longitudinal sectional view showing a sectional structure of a conventional semiconductor device.

[Explanation of symbols]

 11, 31, 51, 71 Semiconductor substrate 12, 32, 52 P well 13, 33, 53 N well 14, 34, 54, 74 Field oxide film 15, 35, 55, 75 Gate oxide film 16, 36, 56, 76 Gate electrode 17, 37, 57, 79 Diffusion layer 18, 38, 58, 78 Side wall 19, 39, 59, 79 Source, drain region 20, 40, 60 Insulation layer 21, 41, 61, 62 Resist film 22, 23, 42, 43, 63, 64 Silicide film 44 Protective film

Claims (6)

[Claims] A gate electrode formed on a surface of a semiconductor substrate of one conductivity type via a gate insulating film; and a gate electrode formed on both sides of the gate electrode in a surface portion of the semiconductor substrate. A MIS transistor having: a source region and a drain region; and an insulating layer formed at a position deeper than a junction between the source region and the drain region and the semiconductor substrate. 2. The semiconductor device according to claim 1, wherein the insulating layer is formed in an arc shape surrounding the source region and the drain region by implanting impurities while rotating the semiconductor substrate. Semiconductor device. 3. A step of forming a gate electrode on a surface of a semiconductor substrate of one conductivity type via a gate insulating film; Implanting an impurity to form a source region and a drain region; and injecting an impurity into a surface portion of the semiconductor substrate while rotating the semiconductor substrate in a self-aligned manner with the gate electrode; Forming an insulating layer below the semiconductor device. 4. A step of depositing a gate electrode material on a surface of a semiconductor substrate of one conductivity type via a gate insulating film, and depositing a protective film material on the surface of the deposited gate electrode material. Patterning the gate electrode material and the protective film material thus formed to form a gate electrode and a protective film; and, on a surface portion of the semiconductor substrate, an impurity of a reverse conductivity type in a self-aligned manner with the gate electrode and the protective film. Forming a source region and a drain region; and injecting impurities into the surface portion of the semiconductor substrate while rotating the semiconductor substrate in a self-aligned manner with the gate electrode and the protective film. And a step of forming an insulating layer below the drain region. 5. A step of forming a gate electrode on a surface of a semiconductor substrate of one conductivity type with a gate insulating film interposed therebetween, and applying a resist to the entire surface and patterning the resist to cover at least the gate electrode. Forming a source region and a drain region on the surface portion of the semiconductor substrate by injecting impurities of the opposite conductivity type using the resist film as a mask; and forming the resist on the surface portion of the semiconductor substrate. Implanting impurities while rotating the semiconductor substrate using a film as a mask, and forming an insulating layer below the source region and the drain region. 6. The semiconductor device according to claim 3, wherein said impurity implanted for forming said insulating layer is any one of oxygen, nitrogen and fluorine. Production method.