JPH05267678A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To realize high level of integration and high speed operation, by forming a source layer, a channel layer and a drain layer, which are operation regions of an semiconductor element, vertical direction, and constituting the channel layer of material which makes electrons travel at high speed between the source layer and the drain layer. CONSTITUTION:A source layer 21, a channel layer 22 and a drain layer 23 which turn to the operating region of a transistor are formed in order on a semiconductor substrate 20. An N<+> type diffusion layer 24 is formed on the surface layer part of the substrate 20, so as to be in contact with a source layer 21 and stretched in the lateral direction by a necessary amount. The channel layer 22 is composed of SiGe or the like which makes electrons travel at a high speed between the source and the drain. A gate insulating film 25 composed of silicon oxide is formed on the side wall of the channel layer 22. A plurality of gate electrode leading-out parts 26 composed of poly silicon are connected with the channel layer via the gate insulating film 25. A contact hole 27 is formed, and the gate electrode 28 is connected with the gate electrode leading-out part 26.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a vertical MOS structure and a method of manufacturing the same.

[0002]

2. Description of the Related Art In a conventional semiconductor device having a MOS structure (MOS type transistor, etc.), the operating regions of semiconductor elements (transistors) are arranged laterally as shown in FIG. That is, in the surface layer portion of the semiconductor substrate 1, the source region 3 having a high impurity concentration is inserted so as to sandwich the channel region 2 from both sides.
And a drain region 4 is formed. A source electrode 5 is provided on the source region 3 and a drain electrode 6 is provided on the drain region 4. A gate electrode lead-out portion 8 is formed on the channel region 2 with a gate insulating film 7 interposed therebetween, and a gate electrode 9 is provided on the gate electrode lead-out portion 8. In addition, each electrode 5,
The layers 6 and 9 are insulated by the insulating film 10.

Scaling (also referred to as scale-down) is known as a technique for achieving high speed and high integration in the MOS transistor having the above structure. This scaling means, in principle, all device dimensions such as channel length, channel width, junction depth, lateral diffusion distance, and gate insulating film thickness are reduced to 1 / K of the original dimensions to achieve high speed and high integration. It is to correspond.

[0004]

However, since the higher the degree of integration, the finer the processing is required for the scaling, the manufacturing cost is high and the manufacturing cost is high in order to adapt to the so-called submicron level. The process becomes complicated. In particular, in the conventional MOS type transistor, since the operating regions (source, channel, drain) of the transistor are arranged in the lateral direction, self-alignment (self-alignment) is required for high integration.
Even if they are arranged by the t) method, it is difficult to accurately control the dimension between them.

In view of the above, the present invention is based on a completely new viewpoint, has a novel structure, a low manufacturing cost, and a simple manufacturing process, and is suitable for high speed and high integration. And a method for manufacturing the same.

[0006]

In order to achieve the above object, a semiconductor device according to claim 1 of the present invention comprises a semiconductor substrate in which a source layer, a channel layer and a drain layer which are operating regions of a semiconductor element are vertically formed. The channel layer is made of a material that moves electrons at high speed between the source layer and the drain layer, and a gate insulating film is formed on a sidewall of the channel layer.
The gate electrode lead-out portion is formed so as to be connected to the channel layer through the gate insulating film.

A semiconductor device according to a second aspect is the semiconductor device according to the first aspect, wherein a plurality of gate electrode lead-out portions are provided for one channel layer, and a gate electrode is connected to each gate electrode lead-out portion. It is a thing. Claim 3
The semiconductor device according to claim 1 is the semiconductor device according to claim 1,
The gate electrode extraction portion is arranged so as to surround the three side surfaces of the channel layer, and the gate electrode is connected to the gate electrode extraction portion.

A semiconductor device according to a fourth aspect is the semiconductor device according to the first or second aspect, in which a diffusion layer is formed below the source layer in contact with the source layer and extended in the lateral direction as necessary. A source electrode extraction portion is formed on the extended diffusion layer. A method of manufacturing a semiconductor device according to claim 5, wherein a step of forming an insulating film on the semiconductor substrate,
Applying a resist on the insulating film leaving the diffusion layer formation region,
The step of forming a diffusion layer on the surface layer of the semiconductor substrate by diffusing impurities, the step of laterally growing the remaining insulating film after removing the resist, the insulation grown in the above step leaving the source electrode extraction region A step of applying a resist on the film and exposing the diffusion layer by etching, a step of removing the resist and then a step of depositing polysilicon on the insulating film so as to cover the diffusion layer exposed in the step, and an element isolation region The process of applying a resist on the polysilicon remaining, exposing the growth insulating film by etching, and forming the gate electrode extraction part and the source electrode extraction part separately, after removing the resist, exposing it in the above process The step of depositing an insulating film on the gate electrode lead-out portion and the source electrode lead-out portion so as to cover the grown insulating film Step of applying a resist on the edge film and exposing the diffusion layer by etching, removing the resist, and then forming a gate insulating film on the diffusion layer exposed in the above step by thermal oxidation and on the side wall of the etching surface, diffusion A step of exposing the diffusion layer by exposing the diffusion layer by applying a resist on the deposited insulation film and the gate insulation film on the side wall of the etching surface while leaving the gate insulation film on the layer, and removing the gate insulation film on the diffusion layer by etching. On the exposed diffusion layer,
A step of continuously forming a source layer, a channel layer, and a drain layer in the vertical direction while changing the material gas, a step of further depositing an insulating film on the drain layer and the deposited insulating film, and leaving the gate, source, and drain electrode forming regions. And applying a resist on the insulating film deposited in the above step to expose the gate electrode extraction part, the source electrode extraction part and the drain layer by etching, and the gate electrode on the gate electrode extraction part and the source electrode extraction part. Source electrode on top,
The method is characterized by including a step of forming drain electrodes on the drain layer.

[0009]

In the semiconductor device according to the first aspect, since the source layer, the channel layer, and the drain layer which become the operation region of the semiconductor element are vertically formed on the semiconductor substrate, the semiconductor device has a vertical MOS structure. High integration can be achieved without performing scaling considering error as in the conventional case. Then, by thinning the channel layer, the speed can be easily increased. Furthermore, since the channel layer is made of a substance that allows electrons to move at high speed between the source and the drain, further speedup can be realized.

According to another aspect of the semiconductor device of the present invention, the operating region of the semiconductor device is vertical and a plurality of gate electrode lead-out portions are provided for one channel layer. Therefore, a plurality of gates are provided for one semiconductor element. A plurality of electrodes can be provided. Therefore, a logic circuit or the like including a large number of semiconductor elements can be configured with a small number of semiconductor elements. In the semiconductor device according to claim 3, since the gate electrode lead-out portion is arranged so as to surround the three side surfaces of the channel layer and the gate electrode is connected to the gate electrode lead-out portion, the gate voltage can be applied from three directions. Even if the size of the semiconductor element is reduced,
It is possible to suppress the variation in S factor of the semiconductor element and suppress the short channel effect. Therefore, the channel length can be shortened to reduce the size of the transistor, which not only contributes to high integration, but also speeds up the device.

According to another aspect of the semiconductor device of the present invention, the diffusion layer is formed in contact with the source layer so as to extend in the lateral direction as much as necessary, and the source electrode lead-out portion is formed on the extended diffusion layer. If the shape of the operation region of the semiconductor element is a square or more or a circle or the like, the number of gate electrode lead-out portions can be further increased to four or more. Therefore, four or more gate electrodes can be formed for one semiconductor element, and one semiconductor element can form a logic circuit with four or more gates.

In the manufacturing method of the fifth aspect, since the source layer, the channel layer and the drain layer are continuously formed while changing the material gas in the operation region forming step of the semiconductor device, the source-channel-drain is formed by one process. Can be formed, which leads to simplification of the manufacturing process. In addition, since a high temperature treatment is not performed in a step after formation of an operating region of a transistor, a substance which moves electrons at high speed between a source and a drain can be used for a channel layer.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to FIGS. First, the structure of the semiconductor device of this embodiment will be described with reference to FIG. FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention. The semiconductor device of the present embodiment shown in FIG. 1 is a MOS transistor, and a cross section of a transistor having a novel vertical structure is shown on the left side of the figure, and a source electrode for the transistor on the left side is shown on the right side. The ejector is shown.

This vertical type MOS transistor is
As shown in FIG. 1, a source layer 21, a channel layer 22 and a drain layer 23, which are operating regions of a transistor, are sequentially formed in a vertical direction on a semiconductor substrate 20 made of P-type silicon and having a plane orientation (100). On the surface layer of N ⁺
The type diffusion layer 24 is formed in contact with the source layer 21 and extended in the lateral direction (right side in the drawing) as necessary.

The channel layer 23 is formed of a source such as SiGe.
It consists of a substance that allows electrons to move at high speed between drains. A gate insulating film 25 made of silicon oxide is formed on the side wall of the channel layer 23, and a plurality of gate electrode lead-out portions 26 made of polysilicon are formed through the gate insulating film 25.
Are connected. A contact hole 27 is formed on the gate electrode extraction portion 26, and the gate electrode 28 is connected to the gate electrode extraction portion 26 through the contact hole 27. The gate electrode connected to the left gate electrode extraction portion 26 is not shown in the figure.

A contact hole 29 is formed on the drain layer 23, and the drain electrode 30 is connected to the drain layer 23 through the contact hole 29. A source electrode lead-out portion 31 made of polysilicon is formed on the upper right side of the diffusion layer 24. A contact hole 32 is formed on the source electrode extraction portion 31, and the source electrode 33 is connected to the source electrode extraction portion 31 through the contact hole 32.

An insulating film 34A made of silicon oxide is filled and insulated between the semiconductor substrate 20 and the electrode lead-out portions 26, 31, and silicon oxide is provided between the electrodes 27, 30, 33. Insulating films 34B and 34C are filled and insulated. In the above configuration,
Since the source layer 21, the channel layer 22, and the drain layer 23, which are the operating regions of the transistor, are formed in the vertical direction on the semiconductor substrate 20 to form a vertical MOS structure transistor, an error is generated like a conventional MOS transistor. High integration can be achieved without taking into consideration scaling. Then, by thinning the channel layer 22, the speed can be easily increased. Furthermore, since the channel layer 22 is made of a material such as SiGe that moves electrons at high speed between the source and the drain, further speedup can be realized.

Further, by vertically forming the operation region of the transistor, it becomes possible to connect a plurality of gate electrode lead-out portions 26 to one channel layer 22 through the gate insulating film 25. A plurality of gate electrodes 28 can be provided for the transistor. Therefore, a logic circuit or the like using a large number of transistors can be formed with a small number of transistors.

Further, as shown in FIG. 7, when the gate electrode lead-out portion 26 is arranged so as to surround the three side surfaces of the channel layer 22 and the gate electrode 28 is connected to the gate electrode lead-out portion 26, the gate voltage is 3 Since it can be applied from the other side, even if the size of the transistor is reduced, it is possible to suppress the variation in the S factor of the transistor and suppress the short channel effect. Therefore, the channel length can be shortened to reduce the size of the transistor, which not only contributes to high integration, but also speeds up the device.

Furthermore, since the diffusion layer 24 is formed in contact with the source layer 21 so as to extend laterally as much as necessary, and the source electrode extraction portion 31 is formed on the extended diffusion layer 24, As shown in FIG. 8, four gate electrode extraction portions 26 can be formed for one transistor, and a four-gate logic circuit can be constructed. Further, the number of gates can be further increased by making the operating region of the transistor polygonal, circular, or the like.

Next, a method of manufacturing the above semiconductor device will be described with reference to FIGS. 2 to 6 are sectional views showing a method of manufacturing a semiconductor device in the order of steps. First, as shown in FIG. 2A, an insulating film 34A made of silicon oxide is formed on the semiconductor substrate 20 made of P-type silicon and having a plane orientation (100) by thermal oxidation. At this time, the oxidation temperature is, for example, 900 ° C., and the oxidation time is, for example, 30.
If so, the thickness of the insulating film 34A becomes 1000 Å.

Then, as shown in FIG. 2B, a diffusion layer is formed.
A resist 36 is applied on the insulating film 34A leaving a region,
For example, with an injection energy of 50 keV, As⁺(3 x 10¹⁵
cm ^-2) Is injected and diffused to form a surface layer portion of the semiconductor substrate 20.
In addition, the wiring to the adjacent transistor and the extraction of the electrode
To do N⁺Extend the mold diffusion layer 24 laterally as needed
Form.

Next, as shown in FIG. 2C, the resist 36
Then, the insulating film 34A is vertically grown by thermal oxidation. If the oxidation temperature at this time is 900 ° C. and the oxidation time is 30 minutes, for example, the insulating film 34A grows, and as a result, its thickness becomes 2000 Å. After that, Figure 2
As shown in (d), after applying the resist 37 on the insulating film 34A, the insulating film 34A in the source electrode extraction region portion is formed by HF.
To expose the diffusion layer 24.

Then, as shown in FIG. 3A, after removing the resist 37, CVD (Chemical Vap) is performed.
or deposition method to cover the diffusion layer 24 exposed in the step of FIG. 2D so as to cover the insulating film 34A.
Deposit N ⁺ polysilicon 38 on top. At this time, if SiH ₄ + PH ₃ is used as the reaction gas, the vapor growth temperature is 650 ° C., and the vapor growth time is 15 minutes, for example,
The deposited thickness of the polysilicon 38 is 4000 Å.

Then, as shown in FIG. 3B, a resist 39 is coated on the polysilicon 38 leaving the element isolation region, and RIE (Reactive) is performed by using a reaction gas CH _4.
e Ion Etching)
By exposing A, the gate electrode extraction portion 26 and the source electrode extraction portion 31 are formed separately. Next, as shown in FIG. 3C, after removing the resist 39, oxidation is performed on the gate electrode extraction portion 26 and the source electrode extraction portion 31 by the CVD method so as to cover the insulating film 34A exposed in the previous step. An insulating film 34B made of silicon is deposited. At this time, if SiH ₄ + O ₂ is used as the reaction gas, the vapor growth temperature is, for example, 450 ° C., and the vapor growth time is, for example, 5 minutes, the deposition thickness of the insulating film 34B is 5000 Å.

Thereafter, as shown in FIG. 4A, a resist 40 is applied on the insulating film 34B leaving the transistor operation region, and the diffusion layer 24 is exposed by RIE. After that, as shown in FIG. 4B, after removing the resist 40,
The insulating films 34A and 34B are grown by thermal oxidation, and as shown in FIG.
A gate insulating film 25 made of silicon oxide is formed on the diffusion layer 24 exposed in the step (a) and on the side wall of the etching surface. If the oxidation temperature at this time is 900 ° C. and the oxidation time is 5 minutes, for example, the thickness of the gate insulating film 25 is 2
It becomes 50Å.

Then, as shown in FIG. 4C, the diffusion layer 24
A resist 41 is applied on the insulating film 34B and the gate insulating film 25 on the side wall of the etching surface while leaving the upper gate insulating film 25, and the gate insulating film 25 on the diffusion layer 24 is removed by etching with HF to expose the diffusion layer 24. Let Next, FIG.
As shown in FIG. 4A, a gas lease MBE (Molecular B) is formed on the diffusion layer 24 exposed in the step of FIG.
The source layer 21, the channel layer 22 and the drain layer 23 are continuously formed in the vertical direction by changing the material gas by the electron epitaxy. That is, when the source-channel-drain has an NPN structure, PH ₃ ,
When the source gas is changed to B ₂ H ₆ and PH ₃ in this order and the source-channel-drain has a PNP structure, B
_The material gas is changed in the order of ₂ H ₆ , PH ₃ , and B ₂ H ₆ . At this time, in order to increase the moving speed of the electrons moving between the source and the drain, for example, GeH ₄ is introduced at the time of forming the channel to make the channel layer 22 a SiGe layer. Then, thermal oxidation is performed in order to prevent non-contact between the gate oxide film 25 and the channel layer 22, and the gate oxide film 25 and the channel layer 22 are evenly bonded. The oxidation temperature at this time is, for example, 80
The temperature is 0 ° C. and the oxidation time is 10 minutes, for example.

Thereafter, as shown in FIG. 5B, an insulating film 34C made of silicon oxide is further deposited on the drain layer 23 and the insulating film 34B by the CVD method. At this time, if SiH ₄ + O ₂ is used as the reaction gas, the vapor growth temperature is, for example, 450 ° C., and the vapor growth time is, for example, 5 minutes, the insulating film 34C has a film thickness of 5000 Å. Then, as shown in FIG. 5C, a resist 42 is applied on the insulating film 34C leaving the gate, source, and drain electrode forming regions, and the contact holes 27, 29, 32 are formed by RIE.
To form a gate electrode extraction portion 26 and a source electrode extraction portion 3
1 and the drain layer 23 are exposed.

Then, as shown in FIG.
After removing 2, the conductive thin film 43 such as aluminum is deposited on the insulating film 35C by sputtering so as to fill the contact holes 27, 29, 32. The film thickness of the conductive thin film 43 is, for example, 1000Å. Finally, Figure 6
As shown in (b), by patterning the conductive thin film 43,
A gate electrode 28 is provided on the gate electrode extraction portion 26, a source electrode 33 is provided on the source electrode extraction portion 31, and a drain electrode 30 is provided on the drain layer 23.

As described above, since the source layer 21, the channel layer 22 and the drain layer 23 are continuously formed while changing the material gas in the operation region forming step of the transistor of FIG. 5A, the source-channel-drain is formed. Can be formed in a single process, which leads to simplification of the manufacturing process. In addition, since high temperature treatment is not performed in a step after formation of the operating region of the transistor, a substance such as SiGe that moves electrons at high speed between the source and the drain can be used for the channel layer 22.

The present invention is not limited to the above embodiment, and it goes without saying that many modifications and changes can be made within the scope of the present invention.

[0032]

As is apparent from the above description, according to the semiconductor device of the first aspect of the present invention, high integration can be achieved without performing scaling in consideration of an error as in the prior art, and the channel layer can be thinned. Therefore, the speed can be easily increased. Moreover, since the channel layer is made of a substance that allows electrons to move at high speed between the source and the drain, higher speed can be realized.

According to the semiconductor device of the second aspect, it is possible to configure a logic circuit using a large number of semiconductor elements with a small number of semiconductor elements. According to the semiconductor device of the third aspect, since the gate voltage can be applied from three directions, it is possible to suppress the variation of the S factor of the semiconductor element and suppress the short channel effect even if the size of the semiconductor element is reduced. Therefore, the channel length can be shortened to reduce the size of the transistor, which not only contributes to high integration, but also speeds up the device.

According to the semiconductor device of the fourth aspect, the number of the gate electrode lead-out portions can be further increased to four or more by making the shape of the operation region of the semiconductor element square or more or circular. Therefore, it becomes possible to form four or more gate electrodes for one semiconductor element,
A single semiconductor element can form a logic circuit having four or more gates.

According to the manufacturing method of the fifth aspect, the material gas source-channel-is formed when the active region of the semiconductor device is formed.
The drain can be formed in a single process, which leads to simplification of the manufacturing process. In addition, since a high temperature treatment is not performed in a step after formation of an operating region of a transistor, a substance which moves electrons at high speed between a source and a drain can be used for a channel layer.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor device in the order of steps.

FIG. 3 is a sectional view showing the continuation of FIG. 2 in the order of steps.

FIG. 4 is a sectional view showing the continuation of FIG. 3 in the order of steps.

FIG. 5 is a sectional view showing the continuation of FIG. 4 in the order of steps.

FIG. 6 is a sectional view showing the continuation of FIG. 5 in the order of steps.

FIG. 7 is a diagram showing an arrangement of a source electrode, a drain electrode, and a gate electrode when a gate electrode extraction portion is arranged so as to surround three side surfaces of a channel layer and the gate electrode is connected to the gate electrode extraction portion. ..

FIG. 8 is a source electrode in the case where a source electrode lead-out portion is formed in contact with the source layer in the lateral direction and extends over the diffusion layer, and four gate electrode lead-out portions are provided for one channel layer. FIG. 6 is a diagram showing the arrangement of drain electrodes and gate electrodes.

FIG. 9 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

 20 Silicon Substrate 21 Source Layer 22 Channel Layer 23 Drain Layer 24 Diffusion Layer 25 Gate Insulating Film 26 Gate Electrode Extraction Part 27, 29, 32 Contact Hole 28 Gate Electrode 30 Drain Electrode 31 Source Electrode Extraction Part 33 Source Electrode 34A, 34B, 35C Insulating film 37, 39, 40, 41, 42 Resist 38 Polysilicon 43 Conductive thin film

Claims (5)

[Claims] 1. A source layer, a channel layer, and a drain layer, which are to be an operating region of a semiconductor device, are vertically formed on a semiconductor substrate, and the channel layer is a material that moves electrons between the source layer and the drain layer at high speed. And a gate insulating film is formed on a side wall of the channel layer, and a gate electrode lead-out portion is formed so as to be connected to the channel layer through the gate insulating film. 2. The semiconductor device according to claim 1, wherein a plurality of gate electrode lead-out portions are provided for one channel layer, and a gate electrode is connected to each gate electrode lead-out portion. apparatus. 3. The semiconductor device according to claim 1, wherein a gate electrode lead-out portion is arranged so as to surround three side surfaces of the channel layer, and the gate electrode is connected to the gate electrode lead-out portion. Semiconductor device. 4. A semiconductor device according to claim 1, wherein a diffusion layer is formed below the source layer in contact with the source layer and extended laterally as much as necessary, and the extended diffusion is formed. A semiconductor device, wherein a source electrode extraction portion is formed on a layer upper portion. 5. A step of forming an insulating film on a semiconductor substrate, a resist is applied on the insulating film leaving a diffusion layer forming region,
A step of diffusing impurities to form a diffusion layer on the surface of the semiconductor substrate, a step of laterally growing the remaining insulating film after removing the resist, and an insulation grown in the above step leaving the source electrode extraction region. A step of applying a resist on the film and exposing the diffusion layer by etching; a step of removing the resist and then depositing polysilicon on the insulating film so as to cover the diffusion layer exposed in the above step; The process of applying a resist on the polysilicon remaining, exposing the growth insulating film by etching, and forming the gate electrode extraction part and the source electrode extraction part separately, after removing the resist, exposing it in the above process A step of depositing an insulating film on the gate electrode lead-out portion and the source electrode lead-out portion so as to cover the grown insulating film, A step of applying a resist on the insulating film and exposing the diffusion layer by etching, a step of removing the resist, and then forming a gate insulating film on the diffusion layer exposed in the step and a sidewall of the etching surface by thermal oxidation, A step of applying a resist on the deposited insulating film and the gate insulating film on the side wall of the etching surface while leaving the gate insulating film on the diffusion layer, and removing the gate insulating film on the diffusion layer by etching to expose the diffusion layer, A step of continuously forming a source layer, a channel layer, and a drain layer in the vertical direction while changing the material gas on the diffusion layer exposed by the step, a step of further depositing an insulating film on the drain layer and the deposited insulating film, a gate , The source and drain electrode formation regions are left, and a resist is applied on the insulating film deposited in the above step, and the gate electrode extraction portion and A step of exposing the source electrode extraction part and the drain layer, and a step of forming a gate electrode on the gate electrode extraction part, a source electrode on the source electrode extraction part, and a drain electrode on the drain layer. And a method for manufacturing a semiconductor device.