JPH0555589A - Insulated-gate field-effect transistor and its manufacture - Google Patents
Insulated-gate field-effect transistor and its manufactureInfo
- Publication number
- JPH0555589A JPH0555589A JP3218866A JP21886691A JPH0555589A JP H0555589 A JPH0555589 A JP H0555589A JP 3218866 A JP3218866 A JP 3218866A JP 21886691 A JP21886691 A JP 21886691A JP H0555589 A JPH0555589 A JP H0555589A
- Authority
- JP
- Japan
- Prior art keywords
- film
- oxide film
- forming
- nitride film
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 19
- 230000005669 field effect Effects 0.000 title claims description 9
- 238000009792 diffusion process Methods 0.000 claims abstract description 47
- 150000004767 nitrides Chemical class 0.000 claims abstract description 40
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 18
- 230000003647 oxidation Effects 0.000 claims description 17
- 238000007254 oxidation reaction Methods 0.000 claims description 17
- 239000004065 semiconductor Substances 0.000 claims description 16
- 238000001259 photo etching Methods 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 238000009413 insulation Methods 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 31
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
-
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
-
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
-
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- H01—ELECTRIC ELEMENTS
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H01L29/402—Field plates
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は絶縁ゲート形電界効果ト
ランジスタに係り、特にパワーＭＯＳＦＥＴ等に好適な
縦型の絶縁ゲート形電界効果トランジスタに関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an insulated gate field effect transistor, and more particularly to a vertical insulated gate field effect transistor suitable for power MOSFETs and the like.
【０００２】[0002]
【従来の技術】図１０は従来の縦型絶縁ゲート形電界効
果トランジスタ（以下、ＭＯＳＦＥＴという）のセル部
分の断面図である。符号１はＮ型の半導体基板であり、
ＭＯＳＦＥＴのドレイン領域を形成する。符号２はＰ+
型の縦型ＭＯＳＦＥＴのチャンネル拡散領域である。符
号３は、チャンネル拡散領域２内に設けられたＮ+ 型の
拡散層であり、ソース拡散領域を形成する。符号４は薄
い酸化膜からなるゲート絶縁膜であり、符号５は多結晶
シリコン膜からなるゲート電極であり、このゲート電極
５に電圧が印加されることによって、ソース拡散領域３
とドレイン領域１とがゲート絶縁膜４を介して導通が制
御される。符号９は酸化膜等からなる層間絶縁膜であ
り、符号１０はアルミ膜等の金属電極であり、ＭＯＳＦ
ＥＴのソース電極等を形成する。このような縦型のＭＯ
ＳＦＥＴは、高耐圧、大電流を取扱うパワーＭＯＳＦＥ
Ｔに好適な構造である。2. Description of the Related Art FIG. 10 is a sectional view of a cell portion of a conventional vertical insulated gate field effect transistor (hereinafter referred to as MOSFET). Reference numeral 1 is an N-type semiconductor substrate,
Form the drain region of the MOSFET. Code 2 is P +
Type vertical MOSFET channel diffusion region. Reference numeral 3 is an N + type diffusion layer provided in the channel diffusion region 2 and forms a source diffusion region. Reference numeral 4 is a gate insulating film made of a thin oxide film, and reference numeral 5 is a gate electrode made of a polycrystalline silicon film. By applying a voltage to the gate electrode 5, the source diffusion region 3 is formed.
Conduction between the drain region 1 and the drain region 1 is controlled via the gate insulating film 4. Reference numeral 9 is an interlayer insulating film made of an oxide film or the like, reference numeral 10 is a metal electrode such as an aluminum film, and the like.
A source electrode of ET and the like are formed. Vertical MO like this
SFET is a power MOSFET that handles high withstand voltage and large current.
This structure is suitable for T.
【０００３】しかしながら、係る図１のような構造のＭ
ＯＳＦＥＴにおいては、ゲート電極５が薄いゲート絶縁
膜４を介して直接ドレイン領域である半導体基板１に対
面しているので、ＭＯＳＦＥＴのゲートドレイン間の帰
還容量及びゲートソース間の入力容量が大きくなり、ス
イッチングスピードが遅くなるという問題がある。又ド
レイン領域は低濃度のＮ型半導体基板であるため、パワ
ーＭＯＳＦＥＴにおいては、ＯＮ抵抗が大きくなるとい
う問題がある。この点を解決するために、ゲート絶縁膜
４をドレイン領域上において厚く形成することにより容
量を低減し、且つその厚いゲート絶縁膜直下のドレイン
領域の濃度を高くすることによりＯＮ抵抗を低減するこ
とが、特開昭６３−２１８７６号公報、特開平２−３７
７７７号公報等に開示されている。However, the M having the structure as shown in FIG.
In the OSFET, since the gate electrode 5 directly faces the semiconductor substrate 1, which is the drain region, through the thin gate insulating film 4, the feedback capacitance between the gate and drain of the MOSFET and the input capacitance between the gate and source become large, There is a problem that the switching speed becomes slow. Further, since the drain region is a low-concentration N-type semiconductor substrate, there is a problem that the ON resistance becomes large in the power MOSFET. To solve this problem, the gate insulating film 4 is formed thick on the drain region to reduce the capacitance, and the drain region directly below the thick gate insulating film is increased in concentration to reduce the ON resistance. However, JP-A-63-21876 and JP-A-2-37
No. 777, etc.
【０００４】[0004]
【発明が解決しようとする課題】前述のように図３に開
示された従来の構造では、ゲート電極とドレイン領域が
薄い絶縁膜を介して直接対向しているため、入力容量、
帰還容量が大きくなるという問題があり、且つドレイン
領域でのＯＮ抵抗が大きくなるという問題があった。
又、前述の特開昭６３−２１８７６号公報、特開平２−
３７７７７号公報に開示されたＭＯＳＦＥＴでは、ゲー
ト絶縁膜としては酸化膜が用いられているため、信頼性
に問題があり、又その製造工程が複雑となるという問題
があった。As described above, in the conventional structure disclosed in FIG. 3, since the gate electrode and the drain region directly face each other through the thin insulating film, the input capacitance,
There is a problem that the feedback capacitance becomes large, and a problem that the ON resistance in the drain region becomes large.
Further, the above-mentioned JP-A-63-21876 and JP-A-2-
In the MOSFET disclosed in Japanese Patent No. 37777, since an oxide film is used as a gate insulating film, there is a problem in reliability and a problem that the manufacturing process is complicated.
【０００５】[0005]
【課題を解決するための手段】本発明は、かかる縦型の
ＭＯＳＦＥＴにおいて、チャンネル拡散領域の上に設け
られたゲート絶縁膜を酸化膜／窒化膜／酸化膜の三層構
造とし、窒化膜の選択酸化による厚い酸化膜をドレイン
領域上に形成したものである。そしてその製造方法を、
半導体基板上に酸化膜と窒化膜の二層膜を形成すること
により、窒化膜の選択酸化により厚い酸化膜をドレイン
領域上に形成すると共に、該窒化膜上に薄い酸化膜を形
成するようにしたものである。更に、半導体基板上のフ
ィールド領域に形成されるフィールド窒化膜は、ゲート
絶縁膜の窒化膜の形成と同時にするようにしたものであ
る。又、窒化膜の選択酸化による厚い酸化膜形成と同時
に、拡散により高濃度の拡散層をドレイン領域の厚い酸
化膜の下に形成するようにしたものである。According to the present invention, in such a vertical MOSFET, the gate insulating film provided on the channel diffusion region has a three-layer structure of oxide film / nitride film / oxide film, A thick oxide film formed by selective oxidation is formed on the drain region. And the manufacturing method,
By forming a two-layer film of an oxide film and a nitride film on a semiconductor substrate, a thick oxide film is formed on the drain region by selective oxidation of the nitride film, and a thin oxide film is formed on the nitride film. It was done. Further, the field nitride film formed in the field region on the semiconductor substrate is formed simultaneously with the formation of the nitride film of the gate insulating film. Further, at the same time as forming a thick oxide film by selective oxidation of the nitride film, a high-concentration diffusion layer is formed by diffusion under the thick oxide film in the drain region.
【０００６】[0006]
【作用】本発明においては、ゲート絶縁膜として、酸化
膜／窒化膜／酸化膜の三層構造を採用しているため、信
頼性の高い縦型のＭＯＳＦＥＴが提供される。又窒化膜
の選択酸化によりドレイン領域上に厚い酸化膜を形成す
ることにより、ＭＯＳＦＥＴの入力容量及び帰還容量を
低減できる。さらに選択酸化に先立って基板と同一導電
型の不純物をデポジションし、選択酸化と共に拡散する
ことによって、高濃度の拡散層をドレイン領域に形成す
ることができ、ＭＯＳＦＥＴのＯＮ抵抗を減少させるこ
とができる。さらにフィールド窒化膜の形成を、ゲート
絶縁膜の形成と同時に行うことができるので、この製造
方法によれば、特に工程数を増やすことなく上述のＭＯ
ＳＦＥＴを製造することができる。In the present invention, since the gate insulating film has a three-layer structure of oxide film / nitride film / oxide film, a highly reliable vertical MOSFET is provided. Further, by forming a thick oxide film on the drain region by selective oxidation of the nitride film, the input capacitance and feedback capacitance of the MOSFET can be reduced. Further, by depositing impurities of the same conductivity type as the substrate prior to the selective oxidation and diffusing with the selective oxidation, a high-concentration diffusion layer can be formed in the drain region, and the ON resistance of the MOSFET can be reduced. it can. Further, since the field nitride film can be formed simultaneously with the formation of the gate insulating film, according to this manufacturing method, the above-mentioned MO process can be performed without increasing the number of steps.
SFETs can be manufactured.
【０００７】[0007]
【実施例】図１は、本発明の一実施例のＭＯＳＦＥＴの
断面図である。符号１はＮ型の半導体基板であり、ＭＯ
ＳＦＥＴのドレイン領域を構成する。このＮ型の半導体
基板１の下には、図示しない高濃度のＮ+ の半導体基板
があり、その下部よりドレイン電極が取り出される。符
号２はＰ+ 型のチャンネル拡散領域であり、符号３はチ
ャンネル拡散領域２内に設けられたＮ+型のソース拡散
領域である。符号１１はドレイン領域に設けられた高濃
度のＮ+型の拡散層であり、ＭＯＳＦＥＴのＯＮ抵抗を
下げるためのものである。符号４はゲート絶縁膜であ
り、酸化膜６／窒化膜７／酸化膜８の三層構造となって
いる。ここで酸化膜８は、厚い酸化膜１２を選択酸化に
より形成する時に、窒化膜７の上に形成される数十オン
グストローム程度の薄い酸化膜である。符号５は多結晶
シリコンからなるゲート電極である。チャンネル拡散領
域２とソース拡散領域３とはこの多結晶シリコンのゲー
ト電極５をマクスとしてセルフアラインにより二重拡散
により形成される。符号９は酸化膜などの層間絶縁膜で
あり、符号１０はアルミ蒸着膜等の金属電極であり、ソ
ース電極等を構成する。1 is a sectional view of a MOSFET according to an embodiment of the present invention. Reference numeral 1 is an N-type semiconductor substrate, and MO
It constitutes the drain region of the SFET. Under this N-type semiconductor substrate 1, there is a high-concentration N + semiconductor substrate (not shown), and the drain electrode is taken out from the lower part thereof. Reference numeral 2 is a P + -type channel diffusion region, and reference numeral 3 is an N + -type source diffusion region provided in the channel diffusion region 2. Reference numeral 11 is a high-concentration N + type diffusion layer provided in the drain region, and is for reducing the ON resistance of the MOSFET. Reference numeral 4 is a gate insulating film, which has a three-layer structure of oxide film 6 / nitride film 7 / oxide film 8. Here, the oxide film 8 is a thin oxide film of about several tens of angstroms formed on the nitride film 7 when the thick oxide film 12 is formed by selective oxidation. Reference numeral 5 is a gate electrode made of polycrystalline silicon. The channel diffusion region 2 and the source diffusion region 3 are formed by double diffusion by self-alignment using the polycrystalline silicon gate electrode 5 as a mask. Reference numeral 9 is an interlayer insulating film such as an oxide film, reference numeral 10 is a metal electrode such as an aluminum vapor deposition film, and constitutes a source electrode or the like.
【０００８】このような構造によれば、厚い酸化膜１２
がドレイン領域上に形成されているため、ＭＯＳＦＥＴ
のゲート電極５が直接ドレイン領域に対面せず、入力容
量、帰還容量が図３に示す従来の構造と比較して大幅に
減少する。そしてドレイン領域には高濃度の拡散層１１
が設けられているため、ＭＯＳＦＥＴのＯＮ抵抗が減少
する。そしてゲート絶縁膜４は酸化膜６／窒化膜７／酸
化膜８の三層構造となっているため、特に、窒化膜７お
よびその上に熱酸化により形成された薄い酸化膜８によ
り極めて信頼性が高い。According to such a structure, the thick oxide film 12 is formed.
MOSFET is formed on the drain region,
Since the gate electrode 5 does not directly face the drain region, the input capacitance and the feedback capacitance are significantly reduced as compared with the conventional structure shown in FIG. Then, a high concentration diffusion layer 11 is formed in the drain region.
Is provided, the ON resistance of the MOSFET is reduced. Since the gate insulating film 4 has a three-layer structure of the oxide film 6 / nitride film 7 / oxide film 8, the nitride film 7 and the thin oxide film 8 formed thereon by thermal oxidation are extremely reliable. Is high.
【０００９】このＭＯＳＦＥＴの製造方法の一実施例に
ついて、以下に、図２から図９のＭＯＳＦＥＴの製造工
程の断面図に従って説明する。まず、Ｎ+型基体（図示
していない）の上にＮ型のエピタキシャル層を備えた半
導体基板１を準備し、Ｐ型の深い拡散領域であるセル間
の分離のための拡散層１４及びガードリング拡散層１５
を形成する。これは熱酸化により酸化膜１７を成長さ
せ、ホトエッチにより開口し、ボロンをデポジション又
はイオン注入し熱処理によって拡散層を形成する。次に
Ｎ+ 型の深い拡散層であるチップ端部のアニュラー拡散
層１８を形成する。これは酸化膜１７をホトエッチで開
口し、リンをデポジションしドライブインすることによ
って深い高濃度の拡散層を形成する。そして、ＭＯＳＦ
ＥＴのセル部分２０の酸化膜１７をホトエッチにより開
口する（図２）。An embodiment of the method of manufacturing the MOSFET will be described below with reference to sectional views of the manufacturing process of the MOSFET shown in FIGS. First, a semiconductor substrate 1 having an N type epitaxial layer on an N + type substrate (not shown) is prepared, and a diffusion layer 14 and a guard for separating cells, which are P type deep diffusion regions, are provided. Ring diffusion layer 15
To form. This grows an oxide film 17 by thermal oxidation, opens it by photoetching, deposits or ion-implants boron, and forms a diffusion layer by heat treatment. Next, an annular diffusion layer 18 at the end of the chip, which is an N + type deep diffusion layer, is formed. This forms a deep high-concentration diffusion layer by opening the oxide film 17 by photoetching, depositing phosphorus and driving in. And MOSF
The oxide film 17 of the cell portion 20 of the ET is opened by photoetching (FIG. 2).
【００１０】次に、ゲート絶縁膜およびフィールド窒化
膜となる酸化膜と窒化膜の二層膜２１を形成する。ま
ず、熱酸化によって厚さ数百オングストローム程度の酸
化膜を形成して、その上に窒化膜をＣＶＤにより数百オ
ングストローム程度形成する（図３）。そして二層膜２
１の窒化膜をホトエッチにより開口し、セル部分２０の
ＭＯＳＦＥＴのゲート絶縁膜形成と同時に、チップ周辺
のフィールド部分に、パッシベーションのためのフィー
ルド窒化膜２２を形成する（図４）。。この様にフィー
ルド窒化膜をゲート絶縁膜と同時に形成することによ
り、特別のフィールド窒化膜のための処理が不要とな
り、工程が短縮される。Next, a two-layer film 21 of an oxide film and a nitride film to be a gate insulating film and a field nitride film is formed. First, an oxide film with a thickness of about several hundred angstroms is formed by thermal oxidation, and a nitride film is formed thereon with a thickness of about several hundred angstroms by CVD (FIG. 3). And the two-layer film 2
The first nitride film is opened by photoetching, and at the same time when the MOSFET gate insulating film in the cell portion 20 is formed, the field nitride film 22 for passivation is formed in the field portion around the chip (FIG. 4). .. By forming the field nitride film at the same time as the gate insulating film in this way, a special process for the field nitride film is unnecessary, and the process is shortened.
【００１１】次に、ドレイン領域の高濃度Ｎ+ 拡散層１
１の形成と、厚い酸化膜１２の形成を行う。図４におけ
る二層膜２１の開口部にリンをイオン注入し、窒化膜を
マスクとする選択酸化（ＬＯＣＯＳ）によって膜厚１ミ
クロン程度の厚い酸化膜１２を形成する。同時に、厚い
酸化膜の形成のための熱処理によって、イオン注入され
たリンが拡散され厚い酸化膜１２の下に、深いＮ+型の
拡散層１１が形成される（図５）。この厚い酸化膜１２
は、後に形成されるゲート電極直下に位置し、ゲート電
極を半導体基板１のドレイン領域から離すことにより、
ＭＯＳＦＥＴの入力容量、帰還容量を減少させる。深い
Ｎ+型の拡散層１１は、同様に後に形成されるゲート電
極直下のドレイン領域に位置し、ＭＯＳＦＥＴのＯＮ抵
抗を減少させる。また、二層膜２１は、酸化膜６／窒化
膜７／酸化膜８の三層膜２３となる。ここで最上層の酸
化膜８は、厚い酸化膜１２を選択酸化（ＬＯＣＯＳ）に
より形成する時に、窒化膜７の上に形成される数十オン
グストローム程度の薄い酸化膜である。Next, the high-concentration N + diffusion layer 1 in the drain region 1
1 and the thick oxide film 12 are formed. Phosphorus is ion-implanted into the opening of the two-layer film 21 in FIG. 4, and a thick oxide film 12 having a thickness of about 1 micron is formed by selective oxidation (LOCOS) using the nitride film as a mask. At the same time, by heat treatment for forming a thick oxide film, the ion-implanted phosphorus is diffused and a deep N + type diffusion layer 11 is formed under the thick oxide film 12 (FIG. 5). This thick oxide film 12
Is located immediately below the gate electrode to be formed later, and by separating the gate electrode from the drain region of the semiconductor substrate 1,
The input capacitance and feedback capacitance of the MOSFET are reduced. The deep N + type diffusion layer 11 is located in the drain region directly below the gate electrode which is also formed later, and reduces the ON resistance of the MOSFET. The two-layer film 21 becomes a three-layer film 23 of oxide film 6 / nitride film 7 / oxide film 8. Here, the uppermost oxide film 8 is a thin oxide film of about several tens of angstroms formed on the nitride film 7 when the thick oxide film 12 is formed by selective oxidation (LOCOS).
【００１２】そして、多結晶シリコン膜をＣＶＤによっ
て全面に成長させる。そしてホトエッチによってゲート
電極５を形成する（図６）。Ｐ型拡散層であるチャンネ
ル拡散領域２及びＮ+型拡散層であるソース拡散領域３
を二重にゲート電極５およびホトレジストをマスクとし
て拡散により形成する（図７）。この拡散は、まずボロ
ンをゲート電極５のセルフアラインにより、三層膜２３
を通してイオン注入し、熱処理により、チャンネル拡散
領域２の拡散層が形成される。つぎに、レジストおよび
ゲート電極をマスクとして、同様にリンのイオン注入と
拡散により、ソース拡散領域３を形成する。そして全面
にＣＶＤによってリンドープの酸化膜を形成する。この
リンドープ酸化膜（ＰＳＧ）は、多結晶シリコンによる
ゲート電極５とその上に配線されるアルミ等の金属電極
との層間絶縁膜９となる。そしてソース拡散領域へのソ
ースコンタクト等をドライホトエッチによって開口する
（図８）。最後に、アルミ蒸着によりアルミ膜を全面に
形成し、ホトエッチによりアルミの金属電極１０を形成
して、ＭＯＳＦＥＴが完成する。Then, a polycrystalline silicon film is grown on the entire surface by CVD. Then, the gate electrode 5 is formed by photoetching (FIG. 6). A channel diffusion region 2 which is a P type diffusion layer and a source diffusion region 3 which is an N + type diffusion layer.
Are doubly formed by diffusion using the gate electrode 5 and the photoresist as a mask (FIG. 7). In this diffusion, first, boron is self-aligned with the gate electrode 5 to form the three-layer film 23.
Ion implantation is performed through and heat treatment is performed to form a diffusion layer of the channel diffusion region 2. Next, using the resist and the gate electrode as a mask, the source diffusion region 3 is similarly formed by ion implantation and diffusion of phosphorus. Then, a phosphorus-doped oxide film is formed on the entire surface by CVD. The phosphorus-doped oxide film (PSG) serves as an interlayer insulating film 9 between the gate electrode 5 made of polycrystalline silicon and the metal electrode such as aluminum to be wired thereon. Then, a source contact or the like to the source diffusion region is opened by dry photoetching (FIG. 8). Finally, an aluminum film is formed on the entire surface by aluminum vapor deposition, and an aluminum metal electrode 10 is formed by photoetching to complete the MOSFET.
【００１３】[0013]
【発明の効果】本発明においては、ゲート絶縁膜とし
て、酸化膜／窒化膜／酸化膜の三層構造を採用している
ため、ゲートソース間絶縁破壊の時間依存性など、信頼
性の高い縦型のＭＯＳＦＥＴが提供される。又窒化膜の
選択酸化によりドレイン領域上に厚い酸化膜を形成して
いるので、ＭＯＳＦＥＴの入力容量及び帰還容量が減少
される。さらに選択酸化と共に、Ｎ型の高濃度の不純物
を拡散することによって、ドレイン領域に高濃度の拡散
層を形成することができ、ＭＯＳＦＥＴのＯＮ抵抗を減
少させることができる。さらにこの製造方法によれば、
従来の窒化膜による選択酸化を用いた工程と同じであ
り、特に工程数を増やすことなくセル周辺のフィールド
領域にフィールド窒化膜を形成することができる。According to the present invention, since the gate insulating film has a three-layer structure of oxide film / nitride film / oxide film, it has a highly reliable vertical structure such as the time dependence of the gate-source dielectric breakdown. Type MOSFETs are provided. Further, since the thick oxide film is formed on the drain region by the selective oxidation of the nitride film, the input capacitance and the feedback capacitance of the MOSFET are reduced. Further, a high-concentration diffusion layer can be formed in the drain region by diffusing the N-type high-concentration impurity together with the selective oxidation, and the ON resistance of the MOSFET can be reduced. Furthermore, according to this manufacturing method,
This is the same as the conventional process using selective oxidation using a nitride film, and the field nitride film can be formed in the field region around the cell without particularly increasing the number of processes.
【図１】本発明の一実施例のＭＯＳＦＥＴの断面図であ
る。FIG. 1 is a cross-sectional view of a MOSFET according to an embodiment of the present invention.
【図２】本発明のＭＯＳＦＥＴの製造工程の一実施例を
示す断面図である。FIG. 2 is a cross-sectional view showing one embodiment of the manufacturing process of the MOSFET of the present invention.
【図３】本発明のＭＯＳＦＥＴの製造工程の一実施例を
示す断面図である。FIG. 3 is a cross-sectional view showing one embodiment of the manufacturing process of the MOSFET of the present invention.
【図４】本発明のＭＯＳＦＥＴの製造工程の一実施例を
示す断面図である。FIG. 4 is a cross-sectional view showing one embodiment of the manufacturing process of the MOSFET of the present invention.
【図５】本発明のＭＯＳＦＥＴの製造工程の一実施例を
示す断面図である。FIG. 5 is a cross-sectional view showing one embodiment of the manufacturing process of the MOSFET of the present invention.
【図６】本発明のＭＯＳＦＥＴの製造工程の一実施例を
示す断面図である。FIG. 6 is a cross-sectional view showing an embodiment of the manufacturing process of the MOSFET of the present invention.
【図７】本発明のＭＯＳＦＥＴの製造工程の一実施例を
示す断面図である。FIG. 7 is a cross-sectional view showing one example of a manufacturing process of the MOSFET of the present invention.
【図８】本発明のＭＯＳＦＥＴの製造工程の一実施例を
示す断面図である。FIG. 8 is a cross-sectional view showing an embodiment of the manufacturing process of the MOSFET of the present invention.
【図９】本発明のＭＯＳＦＥＴの製造工程の一実施例を
示す断面図である。FIG. 9 is a cross-sectional view showing one embodiment of the manufacturing process of the MOSFET of the present invention.
【図１０】従来のＭＯＳＦＥＴの断面図である。FIG. 10 is a cross-sectional view of a conventional MOSFET.
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 ＦＩ 技術表示箇所 // Ｈ０１Ｌ 21/318 Ｃ 8518−4Ｍ 9168−4Ｍ Ｈ０１Ｌ 29/78 ３２１ Ｙ ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Office reference number FI technical display location // H01L 21/318 C 8518-4M 9168-4M H01L 29/78 321 Y
Claims (4)
該半導体基板の表面に設けられたチャンネル拡散領域
と、該チャンネル拡散領域内に設けられたソース拡散領
域と、前記チャンネル拡散領域の上に設けられたゲート
絶縁膜を介して前記ドレイン領域と前記ソース領域の導
通を制御するゲート電極とからなる絶縁ゲート形電界効
果トランジスタにおいて、前記ゲート絶縁膜は、酸化膜
と窒化膜と酸化膜の三層構造であり、該窒化膜により選
択酸化された厚い酸化膜を前記ドレイン領域上に具備す
ることを特徴とする絶縁ゲート型電界効果トランジス
タ。1. A semiconductor substrate forming a drain region,
A channel diffusion region provided on the surface of the semiconductor substrate, a source diffusion region provided in the channel diffusion region, and the drain region and the source via a gate insulating film provided on the channel diffusion region. In an insulated gate field effect transistor including a gate electrode for controlling conduction of a region, the gate insulating film has a three-layer structure of an oxide film, a nitride film and an oxide film, and a thick oxide selectively oxidized by the nitride film. An insulated gate field effect transistor comprising a film on the drain region.
を形成する工程と、該二層膜をホトエッチによりパター
ンを形成する工程と、前記二層膜のパターンをマスクと
して選択酸化により厚い酸化膜を形成すると共に、前記
窒化膜上に薄い酸化膜を形成する工程と、多結晶シリコ
ン膜を形成する工程と、該多結晶シリコン膜をホトエッ
チによりゲート電極パターンを形成する工程と、該多結
晶シリコン膜をマスクとしてチャンネル領域及びソース
拡散領域を二重に拡散により形成する工程と、コンタク
ト開口を設け金属電極を形成する工程とからなることを
特徴とする絶縁ゲート形電界効果トランジスタの製造方
法。2. A step of forming a two-layer film of an oxide film and a nitride film on a semiconductor substrate, a step of forming a pattern of the two-layer film by photoetching, and a selective oxidation by using the pattern of the two-layer film as a mask. Forming a thick oxide film and forming a thin oxide film on the nitride film; forming a polycrystalline silicon film; forming a gate electrode pattern by photoetching the polycrystalline silicon film; Manufacture of an insulated gate field effect transistor characterized by comprising a step of double-diffusing a channel region and a source diffusion region using a polycrystalline silicon film as a mask, and a step of forming a contact opening and forming a metal electrode. Method.
成されるフィールド窒化膜は、前記ゲート絶縁膜の窒化
膜を形成し、ホトエッチによりパターンを形成する工程
と同時になされることを特徴とする請求項２の絶縁ゲー
ト形電界効果トランジスタの製造方法。3. The field nitride film formed in the field region on the semiconductor substrate is formed simultaneously with the step of forming a nitride film of the gate insulating film and forming a pattern by photoetching. 2. A method for manufacturing an insulated gate field effect transistor according to 2.
層膜を形成し、ホトエッチによりパターンを形成後、前
記半導体基板と同一型不純物をデポジションし、前記窒
化膜の選択酸化による厚い酸化膜形成と同時に、拡散に
より高濃度の拡散層を前記厚い酸化膜の下のドレイン領
域に形成することを特徴とする請求項２の絶縁ゲート形
電界効果トランジスタの製造方法。4. A two-layer film including an oxide film and a nitride film is formed on the semiconductor substrate, a pattern is formed by photoetching, impurities of the same type as those of the semiconductor substrate are deposited, and a thick film is formed by selective oxidation of the nitride film. 3. The method for manufacturing an insulated gate field effect transistor according to claim 2, wherein a high-concentration diffusion layer is formed in the drain region below the thick oxide film by diffusion simultaneously with the formation of the oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21886691A JP3162745B2 (en) | 1991-08-29 | 1991-08-29 | Method of manufacturing insulated gate field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21886691A JP3162745B2 (en) | 1991-08-29 | 1991-08-29 | Method of manufacturing insulated gate field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0555589A true JPH0555589A (en) | 1993-03-05 |
| JP3162745B2 JP3162745B2 (en) | 2001-05-08 |
Family
ID=16726538
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21886691A Expired - Fee Related JP3162745B2 (en) | 1991-08-29 | 1991-08-29 | Method of manufacturing insulated gate field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3162745B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0747968A1 (en) * | 1995-06-07 | 1996-12-11 | STMicroelectronics, Inc. | Structure and process for reducing the on-resistance of MOS-gated power devices |
| JP2001111052A (en) * | 1999-08-04 | 2001-04-20 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method thereof |
| WO2001045147A1 (en) * | 1999-12-15 | 2001-06-21 | Koninklijke Philips Electronics N.V. | Method of manufacturing a transistor |
-
1991
- 1991-08-29 JP JP21886691A patent/JP3162745B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0747968A1 (en) * | 1995-06-07 | 1996-12-11 | STMicroelectronics, Inc. | Structure and process for reducing the on-resistance of MOS-gated power devices |
| US5869371A (en) * | 1995-06-07 | 1999-02-09 | Stmicroelectronics, Inc. | Structure and process for reducing the on-resistance of mos-gated power devices |
| US6046473A (en) * | 1995-06-07 | 2000-04-04 | Stmicroelectronics, Inc. | Structure and process for reducing the on-resistance of MOS-gated power devices |
| JP2001111052A (en) * | 1999-08-04 | 2001-04-20 | Fuji Electric Co Ltd | Semiconductor device and manufacturing method thereof |
| WO2001045147A1 (en) * | 1999-12-15 | 2001-06-21 | Koninklijke Philips Electronics N.V. | Method of manufacturing a transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3162745B2 (en) | 2001-05-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |